1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2014  Ulrich Hecht
8 #include <linux/clk-provider.h>
24 #define CPG_FRQCRA	0x00
25 #define CPG_FRQCRB	0x04
26 #define CPG_SD0CKCR	0x74
27 #define CPG_SD1CKCR	0x78
28 #define CPG_SD2CKCR	0x7c
29 #define CPG_PLLECR	0xd0
30 #define CPG_PLL0CR	0xd8
31 #define CPG_PLL1CR	0x28
32 #define CPG_PLL2CR	0x2c
33 #define CPG_PLL3CR	0xdc
34 #define CPG_CKSCR	0xc0
35 #define CPG_DSI0PHYCR	0x6c
36 #define CPG_DSI1PHYCR	0x70
38 #define CLK_ENABLE_ON_INIT BIT(0)
41 	const char *name;  member
76 			     const char *name)  in sh73a0_cpg_register_clock()  argument
84 	if (!strcmp(name, "main")) {  in sh73a0_cpg_register_clock()
86 		u32 parent_idx = (readl(cpg->reg + CPG_CKSCR) >> 28) & 3;  in sh73a0_cpg_register_clock()
90 	} else if (!strncmp(name, "pll", 3)) {  in sh73a0_cpg_register_clock()
91 		void __iomem *enable_reg = cpg->reg;  in sh73a0_cpg_register_clock()
92 		u32 enable_bit = name[3] - '0';  in sh73a0_cpg_register_clock()
109 			return ERR_PTR(-EINVAL);  in sh73a0_cpg_register_clock()
111 		if (readl(cpg->reg + CPG_PLLECR) & BIT(enable_bit)) {  in sh73a0_cpg_register_clock()
118 	} else if (!strcmp(name, "dsi0phy") || !strcmp(name, "dsi1phy")) {  in sh73a0_cpg_register_clock()
119 		u32 phy_no = name[3] - '0';  in sh73a0_cpg_register_clock()
120 		void __iomem *dsi_reg = cpg->reg +  in sh73a0_cpg_register_clock()
129 	} else if (!strcmp(name, "z")) {  in sh73a0_cpg_register_clock()
136 		const struct div4_clk *c;  in sh73a0_cpg_register_clock()  local
138 		for (c = div4_clks; c->name; c++) {  in sh73a0_cpg_register_clock()
139 			if (!strcmp(name, c->name)) {  in sh73a0_cpg_register_clock()
140 				parent_name = c->parent;  in sh73a0_cpg_register_clock()
142 				reg = c->reg;  in sh73a0_cpg_register_clock()
143 				shift = c->shift;  in sh73a0_cpg_register_clock()
148 		if (!c->name)  in sh73a0_cpg_register_clock()
149 			return ERR_PTR(-EINVAL);  in sh73a0_cpg_register_clock()
153 		return clk_register_fixed_factor(NULL, name, parent_name, 0,  in sh73a0_cpg_register_clock()
156 		return clk_register_divider_table(NULL, name, parent_name, 0,  in sh73a0_cpg_register_clock()
157 						  cpg->reg + reg, shift, width, 0,  in sh73a0_cpg_register_clock()
158 						  table, &cpg->lock);  in sh73a0_cpg_register_clock()
169 	num_clks = of_property_count_strings(np, "clock-output-names");  in sh73a0_cpg_clocks_init()
184 	spin_lock_init(&cpg->lock);  in sh73a0_cpg_clocks_init()
186 	cpg->data.clks = clks;  in sh73a0_cpg_clocks_init()
187 	cpg->data.clk_num = num_clks;  in sh73a0_cpg_clocks_init()
189 	cpg->reg = of_iomap(np, 0);  in sh73a0_cpg_clocks_init()
190 	if (WARN_ON(cpg->reg == NULL))  in sh73a0_cpg_clocks_init()
194 	writel(0x108, cpg->reg + CPG_SD0CKCR);  in sh73a0_cpg_clocks_init()
195 	writel(0x108, cpg->reg + CPG_SD1CKCR);  in sh73a0_cpg_clocks_init()
196 	writel(0x108, cpg->reg + CPG_SD2CKCR);  in sh73a0_cpg_clocks_init()
199 		const char *name;  in sh73a0_cpg_clocks_init()  local
202 		of_property_read_string_index(np, "clock-output-names", i,  in sh73a0_cpg_clocks_init()
203 					      &name);  in sh73a0_cpg_clocks_init()
205 		clk = sh73a0_cpg_register_clock(np, cpg, name);  in sh73a0_cpg_clocks_init()
208 			       __func__, np, name, PTR_ERR(clk));  in sh73a0_cpg_clocks_init()
210 			cpg->data.clks[i] = clk;  in sh73a0_cpg_clocks_init()
213 	of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);  in sh73a0_cpg_clocks_init()
215 CLK_OF_DECLARE(sh73a0_cpg_clks, "renesas,sh73a0-cpg-clocks",