1 // SPDX-License-Identifier: GPL-2.0-or-later
5  * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
20  * - 2 oscillators: osc-26MHz, rtc-32.768KHz
21  * - 3 standard configurable plls: pll1, pll2 & pll3
22  * - 2 exclusive plls: usb phy pll and sata phy pll
23  * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
28  *     - dsp domain: gps, mf
29  *     - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
30  *     - sys domain: security
78 	u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -  in pll_clk_recalc_rate()
86 		u32 cfg0 = clkc_readl(clk->regofs);  in pll_clk_recalc_rate()
87 		u32 nf = (cfg0 & (BIT(13) - 1)) + 1;  in pll_clk_recalc_rate()
88 		u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;  in pll_clk_recalc_rate()
89 		u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;  in pll_clk_recalc_rate()
105 	rate = rate - rate % MHZ;  in pll_clk_round_rate()
139 		return -EINVAL;  in pll_clk_set_rate()
149 	reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);  in pll_clk_set_rate()
150 	clkc_writel(reg, clk->regofs);  in pll_clk_set_rate()
152 	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;  in pll_clk_set_rate()
153 	clkc_writel((nf >> 1) - 1, reg);  in pll_clk_set_rate()
155 	reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;  in pll_clk_set_rate()
285  * clock domains - cpu, mem, sys/io, dsp, gfx
299 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_get_parent()
306 	WARN_ON((cfg & (BIT(3) - 1)) > 4);  in dmn_clk_get_parent()
308 	return cfg & (BIT(3) - 1);  in dmn_clk_get_parent()
314 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_set_parent()
319 		return -EINVAL;  in dmn_clk_set_parent()
321 	cfg &= ~(BIT(3) - 1);  in dmn_clk_set_parent()
322 	clkc_writel(cfg | parent, clk->regofs);  in dmn_clk_set_parent()
323 	/* BIT(3) - switching status: 1 - busy, 0 - done */  in dmn_clk_set_parent()
324 	while (clkc_readl(clk->regofs) & BIT(3))  in dmn_clk_set_parent()
337 	u32 cfg = clkc_readl(clk->regofs);  in dmn_clk_recalc_rate()
346 		u32 wait = (cfg >> 16) & (BIT(4) - 1);  in dmn_clk_recalc_rate()
347 		u32 hold = (cfg >> 20) & (BIT(4) - 1);  in dmn_clk_recalc_rate()
359 	unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;  in dmn_clk_round_rate()
369 	wait = (ratio >> 1) - 1;  in dmn_clk_round_rate()
370 	hold = ratio - wait - 2;  in dmn_clk_round_rate()
382 	unsigned bits = (strcmp(name, "mem") == 0) ? 3 : 4;  in dmn_clk_set_rate()
388 		return -EINVAL;  in dmn_clk_set_rate()
392 	wait = (ratio >> 1) - 1;  in dmn_clk_set_rate()
393 	hold = ratio - wait - 2;  in dmn_clk_set_rate()
395 	reg = clkc_readl(clk->regofs);  in dmn_clk_set_rate()
396 	reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));  in dmn_clk_set_rate()
398 	clkc_writel(reg, clk->regofs);  in dmn_clk_set_rate()
401 	while (clkc_readl(clk->regofs) & BIT(25))  in dmn_clk_set_rate()
414 		ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);  in cpu_clk_set_rate()
419 		ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);  in cpu_clk_set_rate()
424 		ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);  in cpu_clk_set_rate()
428 	cur_parent = clk_get_parent(hw->clk);  in cpu_clk_set_rate()
432 		ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);  in cpu_clk_set_rate()
438 	ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);  in cpu_clk_set_rate()
452 	.name = "mem",
528 /* dsp, gfx, mm, lcd and vpp domain */
546 	.name = "gfx",
641 	bit = clk->enable_bit % 32;  in std_clk_is_enabled()
642 	reg = clk->enable_bit / 32;  in std_clk_is_enabled()
654 	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);  in std_clk_enable()
656 	bit = clk->enable_bit % 32;  in std_clk_enable()
657 	reg = clk->enable_bit / 32;  in std_clk_enable()
671 	BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);  in std_clk_disable()
673 	bit = clk->enable_bit % 32;  in std_clk_disable()
674 	reg = clk->enable_bit / 32;  in std_clk_disable()