Lines Matching +full:reg +full:- +full:init
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
20 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
21 * - 3 standard configurable plls: pll1, pll2 & pll3
22 * - 2 exclusive plls: usb phy pll and sata phy pll
23 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
28 * - dsp domain: gps, mf
29 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
30 * - sys domain: security
59 static inline unsigned long clkc_readl(unsigned reg) in clkc_readl() argument
61 return readl(sirfsoc_clk_vbase + reg); in clkc_readl()
64 static inline void clkc_writel(u32 val, unsigned reg) in clkc_writel() argument
66 writel(val, sirfsoc_clk_vbase + reg); in clkc_writel()
78 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - in pll_clk_recalc_rate()
86 u32 cfg0 = clkc_readl(clk->regofs); in pll_clk_recalc_rate()
87 u32 nf = (cfg0 & (BIT(13) - 1)) + 1; in pll_clk_recalc_rate()
88 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1; in pll_clk_recalc_rate()
89 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1; in pll_clk_recalc_rate()
105 rate = rate - rate % MHZ; in pll_clk_round_rate()
130 unsigned long fin, nf, nr, od, reg; in pll_clk_set_rate() local
139 return -EINVAL; in pll_clk_set_rate()
149 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19); in pll_clk_set_rate()
150 clkc_writel(reg, clk->regofs); in pll_clk_set_rate()
152 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; in pll_clk_set_rate()
153 clkc_writel((nf >> 1) - 1, reg); in pll_clk_set_rate()
155 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; in pll_clk_set_rate()
156 while (!(clkc_readl(reg) & BIT(6))) in pll_clk_set_rate()
220 .init = &clk_pll1_init,
227 .init = &clk_pll2_init,
234 .init = &clk_pll3_init,
244 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); in usb_pll_clk_enable() local
245 reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); in usb_pll_clk_enable()
246 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); in usb_pll_clk_enable()
256 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); in usb_pll_clk_disable() local
257 reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS); in usb_pll_clk_disable()
258 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); in usb_pll_clk_disable()
263 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL); in usb_pll_clk_recalc_rate() local
264 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ; in usb_pll_clk_recalc_rate()
281 .init = &clk_usb_pll_init,
285 * clock domains - cpu, mem, sys/io, dsp, gfx
299 u32 cfg = clkc_readl(clk->regofs); in dmn_clk_get_parent()
306 WARN_ON((cfg & (BIT(3) - 1)) > 4); in dmn_clk_get_parent()
308 return cfg & (BIT(3) - 1); in dmn_clk_get_parent()
314 u32 cfg = clkc_readl(clk->regofs); in dmn_clk_set_parent()
319 return -EINVAL; in dmn_clk_set_parent()
321 cfg &= ~(BIT(3) - 1); in dmn_clk_set_parent()
322 clkc_writel(cfg | parent, clk->regofs); in dmn_clk_set_parent()
323 /* BIT(3) - switching status: 1 - busy, 0 - done */ in dmn_clk_set_parent()
324 while (clkc_readl(clk->regofs) & BIT(3)) in dmn_clk_set_parent()
337 u32 cfg = clkc_readl(clk->regofs); in dmn_clk_recalc_rate()
346 u32 wait = (cfg >> 16) & (BIT(4) - 1); in dmn_clk_recalc_rate()
347 u32 hold = (cfg >> 20) & (BIT(4) - 1); in dmn_clk_recalc_rate()
369 wait = (ratio >> 1) - 1; in dmn_clk_round_rate()
370 hold = ratio - wait - 2; in dmn_clk_round_rate()
380 unsigned ratio, wait, hold, reg; in dmn_clk_set_rate() local
388 return -EINVAL; in dmn_clk_set_rate()
392 wait = (ratio >> 1) - 1; in dmn_clk_set_rate()
393 hold = ratio - wait - 2; in dmn_clk_set_rate()
395 reg = clkc_readl(clk->regofs); in dmn_clk_set_rate()
396 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20)); in dmn_clk_set_rate()
397 reg |= (wait << 16) | (hold << 20) | BIT(25); in dmn_clk_set_rate()
398 clkc_writel(reg, clk->regofs); in dmn_clk_set_rate()
401 while (clkc_readl(clk->regofs) & BIT(25)) in dmn_clk_set_rate()
414 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); in cpu_clk_set_rate()
419 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); in cpu_clk_set_rate()
424 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk); in cpu_clk_set_rate()
428 cur_parent = clk_get_parent(hw->clk); in cpu_clk_set_rate()
432 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk); in cpu_clk_set_rate()
438 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk); in cpu_clk_set_rate()
461 .init = &clk_mem_init,
476 .init = &clk_sys_init,
490 .init = &clk_io_init,
513 .init = &clk_cpu_init,
541 .init = &clk_dsp_init,
556 .init = &clk_gfx_init,
571 .init = &clk_mm_init,
591 .init = &clk_lcd_init,
606 .init = &clk_vpp_init,
637 u32 reg; in std_clk_is_enabled() local
641 bit = clk->enable_bit % 32; in std_clk_is_enabled()
642 reg = clk->enable_bit / 32; in std_clk_is_enabled()
643 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); in std_clk_is_enabled()
645 return !!(clkc_readl(reg) & BIT(bit)); in std_clk_is_enabled()
650 u32 val, reg; in std_clk_enable() local
654 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); in std_clk_enable()
656 bit = clk->enable_bit % 32; in std_clk_enable()
657 reg = clk->enable_bit / 32; in std_clk_enable()
658 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); in std_clk_enable()
660 val = clkc_readl(reg) | BIT(bit); in std_clk_enable()
661 clkc_writel(val, reg); in std_clk_enable()
667 u32 val, reg; in std_clk_disable() local
671 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63); in std_clk_disable()
673 bit = clk->enable_bit % 32; in std_clk_disable()
674 reg = clk->enable_bit / 32; in std_clk_disable()
675 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg); in std_clk_disable()
677 val = clkc_readl(reg) & ~BIT(bit); in std_clk_disable()
678 clkc_writel(val, reg); in std_clk_disable()
701 .init = &clk_cphif_init,
715 .init = &clk_dmac0_init,
729 .init = &clk_dmac1_init,
743 .init = &clk_audio_init,
757 .init = &clk_uart0_init,
771 .init = &clk_uart1_init,
785 .init = &clk_uart2_init,
799 .init = &clk_usp0_init,
813 .init = &clk_usp1_init,
827 .init = &clk_usp2_init,
841 .init = &clk_vip_init,
855 .init = &clk_spi0_init,
869 .init = &clk_spi1_init,
883 .init = &clk_tsc_init,
897 .init = &clk_i2c0_init,
911 .init = &clk_i2c1_init,
925 .init = &clk_pwmc_init,
939 .init = &clk_efuse_init,
953 .init = &clk_pulse_init,
971 .init = &clk_gps_init,
985 .init = &clk_mf_init,
1003 .init = &clk_security_init,
1021 .init = &clk_usb0_init,
1035 .init = &clk_usb1_init,