Lines Matching +full:i2c +full:- +full:gate
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
200 #define I2C(_name, _parents, _offset,\ macro
229 #define GATE(_name, _parent_name, \ macro
609 I2C("i2c1", mux_pllp_clkm, CLK_SOURCE_I2C1, 12, tegra_clk_i2c1),
610 I2C("i2c2", mux_pllp_clkm, CLK_SOURCE_I2C2, 54, tegra_clk_i2c2),
611 I2C("i2c3", mux_pllp_clkm, CLK_SOURCE_I2C3, 67, tegra_clk_i2c3),
612 I2C("i2c4", mux_pllp_clkm, CLK_SOURCE_I2C4, 103, tegra_clk_i2c4),
613 I2C("i2c5", mux_pllp_clkm, CLK_SOURCE_I2C5, 47, tegra_clk_i2c5),
614 I2C("i2c6", mux_pllp_clkm, CLK_SOURCE_I2C6, 166, tegra_clk_i2c6),
762 I2C("vii2c", mux_pllp_pllc_clkm, CLK_SOURCE_VI_I2C, 208, tegra_clk_vi_i2c),
773 GATE("rtc", "clk_32k", 4, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_rtc, 0),
774 GATE("timer", "clk_m", 5, 0, tegra_clk_timer, CLK_IS_CRITICAL),
775 GATE("isp", "clk_m", 23, 0, tegra_clk_isp, 0),
776 GATE("vcp", "clk_m", 29, 0, tegra_clk_vcp, 0),
777 GATE("ahbdma", "hclk", 33, 0, tegra_clk_ahbdma, 0),
778 GATE("apbdma", "pclk", 34, 0, tegra_clk_apbdma, 0),
779 GATE("kbc", "clk_32k", 36, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_kbc, 0),
781 * Critical for RAM re-repair operation, which must occur on resume
784 GATE("fuse", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse, CLK_IS_CRITICAL),
785 GATE("fuse_burn", "clk_m", 39, TEGRA_PERIPH_ON_APB, tegra_clk_fuse_burn, 0),
786 GATE("kfuse", "clk_m", 40, TEGRA_PERIPH_ON_APB, tegra_clk_kfuse, 0),
787 GATE("apbif", "clk_m", 107, TEGRA_PERIPH_ON_APB, tegra_clk_apbif, 0),
788 GATE("hda2hdmi", "clk_m", 128, TEGRA_PERIPH_ON_APB, tegra_clk_hda2hdmi, 0),
789 GATE("bsea", "clk_m", 62, 0, tegra_clk_bsea, 0),
790 GATE("bsev", "clk_m", 63, 0, tegra_clk_bsev, 0),
791 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
792 GATE("usbd", "clk_m", 22, 0, tegra_clk_usbd, 0),
793 GATE("usb2", "clk_m", 58, 0, tegra_clk_usb2, 0),
794 GATE("usb3", "clk_m", 59, 0, tegra_clk_usb3, 0),
795 GATE("csi", "pll_p_out3", 52, 0, tegra_clk_csi, 0),
796 GATE("afi", "mselect", 72, 0, tegra_clk_afi, 0),
797 GATE("csus", "clk_m", 92, TEGRA_PERIPH_NO_RESET, tegra_clk_csus, 0),
798 GATE("dds", "clk_m", 150, TEGRA_PERIPH_ON_APB, tegra_clk_dds, 0),
799 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
800 GATE("dtv", "clk_m", 79, TEGRA_PERIPH_ON_APB, tegra_clk_dtv, 0),
801 GATE("xusb_host", "xusb_host_src", 89, 0, tegra_clk_xusb_host, 0),
802 GATE("xusb_ss", "xusb_ss_src", 156, 0, tegra_clk_xusb_ss, 0),
803 GATE("xusb_dev", "xusb_dev_src", 95, 0, tegra_clk_xusb_dev, 0),
804 GATE("emc", "emc_mux", 57, 0, tegra_clk_emc, CLK_IS_CRITICAL),
805 GATE("sata_cold", "clk_m", 129, TEGRA_PERIPH_ON_APB, tegra_clk_sata_cold, 0),
806 GATE("ispa", "isp", 23, 0, tegra_clk_ispa, 0),
807 GATE("ispb", "isp", 3, 0, tegra_clk_ispb, 0),
808 GATE("vim2_clk", "clk_m", 11, 0, tegra_clk_vim2_clk, 0),
809 GATE("pcie", "clk_m", 70, 0, tegra_clk_pcie, 0),
810 GATE("gpu", "pll_ref", 184, 0, tegra_clk_gpu, 0),
811 GATE("pllg_ref", "pll_ref", 189, 0, tegra_clk_pll_g_ref, 0),
812 GATE("hsic_trk", "usb2_hsic_trk", 209, TEGRA_PERIPH_NO_RESET, tegra_clk_hsic_trk, 0),
813 GATE("usb2_trk", "usb2_hsic_trk", 210, TEGRA_PERIPH_NO_RESET, tegra_clk_usb2_trk, 0),
814 GATE("xusb_gate", "osc", 143, 0, tegra_clk_xusb_gate, 0),
815 GATE("pll_p_out_cpu", "pll_p", 223, 0, tegra_clk_pll_p_out_cpu, 0),
816 GATE("pll_p_out_adsp", "pll_p", 187, 0, tegra_clk_pll_p_out_adsp, 0),
817 GATE("apb2ape", "clk_m", 107, 0, tegra_clk_apb2ape, 0),
818 GATE("cec", "pclk", 136, 0, tegra_clk_cec, 0),
819 GATE("iqc1", "clk_m", 221, 0, tegra_clk_iqc1, 0),
820 GATE("iqc2", "clk_m", 220, 0, tegra_clk_iqc1, 0),
821 GATE("pll_a_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out_adsp, 0),
822 GATE("pll_a_out0_out_adsp", "pll_a", 188, 0, tegra_clk_pll_a_out0_out_adsp, 0),
823 GATE("adsp", "aclk", 199, 0, tegra_clk_adsp, 0),
824 GATE("adsp_neon", "aclk", 218, 0, tegra_clk_adsp_neon, 0),
877 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
881 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
885 data->periph.gate.regs = bank; in periph_clk_init()
903 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in gate_clk_init()
907 clk = tegra_clk_register_periph_gate(data->name, in gate_clk_init()
908 data->p.parent_name, data->periph.gate.flags, in gate_clk_init()
909 clk_base, data->flags, in gate_clk_init()
910 data->periph.gate.clk_num, in gate_clk_init()
928 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in div_clk_init()
932 clk = tegra_clk_register_divider(data->name, in div_clk_init()
933 data->p.parent_name, clk_base + data->offset, in div_clk_init()
934 data->flags, data->periph.divider.flags, in div_clk_init()
935 data->periph.divider.shift, in div_clk_init()
936 data->periph.divider.width, in div_clk_init()
937 data->periph.divider.frac_width, in div_clk_init()
938 data->periph.divider.lock); in div_clk_init()
965 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in init_pllp()
969 clk = tegra_clk_register_divider(data->div_name, "pll_p", in init_pllp()
970 clk_base + data->offset, 0, data->div_flags, in init_pllp()
971 data->div_shift, 8, 1, data->lock); in init_pllp()
972 clk = tegra_clk_register_pll_out(data->pll_out_name, in init_pllp()
973 data->div_name, clk_base + data->offset, in init_pllp()
974 data->rst_shift + 1, data->rst_shift, in init_pllp()
976 data->lock); in init_pllp()
985 * CPU, register a gate clock "pll_p_out_cpu" for this gating in init_pllp()
987 * re-parenting CPU off from "pll_p_out4" the PLLP branching to in init_pllp()