1 // SPDX-License-Identifier: GPL-2.0
5  *  Copyright (C) 2016-2019 Xilinx
7  * Adjustable divider clock implementation
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
16  * DOC: basic adjustable divider clock that cannot gate
18  * Traits of this clock:
19  * prepare - clk_prepare only ensures that parents are prepared
20  * enable - clk_enable only ensures that parents are enabled
21  * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
22  * parent - fixed parent.  No clk_set_parent support
32  * struct zynqmp_clk_divider - adjustable divider clock
33  * @hw:		handle between common and hardware-specific interfaces
36  * @clk_id:	Id of clock
64 		return (rate - up_rate) <= (down_rate - rate) ? up : down;  in zynqmp_divider_get_val()
72  * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
73  * @hw:			handle between common and hardware-specific interfaces
74  * @parent_rate:	rate of parent clock
83 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_recalc_rate()
84 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_recalc_rate()
85 	u32 div, value;  in zynqmp_clk_divider_recalc_rate()  local
88 	ret = zynqmp_pm_clock_getdivider(clk_id, &div);  in zynqmp_clk_divider_recalc_rate()
95 		value = div & 0xFFFF;  in zynqmp_clk_divider_recalc_rate()
97 		value = div >> 16;  in zynqmp_clk_divider_recalc_rate()
99 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_recalc_rate()
103 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),  in zynqmp_clk_divider_recalc_rate()
113  * zynqmp_clk_divider_round_rate() - Round rate of divider clock
114  * @hw:			handle between common and hardware-specific interfaces
115  * @rate:		rate of clock to be set
116  * @prate:		rate of parent clock
126 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_round_rate()
127 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_round_rate()
133 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in zynqmp_clk_divider_round_rate()
144 		if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_round_rate()
150 	width = fls(divider->max_div);  in zynqmp_clk_divider_round_rate()
152 	rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags);  in zynqmp_clk_divider_round_rate()
154 	if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate))  in zynqmp_clk_divider_round_rate()
161  * zynqmp_clk_divider_set_rate() - Set rate of divider clock
162  * @hw:			handle between common and hardware-specific interfaces
163  * @rate:		rate of clock to be set
164  * @parent_rate:	rate of parent clock
173 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_set_rate()
174 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_set_rate()
175 	u32 value, div;  in zynqmp_clk_divider_set_rate()  local
178 	value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);  in zynqmp_clk_divider_set_rate()
180 		div = value & 0xFFFF;  in zynqmp_clk_divider_set_rate()
181 		div |= 0xffff << 16;  in zynqmp_clk_divider_set_rate()
183 		div = 0xffff;  in zynqmp_clk_divider_set_rate()
184 		div |= value << 16;  in zynqmp_clk_divider_set_rate()
187 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_set_rate()
188 		div = __ffs(div);  in zynqmp_clk_divider_set_rate()
190 	ret = zynqmp_pm_clock_setdivider(clk_id, div);  in zynqmp_clk_divider_set_rate()
206  * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
207  * @clk_id:		Id of clock
210  * Return: Maximum divisor of a clock if query data is successful
234  * zynqmp_clk_register_divider() - Register a divider clock
235  * @name:		Name of this clock
236  * @clk_id:		Id of clock
237  * @parents:		Name of this clock's parents
239  * @nodes:		Clock topology node
241  * Return: clock hardware to registered clock divider
249 	struct zynqmp_clk_divider *div;  in zynqmp_clk_register_divider()  local
255 	div = kzalloc(sizeof(*div), GFP_KERNEL);  in zynqmp_clk_register_divider()
256 	if (!div)  in zynqmp_clk_register_divider()
257 		return ERR_PTR(-ENOMEM);  in zynqmp_clk_register_divider()
262 	init.flags = nodes->flag & ~CLK_FRAC;  in zynqmp_clk_register_divider()
267 	div->is_frac = !!((nodes->flag & CLK_FRAC) |  in zynqmp_clk_register_divider()
268 			  (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));  in zynqmp_clk_register_divider()
269 	div->flags = nodes->type_flag;  in zynqmp_clk_register_divider()
270 	div->hw.init = &init;  in zynqmp_clk_register_divider()
271 	div->clk_id = clk_id;  in zynqmp_clk_register_divider()
272 	div->div_type = nodes->type;  in zynqmp_clk_register_divider()
278 	div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type);  in zynqmp_clk_register_divider()
280 	hw = &div->hw;  in zynqmp_clk_register_divider()
283 		kfree(div);  in zynqmp_clk_register_divider()