Lines Matching +full:pll +full:- +full:clock +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0
3 * Zynq UltraScale+ MPSoC PLL driver
5 * Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14 * struct zynqmp_pll - PLL clock
15 * @hw: Handle between common and hardware-specific interfaces
16 * @clk_id: PLL clock ID
43 * zynqmp_pll_get_mode() - Get mode of PLL
44 * @hw: Handle between common and hardware-specific interfaces
46 * Return: Mode of PLL
51 u32 clk_id = clk->clk_id; in zynqmp_pll_get_mode()
58 pr_warn_once("%s() PLL get frac mode failed for %s, ret = %d\n", in zynqmp_pll_get_mode()
65 * zynqmp_pll_set_mode() - Set the PLL mode
66 * @hw: Handle between common and hardware-specific interfaces
72 u32 clk_id = clk->clk_id; in zynqmp_pll_set_mode()
84 pr_warn_once("%s() PLL set frac mode failed for %s, ret = %d\n", in zynqmp_pll_set_mode()
87 clk->set_pll_mode = true; in zynqmp_pll_set_mode()
91 * zynqmp_pll_round_rate() - Round a clock frequency
92 * @hw: Handle between common and hardware-specific interfaces
93 * @rate: Desired clock frequency
94 * @prate: Clock frequency of parent clock
96 * Return: Frequency closest to @rate the hardware can generate
124 * zynqmp_pll_recalc_rate() - Recalculate clock frequency
125 * @hw: Handle between common and hardware-specific interfaces
126 * @parent_rate: Clock frequency of parent clock
128 * Return: Current clock frequency
134 u32 clk_id = clk->clk_id; in zynqmp_pll_recalc_rate()
158 * zynqmp_pll_set_rate() - Set rate of PLL
159 * @hw: Handle between common and hardware-specific interfaces
160 * @rate: Frequency of clock to be set
161 * @parent_rate: Clock frequency of parent clock
163 * Set PLL divider to set desired rate.
171 u32 clk_id = clk->clk_id; in zynqmp_pll_set_rate()
188 if (ret == -EUSERS) in zynqmp_pll_set_rate()
210 * zynqmp_pll_is_enabled() - Check if a clock is enabled
211 * @hw: Handle between common and hardware-specific interfaces
213 * Return: 1 if the clock is enabled, 0 otherwise
219 u32 clk_id = clk->clk_id; in zynqmp_pll_is_enabled()
225 pr_warn_once("%s() clock get state failed for %s, ret = %d\n", in zynqmp_pll_is_enabled()
227 return -EIO; in zynqmp_pll_is_enabled()
234 * zynqmp_pll_enable() - Enable clock
235 * @hw: Handle between common and hardware-specific interfaces
243 u32 clk_id = clk->clk_id; in zynqmp_pll_enable()
247 * Don't skip enabling clock if there is an IOCTL_SET_PLL_FRAC_MODE request in zynqmp_pll_enable()
250 if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode)) in zynqmp_pll_enable()
253 clk->set_pll_mode = false; in zynqmp_pll_enable()
257 pr_warn_once("%s() clock enable failed for %s, ret = %d\n", in zynqmp_pll_enable()
264 * zynqmp_pll_disable() - Disable clock
265 * @hw: Handle between common and hardware-specific interfaces
271 u32 clk_id = clk->clk_id; in zynqmp_pll_disable()
279 pr_warn_once("%s() clock disable failed for %s, ret = %d\n", in zynqmp_pll_disable()
293 * zynqmp_clk_register_pll() - Register PLL with the clock framework
294 * @name: PLL name
295 * @clk_id: Clock ID
296 * @parents: Name of this clock's parents
298 * @nodes: Clock topology node
300 * Return: clock hardware to the registered clock
307 struct zynqmp_pll *pll; in zynqmp_clk_register_pll() local
314 init.flags = nodes->flag; in zynqmp_clk_register_pll()
318 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in zynqmp_clk_register_pll()
319 if (!pll) in zynqmp_clk_register_pll()
320 return ERR_PTR(-ENOMEM); in zynqmp_clk_register_pll()
322 pll->hw.init = &init; in zynqmp_clk_register_pll()
323 pll->clk_id = clk_id; in zynqmp_clk_register_pll()
325 hw = &pll->hw; in zynqmp_clk_register_pll()
328 kfree(pll); in zynqmp_clk_register_pll()