Lines Matching full:cmt
3 * SuperH Timer Support - CMT
36 * The CMT comes in 5 different identified flavours, depending not only on the
53 * registers block address. Some CMT instances have a subset of channels
61 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
92 struct sh_cmt_device *cmt; member
245 return ch->cmt->info->read_control(ch->iostart, 0); in sh_cmt_read_cmstr()
247 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); in sh_cmt_read_cmstr()
256 ch->cmt->info->write_control(ch->iostart, 0, value); in sh_cmt_write_cmstr()
257 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmstr()
259 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); in sh_cmt_write_cmstr()
260 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmstr()
267 return ch->cmt->info->read_control(ch->ioctrl, CMCSR); in sh_cmt_read_cmcsr()
275 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); in sh_cmt_write_cmcsr()
276 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmcsr()
282 return ch->cmt->info->read_count(ch->ioctrl, CMCNT); in sh_cmt_read_cmcnt()
288 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2); in sh_cmt_write_cmcnt()
291 if (ch->cmt->info->model > SH_CMT_16BIT) { in sh_cmt_write_cmcnt()
299 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); in sh_cmt_write_cmcnt()
306 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR); in sh_cmt_write_cmcor()
309 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); in sh_cmt_write_cmcor()
310 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmcor()
319 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
327 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
341 raw_spin_lock_irqsave(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
350 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
357 pm_runtime_get_sync(&ch->cmt->pdev->dev); in sh_cmt_enable()
358 dev_pm_syscore_device(&ch->cmt->pdev->dev, true); in sh_cmt_enable()
361 ret = clk_enable(ch->cmt->clk); in sh_cmt_enable()
363 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", in sh_cmt_enable()
372 if (ch->cmt->info->width == 16) { in sh_cmt_enable()
386 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", in sh_cmt_enable()
397 clk_disable(ch->cmt->clk); in sh_cmt_enable()
408 /* disable interrupts in CMT block */ in sh_cmt_disable()
412 clk_disable(ch->cmt->clk); in sh_cmt_disable()
414 dev_pm_syscore_device(&ch->cmt->pdev->dev, false); in sh_cmt_disable()
415 pm_runtime_put(&ch->cmt->pdev->dev); in sh_cmt_disable()
505 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", in sh_cmt_clock_event_program_verify()
514 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", in __sh_cmt_set_next()
536 ch->cmt->info->clear_bits); in sh_cmt_interrupt()
593 if (ch->cmt->num_channels == 1 && in sh_cmt_start()
632 if (ch->cmt->num_channels == 1) { in sh_cmt_clocksource_read()
685 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); in sh_cmt_clocksource_suspend()
695 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); in sh_cmt_clocksource_resume()
711 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); in sh_cmt_register_clocksource()
714 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", in sh_cmt_register_clocksource()
717 clocksource_register_hz(cs, ch->cmt->rate); in sh_cmt_register_clocksource()
731 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); in sh_cmt_clock_event_start()
753 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", in sh_cmt_clock_event_set_state()
787 pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev); in sh_cmt_clock_event_suspend()
788 clk_unprepare(ch->cmt->clk); in sh_cmt_clock_event_suspend()
795 clk_prepare(ch->cmt->clk); in sh_cmt_clock_event_resume()
796 pm_genpd_syscore_poweron(&ch->cmt->pdev->dev); in sh_cmt_clock_event_resume()
806 irq = platform_get_irq(ch->cmt->pdev, ch->index); in sh_cmt_register_clockevent()
812 dev_name(&ch->cmt->pdev->dev), ch); in sh_cmt_register_clockevent()
814 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", in sh_cmt_register_clockevent()
833 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); in sh_cmt_register_clockevent()
839 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", in sh_cmt_register_clockevent()
852 ch->cmt->has_clockevent = true; in sh_cmt_register()
859 ch->cmt->has_clocksource = true; in sh_cmt_register()
868 bool clocksource, struct sh_cmt_device *cmt) in sh_cmt_setup_channel() argument
877 ch->cmt = cmt; in sh_cmt_setup_channel()
887 switch (cmt->info->model) { in sh_cmt_setup_channel()
889 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; in sh_cmt_setup_channel()
893 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; in sh_cmt_setup_channel()
897 ch->iostart = cmt->mapbase + ch->hwidx * 0x100; in sh_cmt_setup_channel()
902 value = ioread32(cmt->mapbase + CMCLKE); in sh_cmt_setup_channel()
904 iowrite32(value, cmt->mapbase + CMCLKE); in sh_cmt_setup_channel()
908 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) in sh_cmt_setup_channel()
911 ch->max_match_value = (1 << cmt->info->width) - 1; in sh_cmt_setup_channel()
916 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), in sh_cmt_setup_channel()
919 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", in sh_cmt_setup_channel()
928 static int sh_cmt_map_memory(struct sh_cmt_device *cmt) in sh_cmt_map_memory() argument
932 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); in sh_cmt_map_memory()
934 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); in sh_cmt_map_memory()
938 cmt->mapbase = ioremap(mem->start, resource_size(mem)); in sh_cmt_map_memory()
939 if (cmt->mapbase == NULL) { in sh_cmt_map_memory()
940 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); in sh_cmt_map_memory()
948 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
949 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
957 .compatible = "renesas,cmt-48",
962 .compatible = "renesas,cmt-48-gen2",
993 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev) in sh_cmt_setup() argument
999 cmt->pdev = pdev; in sh_cmt_setup()
1000 raw_spin_lock_init(&cmt->lock); in sh_cmt_setup()
1003 cmt->info = of_device_get_match_data(&pdev->dev); in sh_cmt_setup()
1004 cmt->hw_channels = cmt->info->channels_mask; in sh_cmt_setup()
1009 cmt->info = (const struct sh_cmt_info *)id->driver_data; in sh_cmt_setup()
1010 cmt->hw_channels = cfg->channels_mask; in sh_cmt_setup()
1012 dev_err(&cmt->pdev->dev, "missing platform data\n"); in sh_cmt_setup()
1017 cmt->clk = clk_get(&cmt->pdev->dev, "fck"); in sh_cmt_setup()
1018 if (IS_ERR(cmt->clk)) { in sh_cmt_setup()
1019 dev_err(&cmt->pdev->dev, "cannot get clock\n"); in sh_cmt_setup()
1020 return PTR_ERR(cmt->clk); in sh_cmt_setup()
1023 ret = clk_prepare(cmt->clk); in sh_cmt_setup()
1028 ret = clk_enable(cmt->clk); in sh_cmt_setup()
1032 rate = clk_get_rate(cmt->clk); in sh_cmt_setup()
1039 if (cmt->info->model >= SH_CMT_48BIT) in sh_cmt_setup()
1040 cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate); in sh_cmt_setup()
1041 cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8); in sh_cmt_setup()
1044 ret = sh_cmt_map_memory(cmt); in sh_cmt_setup()
1049 cmt->num_channels = hweight8(cmt->hw_channels); in sh_cmt_setup()
1050 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), in sh_cmt_setup()
1052 if (cmt->channels == NULL) { in sh_cmt_setup()
1061 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { in sh_cmt_setup()
1063 bool clocksource = i == 1 || cmt->num_channels == 1; in sh_cmt_setup()
1066 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, in sh_cmt_setup()
1067 clockevent, clocksource, cmt); in sh_cmt_setup()
1074 clk_disable(cmt->clk); in sh_cmt_setup()
1076 platform_set_drvdata(pdev, cmt); in sh_cmt_setup()
1081 kfree(cmt->channels); in sh_cmt_setup()
1082 iounmap(cmt->mapbase); in sh_cmt_setup()
1084 clk_disable(cmt->clk); in sh_cmt_setup()
1086 clk_unprepare(cmt->clk); in sh_cmt_setup()
1088 clk_put(cmt->clk); in sh_cmt_setup()
1094 struct sh_cmt_device *cmt = platform_get_drvdata(pdev); in sh_cmt_probe() local
1102 if (cmt) { in sh_cmt_probe()
1107 cmt = kzalloc(sizeof(*cmt), GFP_KERNEL); in sh_cmt_probe()
1108 if (cmt == NULL) in sh_cmt_probe()
1111 ret = sh_cmt_setup(cmt, pdev); in sh_cmt_probe()
1113 kfree(cmt); in sh_cmt_probe()
1121 if (cmt->has_clockevent || cmt->has_clocksource) in sh_cmt_probe()
1162 MODULE_DESCRIPTION("SuperH CMT Timer Driver");