Lines Matching +full:12 +full:bit +full:- +full:clkdiv +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2006-2008 Simtec Electronics
19 #include <linux/soc/samsung/s3c-cpufreq-core.h>
20 #include <linux/soc/samsung/s3c-pm.h>
28 /* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
32 u32 clkdiv = 0; in s3c2410_cpufreq_setdivs() local
34 if (cfg->divs.h_divisor == 2) in s3c2410_cpufreq_setdivs()
35 clkdiv |= S3C2410_CLKDIVN_HDIVN; in s3c2410_cpufreq_setdivs()
37 if (cfg->divs.p_divisor != cfg->divs.h_divisor) in s3c2410_cpufreq_setdivs()
38 clkdiv |= S3C2410_CLKDIVN_PDIVN; in s3c2410_cpufreq_setdivs()
40 s3c24xx_write_clkdivn(clkdiv); in s3c2410_cpufreq_setdivs()
49 fclk = cfg->freq.fclk; in s3c2410_cpufreq_calcdivs()
50 hclk_max = cfg->max.hclk; in s3c2410_cpufreq_calcdivs()
52 cfg->freq.armclk = fclk; in s3c2410_cpufreq_calcdivs()
57 hdiv = (fclk > cfg->max.hclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
60 if (hclk > cfg->max.hclk) { in s3c2410_cpufreq_calcdivs()
62 return -EINVAL; in s3c2410_cpufreq_calcdivs()
65 pdiv = (hclk > cfg->max.pclk) ? 2 : 1; in s3c2410_cpufreq_calcdivs()
68 if (pclk > cfg->max.pclk) { in s3c2410_cpufreq_calcdivs()
70 return -EINVAL; in s3c2410_cpufreq_calcdivs()
76 cfg->divs.p_divisor = pdiv; in s3c2410_cpufreq_calcdivs()
77 cfg->divs.h_divisor = hdiv; in s3c2410_cpufreq_calcdivs()
89 /* transition latency is about 5ms worst-case, so
95 .locktime_bits = 12,