Lines Matching +full:0 +full:- +full:rtic +full:- +full:memory
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * CAAM hardware register-level view
5 * Copyright 2008-2011 Freescale Semiconductor, Inc.
15 #include <linux/io-64-nonatomic-hi-lo.h>
18 * Architecture-specific register access methods
20 * CAAM's bus-addressable registers are 64 bits internally.
21 * They have been wired to be safely accessible on 32-bit
24 * can be treated as two 32-bit entities, or finally (c) if they
25 * must be treated as a single 64-bit value, then this can safely
26 * be done with two 32-bit cycles.
28 * For 32-bit operations on 64-bit values, CAAM follows the same
29 * 64-bit register access conventions as it's predecessors, in that
31 * higher address, thus, a full 64-bit write cycle requires a write
37 * - SWRST is in bit 31 of MCFG.
38 * - MCFG begins at base+0x0000.
39 * - Bits 63-32 are a 32-bit word at base+0x0000 (numerically-lower)
40 * - Bits 31-0 are a 32-bit word at base+0x0004 (numerically-higher)
42 * (and on Power, the convention is 0-31, 32-63, I know...)
44 * Assuming a 64-bit write to this MCFG to perform a software reset
45 * would then require a write of 0 to base+0x0000, followed by a
46 * write of 0x80000000 to base+0x0004, which would "execute" the
49 * Of course, since MCFG 63-32 is all zero, we could cheat and simply
50 * write 0x8000000 to base+0x0004, and the reset would work fine.
51 * However, since CAAM does contain some write-and-read-intended
52 * 64-bit registers, this code defines 64-bit access methods for
54 * clean transition to 64-bit is possible when it becomes necessary.
57 * 32-bit architectures cannot enforce an atomic-64 operation,
60 * - On writes, since the HW is assumed to latch the cycle on the
61 * write of the higher-numeric-address word, then ordered
64 * - For reads, where a register contains a relevant value of more
132 * base + 0x0000 : most-significant 32 bits
133 * base + 0x0004 : least-significant 32 bits
135 * The 32-bit version of this core therefore has to write to base + 0x0004
136 * to set the 32-bit wide DMA address.
139 * base + 0x0000 : least-significant 32 bits
140 * base + 0x0004 : most-significant 32 bits
281 /* Version registers (Era 10+) e80-eff */
311 #define CHA_VER_NUM_MASK 0xffull
314 #define CHA_VER_MISC_MASK (0xffull << CHA_VER_MISC_SHIFT)
317 #define CHA_VER_REV_MASK (0xffull << CHA_VER_REV_SHIFT)
320 #define CHA_VER_VID_MASK (0xffull << CHA_VER_VID_SHIFT)
322 /* CHA Miscellaneous Information - AESA_MISC specific */
325 /* CHA Miscellaneous Information - PKHA_MISC specific */
329 * caam_perfmon - Performance Monitor/Secure Memory Status/
332 * Spans f00-fff wherever instantiated
337 #define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
345 #define CHA_ID_LS_AES_SHIFT 0
346 #define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
349 #define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
352 #define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT)
355 #define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
358 #define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
361 #define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT)
364 #define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT)
367 #define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT)
369 #define CHA_ID_MS_CRC_SHIFT 0
370 #define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT)
373 #define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT)
376 #define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT)
379 #define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT)
382 #define CHA_VER_VID_AES_LP 0x3ull
383 #define CHA_VER_VID_AES_HP 0x4ull
384 #define CHA_VER_VID_MD_LP256 0x0ull
385 #define CHA_VER_VID_MD_LP512 0x1ull
386 #define CHA_VER_VID_MD_HP 0x2ull
395 /* Performance Monitor Registers f00-f9f */
396 u64 req_dequeued; /* PC_REQ_DEQ - Dequeued Requests */
397 u64 ob_enc_req; /* PC_OB_ENC_REQ - Outbound Encrypt Requests */
398 u64 ib_dec_req; /* PC_IB_DEC_REQ - Inbound Decrypt Requests */
399 u64 ob_enc_bytes; /* PC_OB_ENCRYPT - Outbound Bytes Encrypted */
400 u64 ob_prot_bytes; /* PC_OB_PROTECT - Outbound Bytes Protected */
401 u64 ib_dec_bytes; /* PC_IB_DECRYPT - Inbound Bytes Decrypted */
405 /* CAAM Hardware Instantiation Parameters fa0-fbf */
406 u32 cha_rev_ms; /* CRNR - CHA Rev No. Most significant half*/
407 u32 cha_rev_ls; /* CRNR - CHA Rev No. Least significant half*/
409 #define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
412 #define CTPR_MS_VIRT_EN_INCL 0x00000001
413 #define CTPR_MS_VIRT_EN_POR 0x00000002
414 #define CTPR_MS_PG_SZ_MASK 0x10
416 u32 comp_parms_ms; /* CTPR - Compile Parameters Register */
417 u32 comp_parms_ls; /* CTPR - Compile Parameters Register */
420 /* CAAM Global Status fc0-fdf */
421 u64 faultaddr; /* FAR - Fault Address */
422 u32 faultliodn; /* FALR - Fault Address LIODN */
423 u32 faultdetail; /* FADR - Fault Addr Detail */
427 u32 status; /* CSTA - CAAM Status */
430 /* Component Instantiation Parameters fe0-fff */
431 u32 rtic_id; /* RVID - RTIC Version ID */
432 #define CCBVID_ERA_MASK 0xff000000
434 u32 ccb_id; /* CCBVID - CCB Version ID */
435 u32 cha_id_ms; /* CHAVID - CHA Version ID Most Significant*/
436 u32 cha_id_ls; /* CHAVID - CHA Version ID Least Significant*/
437 u32 cha_num_ms; /* CHANUM - CHA Number Most Significant */
438 u32 cha_num_ls; /* CHANUM - CHA Number Least Significant*/
439 #define SECVID_MS_IPID_MASK 0xffff0000
441 #define SECVID_MS_MAJ_REV_MASK 0x0000ff00
443 u32 caam_id_ms; /* CAAMVID - CAAM Version ID MS */
444 u32 caam_id_ls; /* CAAMVID - CAAM Version ID LS */
448 #define MSTRID_LOCK_LIODN 0x80000000
449 #define MSTRID_LOCK_MAKETRUSTED 0x00010000 /* only for JR masterid */
451 #define MSTRID_LIODN_MASK 0x0fff
453 u32 liodn_ms; /* lock and make-trusted control bits */
454 u32 liodn_ls; /* LIODN for non-sequence and seq access */
464 /* Padded out to 0x100 */
466 u32 mode; /* RTSTMODEx - Test mode */
468 u32 reset; /* RTSTRESETx - Test reset control */
470 u32 status; /* RTSTSSTATUSx - Test status */
472 u32 errstat; /* RTSTERRSTATx - Test error status */
474 u32 errctl; /* RTSTERRCTLx - Test error control */
476 u32 entropy; /* RTSTENTROPYx - Test entropy */
478 u32 verifctl; /* RTSTVERIFCTLx - Test verification control */
480 u32 verifstat; /* RTSTVERIFSTATx - Test verification status */
482 u32 verifdata; /* RTSTVERIFDx - Test verification data */
484 u32 xkey; /* RTSTXKEYx - Test XKEY */
486 u32 oscctctl; /* RTSTOSCCTCTLx - Test osc. counter control */
488 u32 oscct; /* RTSTOSCCTx - Test oscillator counter */
490 u32 oscctstat; /* RTSTODCCTSTATx - Test osc counter status */
492 u32 ofifo[4]; /* RTSTOFIFOx - Test output FIFO */
499 #define RTMCTL_PRGM BIT(16) /* 1 -> program mode, 0 -> run mode */
500 #define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0 /* use von Neumann data in
515 u32 rtpkrsq; /* PRGM=0: poker square calc. result register */
518 #define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
524 u32 rttotsam; /* PRGM=0: total samples register */
530 u32 rtfrqcnt; /* PRGM=0: freq. count register */
533 #define RDSTA_SKVT 0x80000000
534 #define RDSTA_SKVN 0x40000000
537 #define RDSTA_IF0 0x00000001
538 #define RDSTA_IF1 0x00000002
545 * caam_ctrl - basic core configuration
546 * starts base + 0x0000 padded out to 0x1000
554 #define DECO_RESET_0 (DECO_RESET << 0)
561 /* Basic Configuration Section 000-01f */
568 /* Bus Access Configuration Section 010-11f */
570 struct masterid jr_mid[4]; /* JRxLIODNR - JobR LIODN setup */
572 u32 jrstart; /* JRSTART - Job Ring Start Register */
573 struct masterid rtic_mid[4]; /* RTICxLIODNR - RTIC LIODN setup */
575 u32 deco_rsr; /* DECORSR - Deco Request Source */
577 u32 deco_rq; /* DECORR - DECO Request */
578 struct partid deco_mid[5]; /* DECOxLIODNR - 1 per DECO */
581 /* DECO Availability/Reset Section 120-3ff */
582 u32 deco_avail; /* DAR - DECO availability */
583 u32 deco_reset; /* DRR - DECO reset */
586 /* Key Encryption/Decryption Configuration 400-5ff */
587 /* Read/Writable only while in Non-secure mode */
588 u32 kek[KEK_KEY_SIZE]; /* JDKEKR - Key Encryption Key */
589 u32 tkek[TKEK_KEY_SIZE]; /* TDKEKR - Trusted Desc KEK */
590 u32 tdsk[TDSK_KEY_SIZE]; /* TDSKR - Trusted Desc Signing Key */
592 u64 sknonce; /* SKNR - Secure Key Nonce */
595 /* RNG Test/Verification/Debug Access 600-7ff */
604 /* Version registers - introduced with era 10 e80-eff */
606 /* Performance Monitor f00-fff */
613 #define MCFGR_SWRESET 0x80000000 /* software reset */
614 #define MCFGR_WDENABLE 0x40000000 /* DECO watchdog enable */
615 #define MCFGR_WDFAIL 0x20000000 /* DECO watchdog force-fail */
616 #define MCFGR_DMA_RESET 0x10000000
617 #define MCFGR_LONG_PTR 0x00010000 /* Use >32-bit desc addressing */
618 #define SCFGR_RDBENABLE 0x00000400
619 #define SCFGR_VIRT_EN 0x00008000
620 #define DECORR_RQD0ENABLE 0x00000001 /* Enable DECO0 for direct access */
621 #define DECORSR_JR0 0x00000001 /* JR to supply TZ, SDID, ICID */
622 #define DECORSR_VALID 0x80000000
623 #define DECORR_DEN0 0x00010000 /* DECO0 available for access*/
627 #define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
628 #define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT)
629 #define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT)
630 #define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT)
634 #define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
635 #define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT)
636 #define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT)
637 #define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT)
641 #define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
643 #define MCFGR_AXIPRI 0x00000008 /* Assert AXI priority sideband */
644 #define MCFGR_LARGE_BURST 0x00000004 /* 128/256-byte burst size */
645 #define MCFGR_BURST_64 0x00000001 /* 64-byte burst size */
648 #define JRSTART_JR0_START 0x00000001 /* Start Job ring 0 */
649 #define JRSTART_JR1_START 0x00000002 /* Start Job ring 1 */
650 #define JRSTART_JR2_START 0x00000004 /* Start Job ring 2 */
651 #define JRSTART_JR3_START 0x00000008 /* Start Job ring 3 */
654 * caam_job_ring - direct job ring setup
655 * 1-4 possible per instantiation, base + 1000/2000/3000/4000
656 * Padded out to 0x1000
660 u64 inpring_base; /* IRBAx - Input desc ring baseaddr */
662 u32 inpring_size; /* IRSx - Input ring size */
664 u32 inpring_avail; /* IRSAx - Input ring room remaining */
666 u32 inpring_jobadd; /* IRJAx - Input ring jobs added */
669 u64 outring_base; /* ORBAx - Output status ring base addr */
671 u32 outring_size; /* ORSx - Output ring size */
673 u32 outring_rmvd; /* ORJRx - Output ring jobs removed */
675 u32 outring_used; /* ORSFx - Output ring slots full */
679 u32 jroutstatus; /* JRSTAx - JobR output status */
681 u32 jrintstatus; /* JRINTx - JobR interrupt status */
682 u32 rconfig_hi; /* JRxCFG - Ring configuration */
687 u32 inp_rdidx; /* IRRIx - Input ring read index */
689 u32 out_wtidx; /* ORWIx - Output ring write index */
693 u32 jrcommand; /* JRCRx - JobR command */
697 /* Version registers - introduced with era 10 e80-eff */
699 /* Performance Monitor f00-fff */
703 #define JR_RINGSIZE_MASK 0x03ff
705 * jrstatus - Job Ring Output Status
711 #define JRSTA_SSRC_MASK 0xf0000000
713 #define JRSTA_SSRC_NONE 0x00000000
714 #define JRSTA_SSRC_CCB_ERROR 0x20000000
715 #define JRSTA_SSRC_JUMP_HALT_USER 0x30000000
716 #define JRSTA_SSRC_DECO 0x40000000
717 #define JRSTA_SSRC_QI 0x50000000
718 #define JRSTA_SSRC_JRERROR 0x60000000
719 #define JRSTA_SSRC_JUMP_HALT_CC 0x70000000
721 #define JRSTA_DECOERR_JUMP 0x08000000
723 #define JRSTA_DECOERR_INDEX_MASK 0xff00
724 #define JRSTA_DECOERR_ERROR_MASK 0x00ff
726 #define JRSTA_DECOERR_NONE 0x00
727 #define JRSTA_DECOERR_LINKLEN 0x01
728 #define JRSTA_DECOERR_LINKPTR 0x02
729 #define JRSTA_DECOERR_JRCTRL 0x03
730 #define JRSTA_DECOERR_DESCCMD 0x04
731 #define JRSTA_DECOERR_ORDER 0x05
732 #define JRSTA_DECOERR_KEYCMD 0x06
733 #define JRSTA_DECOERR_LOADCMD 0x07
734 #define JRSTA_DECOERR_STORECMD 0x08
735 #define JRSTA_DECOERR_OPCMD 0x09
736 #define JRSTA_DECOERR_FIFOLDCMD 0x0a
737 #define JRSTA_DECOERR_FIFOSTCMD 0x0b
738 #define JRSTA_DECOERR_MOVECMD 0x0c
739 #define JRSTA_DECOERR_JUMPCMD 0x0d
740 #define JRSTA_DECOERR_MATHCMD 0x0e
741 #define JRSTA_DECOERR_SHASHCMD 0x0f
742 #define JRSTA_DECOERR_SEQCMD 0x10
743 #define JRSTA_DECOERR_DECOINTERNAL 0x11
744 #define JRSTA_DECOERR_SHDESCHDR 0x12
745 #define JRSTA_DECOERR_HDRLEN 0x13
746 #define JRSTA_DECOERR_BURSTER 0x14
747 #define JRSTA_DECOERR_DESCSIGNATURE 0x15
748 #define JRSTA_DECOERR_DMA 0x16
749 #define JRSTA_DECOERR_BURSTFIFO 0x17
750 #define JRSTA_DECOERR_JRRESET 0x1a
751 #define JRSTA_DECOERR_JOBFAIL 0x1b
752 #define JRSTA_DECOERR_DNRERR 0x80
753 #define JRSTA_DECOERR_UNDEFPCL 0x81
754 #define JRSTA_DECOERR_PDBERR 0x82
755 #define JRSTA_DECOERR_ANRPLY_LATE 0x83
756 #define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
757 #define JRSTA_DECOERR_SEQOVF 0x85
758 #define JRSTA_DECOERR_INVSIGN 0x86
759 #define JRSTA_DECOERR_DSASIGN 0x87
761 #define JRSTA_QIERR_ERROR_MASK 0x00ff
763 #define JRSTA_CCBERR_JUMP 0x08000000
764 #define JRSTA_CCBERR_INDEX_MASK 0xff00
766 #define JRSTA_CCBERR_CHAID_MASK 0x00f0
768 #define JRSTA_CCBERR_ERRID_MASK 0x000f
770 #define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
771 #define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
772 #define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
773 #define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
774 #define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
775 #define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
776 #define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
777 #define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
778 #define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
780 #define JRSTA_CCBERR_ERRID_NONE 0x00
781 #define JRSTA_CCBERR_ERRID_MODE 0x01
782 #define JRSTA_CCBERR_ERRID_DATASIZ 0x02
783 #define JRSTA_CCBERR_ERRID_KEYSIZ 0x03
784 #define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
785 #define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
786 #define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
787 #define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
788 #define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
789 #define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
790 #define JRSTA_CCBERR_ERRID_ICVCHK 0x0a
791 #define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
792 #define JRSTA_CCBERR_ERRID_CCMAAD 0x0c
793 #define JRSTA_CCBERR_ERRID_INVCHA 0x0f
795 #define JRINT_ERR_INDEX_MASK 0x3fff0000
797 #define JRINT_ERR_TYPE_MASK 0xf00
799 #define JRINT_ERR_HALT_MASK 0xc
801 #define JRINT_ERR_HALT_INPROGRESS 0x4
802 #define JRINT_ERR_HALT_COMPLETE 0x8
803 #define JRINT_JR_ERROR 0x02
804 #define JRINT_JR_INT 0x01
815 #define JRCFG_SOE 0x04
816 #define JRCFG_ICEN 0x02
817 #define JRCFG_IMSK 0x01
821 #define JRCR_RESET 0x01
824 * caam_assurance - Assurance Controller View
825 * base + 0x6000 padded out to 0x1000
846 u32 status; /* RSTA - Status */
848 u32 cmd; /* RCMD - Command */
850 u32 ctrl; /* RCTL - Control */
852 u32 throttle; /* RTHR - Throttle */
854 u64 watchdog; /* RWDOG - Watchdog Timer */
856 u32 rend; /* REND - Endian corrections */
860 struct rtic_block memblk[4]; /* Memory Blocks A-D */
864 struct rtic_memhash hash[4]; /* Block hash values A-D */
869 * caam_queue_if - QI configuration and control
870 * starts base + 0x7000, padded out to 0x1000 long
874 u32 qi_control_hi; /* QICTL - QI Control */
877 u32 qi_status; /* QISTA - QI Status */
878 u32 qi_deq_cfg_hi; /* QIDQC - QI Dequeue Configuration */
880 u32 qi_enq_cfg_hi; /* QISEQC - QI Enqueue Command */
885 /* QI control bits - low word */
886 #define QICTL_DQEN 0x01 /* Enable frame pop */
887 #define QICTL_STOP 0x02 /* Stop dequeue/enqueue */
888 #define QICTL_SOE 0x04 /* Stop on error */
890 /* QI control bits - high word */
891 #define QICTL_MBSI 0x01
892 #define QICTL_MHWSI 0x02
893 #define QICTL_MWSI 0x04
894 #define QICTL_MDWSI 0x08
895 #define QICTL_CBSI 0x10 /* CtrlDataByteSwapInput */
896 #define QICTL_CHWSI 0x20 /* CtrlDataHalfSwapInput */
897 #define QICTL_CWSI 0x40 /* CtrlDataWordSwapInput */
898 #define QICTL_CDWSI 0x80 /* CtrlDataDWordSwapInput */
899 #define QICTL_MBSO 0x0100
900 #define QICTL_MHWSO 0x0200
901 #define QICTL_MWSO 0x0400
902 #define QICTL_MDWSO 0x0800
903 #define QICTL_CBSO 0x1000 /* CtrlDataByteSwapOutput */
904 #define QICTL_CHWSO 0x2000 /* CtrlDataHalfSwapOutput */
905 #define QICTL_CWSO 0x4000 /* CtrlDataWordSwapOutput */
906 #define QICTL_CDWSO 0x8000 /* CtrlDataDWordSwapOutput */
907 #define QICTL_DMBS 0x010000
908 #define QICTL_EPO 0x020000
911 #define QISTA_PHRDERR 0x01 /* PreHeader Read Error */
912 #define QISTA_CFRDERR 0x02 /* Compound Frame Read Error */
913 #define QISTA_OFWRERR 0x04 /* Output Frame Read Error */
914 #define QISTA_BPDERR 0x08 /* Buffer Pool Depleted */
915 #define QISTA_BTSERR 0x10 /* Buffer Undersize */
916 #define QISTA_CFWRERR 0x20 /* Compound Frame Write Err */
917 #define QISTA_STOPD 0x80000000 /* QI Stopped (see QICTL) */
919 /* deco_sg_table - DECO view of scatter/gather table */
922 u32 elen; /* E, F bits + 30-bit length */
923 u32 bpid_offset; /* Buffer Pool ID + 16-bit length */
927 * caam_deco - descriptor controller - CHA cluster block
932 * 5 typical, base + 0x8000/9000/a000/b000
933 * Padded out to 0x1000 long
937 u32 cls1_mode; /* CxC1MR - Class 1 Mode */
939 u32 cls1_keysize; /* CxC1KSR - Class 1 Key Size */
940 u32 cls1_datasize_hi; /* CxC1DSR - Class 1 Data Size */
943 u32 cls1_icvsize; /* CxC1ICVSR - Class 1 ICV size */
945 u32 cha_ctrl; /* CCTLR - CHA control */
947 u32 irq_crtl; /* CxCIRQ - CCB interrupt done/error/clear */
949 u32 clr_written; /* CxCWR - Clear-Written */
950 u32 ccb_status_hi; /* CxCSTA - CCB Status/Error */
953 u32 aad_size; /* CxAADSZR - Current AAD Size */
955 u32 cls1_iv_size; /* CxC1IVSZR - Current Class 1 IV Size */
957 u32 pkha_a_size; /* PKASZRx - Size of PKHA A */
959 u32 pkha_b_size; /* PKBSZRx - Size of PKHA B */
961 u32 pkha_n_size; /* PKNSZRx - Size of PKHA N */
963 u32 pkha_e_size; /* PKESZRx - Size of PKHA E */
965 u32 cls1_ctx[16]; /* CxC1CTXR - Class 1 Context @100 */
967 u32 cls1_key[8]; /* CxC1KEYR - Class 1 Key @200 */
969 u32 cls2_mode; /* CxC2MR - Class 2 Mode */
971 u32 cls2_keysize; /* CxX2KSR - Class 2 Key Size */
972 u32 cls2_datasize_hi; /* CxC2DSR - Class 2 Data Size */
975 u32 cls2_icvsize; /* CxC2ICVSZR - Class 2 ICV Size */
977 u32 cls2_ctx[18]; /* CxC2CTXR - Class 2 Context @500 */
979 u32 cls2_key[32]; /* CxC2KEYR - Class2 Key @600 */
981 u32 inp_infofifo_hi; /* CxIFIFO - Input Info FIFO @7d0 */
984 u64 inp_datafifo; /* CxDFIFO - Input Data FIFO */
986 u64 out_datafifo; /* CxOFIFO - Output Data FIFO */
988 u32 jr_ctl_hi; /* CxJRR - JobR Control Register @800 */
990 u64 jr_descaddr; /* CxDADR - JobR Descriptor Address */
991 #define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
992 u32 op_status_hi; /* DxOPSTA - DECO Operation Status */
995 u32 liodn; /* DxLSR - DECO LIODN Status - non-seq */
996 u32 td_liodn; /* DxLSR - DECO LIODN Status - trustdesc */
998 u64 math[4]; /* DxMTH - Math register */
1000 struct deco_sg_table gthr_tbl[4]; /* DxGTR - Gather Tables */
1002 struct deco_sg_table sctr_tbl[4]; /* DxSTR - Scatter Tables */
1004 u32 descbuf[64]; /* DxDESB - Descriptor buffer */
1006 #define DESC_DBG_DECO_STAT_VALID 0x80000000
1007 #define DESC_DBG_DECO_STAT_MASK 0x00F00000
1009 u32 desc_dbg; /* DxDDR - DECO Debug Register */
1011 #define DESC_DER_DECO_STAT_MASK 0x000F0000
1013 u32 dbg_exec; /* DxDER - DECO Debug Exec Register */
1017 #define DECO_STAT_HOST_ERR 0xD
1019 #define DECO_JQCR_WHL 0x20000000
1020 #define DECO_JQCR_FOUR 0x10000000
1026 #define PG_SIZE_4K 0x1000
1027 #define PG_SIZE_64K 0x10000