Lines Matching full:qm
87 #define SEC_ADDR(qm, offset) ((qm)->io_base + (offset) + \ argument
244 static u8 sec_get_endian(struct hisi_qm *qm) in sec_get_endian() argument
252 if (qm->pdev->is_virtfn) { in sec_get_endian()
253 dev_err_ratelimited(&qm->pdev->dev, in sec_get_endian()
257 reg = readl_relaxed(qm->io_base + SEC_ENGINE_PF_CFG_OFF + in sec_get_endian()
273 static int sec_engine_init(struct hisi_qm *qm) in sec_engine_init() argument
279 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
281 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
283 writel_relaxed(0x1, SEC_ADDR(qm, SEC_MEM_START_INIT_REG)); in sec_engine_init()
285 ret = readl_relaxed_poll_timeout(SEC_ADDR(qm, SEC_MEM_INIT_DONE_REG), in sec_engine_init()
289 pci_err(qm->pdev, "fail to init sec mem\n"); in sec_engine_init()
293 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
295 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
297 reg = readl_relaxed(SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL0_REG)); in sec_engine_init()
299 writel_relaxed(reg, SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL0_REG)); in sec_engine_init()
301 reg = readl_relaxed(SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL1_REG)); in sec_engine_init()
303 writel_relaxed(reg, SEC_ADDR(qm, SEC_INTERFACE_USER_CTRL1_REG)); in sec_engine_init()
306 qm->io_base + AM_CFG_SINGLE_PORT_MAX_TRANS); in sec_engine_init()
308 writel(SEC_SAA_ENABLE, SEC_ADDR(qm, SEC_SAA_EN_REG)); in sec_engine_init()
312 SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG0)); in sec_engine_init()
315 SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG1)); in sec_engine_init()
317 SEC_ADDR(qm, SEC_BD_ERR_CHK_EN_REG3)); in sec_engine_init()
320 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
321 reg |= sec_get_endian(qm); in sec_engine_init()
322 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
327 static int sec_set_user_domain_and_cache(struct hisi_qm *qm) in sec_set_user_domain_and_cache() argument
329 /* qm user domain */ in sec_set_user_domain_and_cache()
330 writel(AXUSER_BASE, qm->io_base + QM_ARUSER_M_CFG_1); in sec_set_user_domain_and_cache()
331 writel(ARUSER_M_CFG_ENABLE, qm->io_base + QM_ARUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
332 writel(AXUSER_BASE, qm->io_base + QM_AWUSER_M_CFG_1); in sec_set_user_domain_and_cache()
333 writel(AWUSER_M_CFG_ENABLE, qm->io_base + QM_AWUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
334 writel(WUSER_M_CFG_ENABLE, qm->io_base + QM_WUSER_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
336 /* qm cache */ in sec_set_user_domain_and_cache()
337 writel(AXI_M_CFG, qm->io_base + QM_AXI_M_CFG); in sec_set_user_domain_and_cache()
338 writel(AXI_M_CFG_ENABLE, qm->io_base + QM_AXI_M_CFG_ENABLE); in sec_set_user_domain_and_cache()
341 writel(PEH_AXUSER_CFG, qm->io_base + QM_PEH_AXUSER_CFG); in sec_set_user_domain_and_cache()
342 writel(PEH_AXUSER_CFG_ENABLE, qm->io_base + QM_PEH_AXUSER_CFG_ENABLE); in sec_set_user_domain_and_cache()
347 FIELD_PREP(CQC_CACHE_WB_THRD, 1), qm->io_base + QM_CACHE_CTL); in sec_set_user_domain_and_cache()
349 return sec_engine_init(qm); in sec_set_user_domain_and_cache()
353 static void sec_debug_regs_clear(struct hisi_qm *qm) in sec_debug_regs_clear() argument
358 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); in sec_debug_regs_clear()
359 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); in sec_debug_regs_clear()
362 writel(0x1, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
364 readl(qm->io_base + sec_dfx_regs[i].offset); in sec_debug_regs_clear()
367 writel(0x0, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_debug_regs_clear()
369 hisi_qm_debug_regs_clear(qm); in sec_debug_regs_clear()
372 static void sec_hw_error_enable(struct hisi_qm *qm) in sec_hw_error_enable() argument
376 if (qm->ver == QM_HW_V1) { in sec_hw_error_enable()
377 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_enable()
378 pci_info(qm->pdev, "V1 not support hw error handle\n"); in sec_hw_error_enable()
382 val = readl(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_hw_error_enable()
385 writel(SEC_CORE_INT_CLEAR, qm->io_base + SEC_CORE_INT_SOURCE); in sec_hw_error_enable()
388 writel(SEC_CORE_INT_ENABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_enable()
391 writel(SEC_RAS_CE_ENB_MSK, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_enable()
392 writel(SEC_RAS_FE_ENB_MSK, qm->io_base + SEC_RAS_FE_REG); in sec_hw_error_enable()
393 writel(SEC_RAS_NFE_ENB_MSK, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_enable()
398 writel(val, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_hw_error_enable()
401 static void sec_hw_error_disable(struct hisi_qm *qm) in sec_hw_error_disable() argument
405 val = readl(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_hw_error_disable()
408 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_disable()
409 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_FE_REG); in sec_hw_error_disable()
410 writel(SEC_RAS_DISABLE, qm->io_base + SEC_RAS_NFE_REG); in sec_hw_error_disable()
413 writel(SEC_CORE_INT_DISABLE, qm->io_base + SEC_CORE_INT_MASK); in sec_hw_error_disable()
418 writel(val, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_hw_error_disable()
423 struct hisi_qm *qm = file->qm; in sec_current_qm_read() local
425 return readl(qm->io_base + QM_DFX_MB_CNT_VF); in sec_current_qm_read()
430 struct hisi_qm *qm = file->qm; in sec_current_qm_write() local
434 if (val > qm->vfs_num) in sec_current_qm_write()
439 qm->debug.curr_qm_qp_num = qm->qp_num; in sec_current_qm_write()
441 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / qm->vfs_num; in sec_current_qm_write()
443 if (val == qm->vfs_num) in sec_current_qm_write()
444 qm->debug.curr_qm_qp_num = in sec_current_qm_write()
445 qm->ctrl_qp_num - qm->qp_num - in sec_current_qm_write()
446 (qm->vfs_num - 1) * vfq_num; in sec_current_qm_write()
448 qm->debug.curr_qm_qp_num = vfq_num; in sec_current_qm_write()
451 writel(val, qm->io_base + QM_DFX_MB_CNT_VF); in sec_current_qm_write()
452 writel(val, qm->io_base + QM_DFX_DB_CNT_VF); in sec_current_qm_write()
455 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK); in sec_current_qm_write()
456 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); in sec_current_qm_write()
459 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK); in sec_current_qm_write()
460 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); in sec_current_qm_write()
467 struct hisi_qm *qm = file->qm; in sec_clear_enable_read() local
469 return readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & in sec_clear_enable_read()
475 struct hisi_qm *qm = file->qm; in sec_clear_enable_write() local
481 tmp = (readl(qm->io_base + SEC_CTRL_CNT_CLR_CE) & in sec_clear_enable_write()
483 writel(tmp, qm->io_base + SEC_CTRL_CNT_CLR_CE); in sec_clear_enable_write()
593 static int sec_core_debug_init(struct hisi_qm *qm) in sec_core_debug_init() argument
595 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); in sec_core_debug_init()
596 struct device *dev = &qm->pdev->dev; in sec_core_debug_init()
602 tmp_d = debugfs_create_dir("sec_dfx", qm->debug.debug_root); in sec_core_debug_init()
610 regset->base = qm->io_base; in sec_core_debug_init()
612 if (qm->pdev->device == SEC_PF_PCI_DEVICE_ID) in sec_core_debug_init()
625 static int sec_debug_init(struct hisi_qm *qm) in sec_debug_init() argument
627 struct sec_dev *sec = container_of(qm, struct sec_dev, qm); in sec_debug_init()
630 if (qm->pdev->device == SEC_PF_PCI_DEVICE_ID) { in sec_debug_init()
634 sec->debug.files[i].qm = qm; in sec_debug_init()
637 qm->debug.debug_root, in sec_debug_init()
643 return sec_core_debug_init(qm); in sec_debug_init()
646 static int sec_debugfs_init(struct hisi_qm *qm) in sec_debugfs_init() argument
648 struct device *dev = &qm->pdev->dev; in sec_debugfs_init()
651 qm->debug.debug_root = debugfs_create_dir(dev_name(dev), in sec_debugfs_init()
653 qm->debug.sqe_mask_offset = SEC_SQE_MASK_OFFSET; in sec_debugfs_init()
654 qm->debug.sqe_mask_len = SEC_SQE_MASK_LEN; in sec_debugfs_init()
655 ret = hisi_qm_debug_init(qm); in sec_debugfs_init()
659 ret = sec_debug_init(qm); in sec_debugfs_init()
672 static void sec_debugfs_exit(struct hisi_qm *qm) in sec_debugfs_exit() argument
674 debugfs_remove_recursive(qm->debug.debug_root); in sec_debugfs_exit()
677 static void sec_log_hw_error(struct hisi_qm *qm, u32 err_sts) in sec_log_hw_error() argument
680 struct device *dev = &qm->pdev->dev; in sec_log_hw_error()
689 err_val = readl(qm->io_base + in sec_log_hw_error()
699 static u32 sec_get_hw_err_status(struct hisi_qm *qm) in sec_get_hw_err_status() argument
701 return readl(qm->io_base + SEC_CORE_INT_STATUS); in sec_get_hw_err_status()
704 static void sec_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts) in sec_clear_hw_err_status() argument
706 writel(err_sts, qm->io_base + SEC_CORE_INT_SOURCE); in sec_clear_hw_err_status()
709 static void sec_open_axi_master_ooo(struct hisi_qm *qm) in sec_open_axi_master_ooo() argument
713 val = readl(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_open_axi_master_ooo()
714 writel(val & SEC_AXI_SHUTDOWN_DISABLE, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_open_axi_master_ooo()
715 writel(val | SEC_AXI_SHUTDOWN_ENABLE, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_open_axi_master_ooo()
739 struct hisi_qm *qm = &sec->qm; in sec_pf_probe_init() local
742 if (qm->ver == QM_HW_V1) in sec_pf_probe_init()
743 qm->ctrl_qp_num = SEC_QUEUE_NUM_V1; in sec_pf_probe_init()
745 qm->ctrl_qp_num = SEC_QUEUE_NUM_V2; in sec_pf_probe_init()
747 qm->err_ini = &sec_err_ini; in sec_pf_probe_init()
749 ret = sec_set_user_domain_and_cache(qm); in sec_pf_probe_init()
753 hisi_qm_dev_err_init(qm); in sec_pf_probe_init()
754 sec_debug_regs_clear(qm); in sec_pf_probe_init()
759 static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) in sec_qm_init() argument
763 qm->pdev = pdev; in sec_qm_init()
764 qm->ver = pdev->revision; in sec_qm_init()
765 qm->sqe_size = SEC_SQE_SIZE; in sec_qm_init()
766 qm->dev_name = sec_name; in sec_qm_init()
768 qm->fun_type = (pdev->device == SEC_PF_PCI_DEVICE_ID) ? in sec_qm_init()
770 if (qm->fun_type == QM_HW_PF) { in sec_qm_init()
771 qm->qp_base = SEC_PF_DEF_Q_BASE; in sec_qm_init()
772 qm->qp_num = pf_q_num; in sec_qm_init()
773 qm->debug.curr_qm_qp_num = pf_q_num; in sec_qm_init()
774 qm->qm_list = &sec_devices; in sec_qm_init()
775 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) { in sec_qm_init()
777 * have no way to get qm configure in VM in v1 hardware, in sec_qm_init()
782 qm->qp_base = SEC_PF_DEF_Q_NUM; in sec_qm_init()
783 qm->qp_num = SEC_QUEUE_NUM_V1 - SEC_PF_DEF_Q_NUM; in sec_qm_init()
792 qm->wq = alloc_workqueue("%s", WQ_HIGHPRI | WQ_MEM_RECLAIM | in sec_qm_init()
794 pci_name(qm->pdev)); in sec_qm_init()
795 if (!qm->wq) { in sec_qm_init()
796 pci_err(qm->pdev, "fail to alloc workqueue\n"); in sec_qm_init()
800 ret = hisi_qm_init(qm); in sec_qm_init()
802 destroy_workqueue(qm->wq); in sec_qm_init()
807 static void sec_qm_uninit(struct hisi_qm *qm) in sec_qm_uninit() argument
809 hisi_qm_uninit(qm); in sec_qm_uninit()
814 struct hisi_qm *qm = &sec->qm; in sec_probe_init() local
817 if (qm->fun_type == QM_HW_PF) { in sec_probe_init()
826 static void sec_probe_uninit(struct hisi_qm *qm) in sec_probe_uninit() argument
828 hisi_qm_dev_err_uninit(qm); in sec_probe_uninit()
830 destroy_workqueue(qm->wq); in sec_probe_uninit()
836 struct device *dev = &sec->qm.pdev->dev; in sec_iommu_used_check()
853 struct hisi_qm *qm; in sec_probe() local
860 qm = &sec->qm; in sec_probe()
861 ret = sec_qm_init(qm, pdev); in sec_probe()
863 pci_err(pdev, "Failed to init SEC QM (%d)!\n", ret); in sec_probe()
876 ret = hisi_qm_start(qm); in sec_probe()
878 pci_err(pdev, "Failed to start sec qm!\n"); in sec_probe()
882 ret = sec_debugfs_init(qm); in sec_probe()
886 ret = hisi_qm_alg_register(qm, &sec_devices); in sec_probe()
892 if (qm->fun_type == QM_HW_PF && vfs_num) { in sec_probe()
901 hisi_qm_alg_unregister(qm, &sec_devices); in sec_probe()
904 sec_debugfs_exit(qm); in sec_probe()
905 hisi_qm_stop(qm, QM_NORMAL); in sec_probe()
908 sec_probe_uninit(qm); in sec_probe()
911 sec_qm_uninit(qm); in sec_probe()
918 struct hisi_qm *qm = pci_get_drvdata(pdev); in sec_remove() local
920 hisi_qm_wait_task_finish(qm, &sec_devices); in sec_remove()
921 hisi_qm_alg_unregister(qm, &sec_devices); in sec_remove()
922 if (qm->fun_type == QM_HW_PF && qm->vfs_num) in sec_remove()
923 hisi_qm_sriov_disable(pdev, qm->is_frozen); in sec_remove()
925 sec_debugfs_exit(qm); in sec_remove()
927 (void)hisi_qm_stop(qm, QM_NORMAL); in sec_remove()
929 if (qm->fun_type == QM_HW_PF) in sec_remove()
930 sec_debug_regs_clear(qm); in sec_remove()
932 sec_probe_uninit(qm); in sec_remove()
934 sec_qm_uninit(qm); in sec_remove()