1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/dma-direction.h>
70  * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124  * /-----------\ 0
126  * |-----------| 0x20
128  * |-----------| 0x40
130  * |-----------| 0x40 (inplace)
132  * |-----------| 0x80
133  * |  DATA IN  |	16 * x (max ->max_req_size)
134  * |-----------| 0x80 (inplace operation)
135  * |  DATA OUT |	16 * x (max ->max_req_size)
136  * \-----------/ SRAM size
141  * /-----------\ 0
143  * |-----------| 0x20
145  * |-----------| 0x40
147  * |-----------| 0x60
149  * |-----------| 0x80
150  * |  DATA IN  |        64 * x (max ->max_req_size)
151  * \-----------/ SRAM size
196 #define CESA_SA_SRAM_PAYLOAD_SIZE		(cesa_dev->sram_size - \
202 #define CESA_SA_SRAM_MSK			(2048 - 1)
205 #define CESA_HASH_BLOCK_SIZE_MSK		(CESA_MAX_HASH_BLOCK_SIZE - 1)
208  * struct mv_cesa_sec_accel_desc - security accelerator descriptor
209  * @config:	engine config
218  * Structure passed to the CESA engine to describe the crypto operation
233  * struct mv_cesa_skcipher_op_ctx - cipher operation context
245  * struct mv_cesa_hash_op_ctx - hash or hmac operation context
257  * struct mv_cesa_op_ctx - crypto operation context
284  * struct mv_cesa_tdma_desc - TDMA descriptor
322  * struct mv_cesa_sg_dma_iter - scatter-gather iterator
339  * struct mv_cesa_dma_iter - crypto operation iterator
342  * @op_len:	sub-operation length (the crypto engine can only act on 2kb
354  * struct mv_cesa_tdma_chain - TDMA chain
358  * Stores a TDMA chain for a specific crypto operation.
368  * struct mv_cesa_caps - CESA device capabilities
388  * struct mv_cesa_dev_dma - DMA pools
406  * struct mv_cesa_dev - CESA device
427  * struct mv_cesa_engine - CESA engine
428  * @id:			engine id
429  * @regs:		engine registers
432  * @lock:		engine lock
434  * @clk:		engine clk
435  * @zclk:		engine zclk
441  * @load:		engine load counter, useful for load balancing
443  *			by this engine.
444  * @complete_queue:	fifo of the processed requests by the engine
446  * Structure storing CESA engine information.
468  * struct mv_cesa_req_ops - CESA request operations
470  *		operation, -EINPROGRESS if it needs more steps or an error
485  * struct mv_cesa_ctx - CESA operation context
488  * Base context structure inherited by operation specific ones.
495  * struct mv_cesa_hash_ctx - CESA hash operation context
505  * struct mv_cesa_hash_ctx - CESA hmac operation context
517  * enum mv_cesa_req_type - request type definitions
527  * struct mv_cesa_req - CESA request
528  * @engine:	engine associated with this request
532 	struct mv_cesa_engine *engine;  member
537  * struct mv_cesa_sg_std_iter - CESA scatter-gather iterator for standard
548  * struct mv_cesa_skcipher_std_req - cipher standard request
561  * struct mv_cesa_skcipher_req - cipher request
562  * @req:	type specific request information
574  * struct mv_cesa_ahash_std_req - standard hash request
582  * struct mv_cesa_ahash_dma_req - DMA hash request
595  * struct mv_cesa_ahash_req - hash request
596  * @req:		type specific request information
627 mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine *engine,  in mv_cesa_engine_enqueue_complete_request()  argument
630 	list_add_tail(&req->list, &engine->complete_queue);  in mv_cesa_engine_enqueue_complete_request()
634 mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine *engine)  in mv_cesa_engine_dequeue_complete_request()  argument
638 	req = list_first_entry_or_null(&engine->complete_queue,  in mv_cesa_engine_dequeue_complete_request()
642 		list_del(&req->list);  in mv_cesa_engine_dequeue_complete_request()
651 	return req->chain.first ? CESA_DMA_REQ : CESA_STD_REQ;  in mv_cesa_req_get_type()
657 	op->desc.config &= cpu_to_le32(~mask);  in mv_cesa_update_op_cfg()
658 	op->desc.config |= cpu_to_le32(cfg);  in mv_cesa_update_op_cfg()
663 	return le32_to_cpu(op->desc.config);  in mv_cesa_get_op_cfg()
668 	op->desc.config = cpu_to_le32(cfg);  in mv_cesa_set_op_cfg()
671 static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine,  in mv_cesa_adjust_op()  argument
674 	u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK;  in mv_cesa_adjust_op()
676 	op->desc.enc_p = CESA_SA_DESC_CRYPT_DATA(offset);  in mv_cesa_adjust_op()
677 	op->desc.enc_key_p = CESA_SA_DESC_CRYPT_KEY(offset);  in mv_cesa_adjust_op()
678 	op->desc.enc_iv = CESA_SA_DESC_CRYPT_IV(offset);  in mv_cesa_adjust_op()
679 	op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_DATA_MSK;  in mv_cesa_adjust_op()
680 	op->desc.mac_src_p |= CESA_SA_DESC_MAC_DATA(offset);  in mv_cesa_adjust_op()
681 	op->desc.mac_digest &= ~CESA_SA_DESC_MAC_DIGEST_MSK;  in mv_cesa_adjust_op()
682 	op->desc.mac_digest |= CESA_SA_DESC_MAC_DIGEST(offset);  in mv_cesa_adjust_op()
683 	op->desc.mac_iv = CESA_SA_DESC_MAC_IV(offset);  in mv_cesa_adjust_op()
688 	op->desc.enc_len = cpu_to_le32(len);  in mv_cesa_set_crypt_op_len()
694 	op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_TOTAL_LEN_MSK;  in mv_cesa_set_mac_op_total_len()
695 	op->desc.mac_src_p |= CESA_SA_DESC_MAC_TOTAL_LEN(len);  in mv_cesa_set_mac_op_total_len()
701 	op->desc.mac_digest &= ~CESA_SA_DESC_MAC_FRAG_LEN_MSK;  in mv_cesa_set_mac_op_frag_len()
702 	op->desc.mac_digest |= CESA_SA_DESC_MAC_FRAG_LEN(len);  in mv_cesa_set_mac_op_frag_len()
705 static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine,  in mv_cesa_set_int_mask()  argument
708 	if (int_mask == engine->int_mask)  in mv_cesa_set_int_mask()
711 	writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK);  in mv_cesa_set_int_mask()
712 	engine->int_mask = int_mask;  in mv_cesa_set_int_mask()
715 static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine)  in mv_cesa_get_int_mask()  argument
717 	return engine->int_mask;  in mv_cesa_get_int_mask()
730 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
739 	for (i = 0; i < cesa_dev->caps->nengines; i++) {  in mv_cesa_select_engine()
740 		struct mv_cesa_engine *engine = cesa_dev->engines + i;  in mv_cesa_select_engine()  local
741 		u32 load = atomic_read(&engine->load);  in mv_cesa_select_engine()
745 			selected = engine;  in mv_cesa_select_engine()
749 	atomic_add(weight, &selected->load);  in mv_cesa_select_engine()
765 	if (ret == -EINPROGRESS)  in mv_cesa_req_needs_cleanup()
774 	if (ret == -EBUSY)  in mv_cesa_req_needs_cleanup()
786 	iter->len = len;  in mv_cesa_req_dma_iter_init()
787 	iter->op_len = min(len, CESA_SA_SRAM_PAYLOAD_SIZE);  in mv_cesa_req_dma_iter_init()
788 	iter->offset = 0;  in mv_cesa_req_dma_iter_init()
795 	iter->op_offset = 0;  in mv_cesa_sg_dma_iter_init()
796 	iter->offset = 0;  in mv_cesa_sg_dma_iter_init()
797 	iter->sg = sg;  in mv_cesa_sg_dma_iter_init()
798 	iter->dir = dir;  in mv_cesa_sg_dma_iter_init()
805 	return min(iter->op_len - sgiter->op_offset,  in mv_cesa_req_dma_iter_transfer_len()
806 		   sg_dma_len(sgiter->sg) - sgiter->offset);  in mv_cesa_req_dma_iter_transfer_len()
815 	iter->offset += iter->op_len;  in mv_cesa_req_dma_iter_next_op()
816 	iter->op_len = min(iter->len - iter->offset,  in mv_cesa_req_dma_iter_next_op()
819 	return iter->op_len;  in mv_cesa_req_dma_iter_next_op()
828 		return -EINPROGRESS;  in mv_cesa_dma_process()
831 		return -EINVAL;  in mv_cesa_dma_process()
837 			 struct mv_cesa_engine *engine);
839 void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
841 int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status);