18 static inline u32 qce_read(struct qce_device *qce, u32 offset)  in qce_read()  argument
20 	return readl(qce->base + offset);  in qce_read()
23 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)  in qce_write()  argument
25 	writel(val, qce->base + offset);  in qce_write()
28 static inline void qce_write_array(struct qce_device *qce, u32 offset,  in qce_write_array()  argument
34 		qce_write(qce, offset + i * sizeof(u32), val[i]);  in qce_write_array()
38 qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)  in qce_clear_array()  argument
43 		qce_write(qce, offset + i * sizeof(u32), 0);  in qce_clear_array()
46 static u32 qce_config_reg(struct qce_device *qce, int little)  in qce_config_reg()  argument
48 	u32 beats = (qce->burst_size >> 3) - 1;  in qce_config_reg()
49 	u32 pipe_pair = qce->pipe_pair_id;  in qce_config_reg()
78 static void qce_setup_config(struct qce_device *qce)  in qce_setup_config()  argument
83 	config = qce_config_reg(qce, 0);  in qce_setup_config()
86 	qce_write(qce, REG_STATUS, 0);  in qce_setup_config()
87 	qce_write(qce, REG_CONFIG, config);  in qce_setup_config()
90 static inline void qce_crypto_go(struct qce_device *qce)  in qce_crypto_go()  argument
92 	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));  in qce_crypto_go()
149 	struct qce_device *qce = tmpl->qce;  in qce_setup_regs_ahash()  local
161 	qce_setup_config(qce);  in qce_setup_regs_ahash()
164 		qce_write(qce, REG_AUTH_SEG_CFG, 0);  in qce_setup_regs_ahash()
165 		qce_write(qce, REG_ENCR_SEG_CFG, 0);  in qce_setup_regs_ahash()
166 		qce_write(qce, REG_ENCR_SEG_SIZE, 0);  in qce_setup_regs_ahash()
167 		qce_clear_array(qce, REG_AUTH_IV0, 16);  in qce_setup_regs_ahash()
168 		qce_clear_array(qce, REG_AUTH_KEY0, 16);  in qce_setup_regs_ahash()
169 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);  in qce_setup_regs_ahash()
178 		qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey,  in qce_setup_regs_ahash()
191 	qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words);  in qce_setup_regs_ahash()
194 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);  in qce_setup_regs_ahash()
196 		qce_write_array(qce, REG_AUTH_BYTECNT0,  in qce_setup_regs_ahash()
212 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_ahash()
213 	qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes);  in qce_setup_regs_ahash()
214 	qce_write(qce, REG_AUTH_SEG_START, 0);  in qce_setup_regs_ahash()
215 	qce_write(qce, REG_ENCR_SEG_CFG, 0);  in qce_setup_regs_ahash()
216 	qce_write(qce, REG_SEG_SIZE, req->nbytes);  in qce_setup_regs_ahash()
219 	config = qce_config_reg(qce, 1);  in qce_setup_regs_ahash()
220 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_ahash()
222 	qce_crypto_go(qce);  in qce_setup_regs_ahash()
292 static void qce_xtskey(struct qce_device *qce, const u8 *enckey,  in qce_xtskey()  argument
301 	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);  in qce_xtskey()
305 	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);  in qce_xtskey()
315 	struct qce_device *qce = tmpl->qce;  in qce_setup_regs_skcipher()  local
324 	qce_setup_config(qce);  in qce_setup_regs_skcipher()
334 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);  in qce_setup_regs_skcipher()
346 			qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen,  in qce_setup_regs_skcipher()
353 	qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words);  in qce_setup_regs_skcipher()
361 		qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words);  in qce_setup_regs_skcipher()
367 	qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);  in qce_setup_regs_skcipher()
368 	qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);  in qce_setup_regs_skcipher()
369 	qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff);  in qce_setup_regs_skcipher()
372 		qce_write(qce, REG_CNTR_MASK, ~0);  in qce_setup_regs_skcipher()
373 		qce_write(qce, REG_CNTR_MASK0, ~0);  in qce_setup_regs_skcipher()
374 		qce_write(qce, REG_CNTR_MASK1, ~0);  in qce_setup_regs_skcipher()
375 		qce_write(qce, REG_CNTR_MASK2, ~0);  in qce_setup_regs_skcipher()
378 	qce_write(qce, REG_SEG_SIZE, totallen);  in qce_setup_regs_skcipher()
381 	config = qce_config_reg(qce, 1);  in qce_setup_regs_skcipher()
382 	qce_write(qce, REG_CONFIG, config);  in qce_setup_regs_skcipher()
384 	qce_crypto_go(qce);  in qce_setup_regs_skcipher()
410 int qce_check_status(struct qce_device *qce, u32 *status)  in qce_check_status()  argument
414 	*status = qce_read(qce, REG_STATUS);  in qce_check_status()
428 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step)  in qce_get_version()  argument
432 	val = qce_read(qce, REG_VERSION);  in qce_get_version()