Lines Matching +full:edma +full:- +full:err
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
21 #include "fsl-edma-common.h"
27 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
34 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
37 intr = edma_readl(fsl_edma, regs->intl); in fsl_edma_tx_handler()
41 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_tx_handler()
43 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); in fsl_edma_tx_handler()
45 fsl_chan = &fsl_edma->chans[ch]; in fsl_edma_tx_handler()
47 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_handler()
49 if (!fsl_chan->edesc) { in fsl_edma_tx_handler()
51 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_handler()
55 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_handler()
56 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_handler()
57 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_handler()
58 fsl_chan->edesc = NULL; in fsl_edma_tx_handler()
59 fsl_chan->status = DMA_COMPLETE; in fsl_edma_tx_handler()
60 fsl_chan->idle = true; in fsl_edma_tx_handler()
62 vchan_cyclic_callback(&fsl_chan->edesc->vdesc); in fsl_edma_tx_handler()
65 if (!fsl_chan->edesc) in fsl_edma_tx_handler()
68 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_handler()
77 unsigned int err, ch; in fsl_edma_err_handler() local
78 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_err_handler()
80 err = edma_readl(fsl_edma, regs->errl); in fsl_edma_err_handler()
81 if (!err) in fsl_edma_err_handler()
84 for (ch = 0; ch < fsl_edma->n_chans; ch++) { in fsl_edma_err_handler()
85 if (err & (0x1 << ch)) { in fsl_edma_err_handler()
86 fsl_edma_disable_request(&fsl_edma->chans[ch]); in fsl_edma_err_handler()
87 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); in fsl_edma_err_handler()
88 fsl_edma->chans[ch].status = DMA_ERROR; in fsl_edma_err_handler()
89 fsl_edma->chans[ch].idle = true; in fsl_edma_err_handler()
106 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; in fsl_edma_xlate()
109 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; in fsl_edma_xlate()
110 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; in fsl_edma_xlate()
112 if (dma_spec->args_count != 2) in fsl_edma_xlate()
115 mutex_lock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
116 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { in fsl_edma_xlate()
117 if (chan->client_count) in fsl_edma_xlate()
119 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { in fsl_edma_xlate()
122 chan->device->privatecnt++; in fsl_edma_xlate()
124 fsl_chan->slave_id = dma_spec->args[1]; in fsl_edma_xlate()
125 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, in fsl_edma_xlate()
127 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
132 mutex_unlock(&fsl_edma->fsl_edma_mutex); in fsl_edma_xlate()
141 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); in fsl_edma_irq_init()
142 if (fsl_edma->txirq < 0) in fsl_edma_irq_init()
143 return fsl_edma->txirq; in fsl_edma_irq_init()
145 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); in fsl_edma_irq_init()
146 if (fsl_edma->errirq < 0) in fsl_edma_irq_init()
147 return fsl_edma->errirq; in fsl_edma_irq_init()
149 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_init()
150 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
151 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); in fsl_edma_irq_init()
153 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); in fsl_edma_irq_init()
157 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, in fsl_edma_irq_init()
158 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); in fsl_edma_irq_init()
160 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); in fsl_edma_irq_init()
164 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, in fsl_edma_irq_init()
165 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); in fsl_edma_irq_init()
167 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); in fsl_edma_irq_init()
183 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); in fsl_edma2_irq_init()
185 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); in fsl_edma2_irq_init()
186 return -EINVAL; in fsl_edma2_irq_init()
197 return -ENXIO; in fsl_edma2_irq_init()
199 sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i); in fsl_edma2_irq_init()
201 /* The last IRQ is for eDMA err */ in fsl_edma2_irq_init()
202 if (i == count - 1) in fsl_edma2_irq_init()
203 ret = devm_request_irq(&pdev->dev, irq, in fsl_edma2_irq_init()
205 0, "eDMA2-ERR", fsl_edma); in fsl_edma2_irq_init()
207 ret = devm_request_irq(&pdev->dev, irq, in fsl_edma2_irq_init()
209 fsl_edma->chans[i].chan_name, in fsl_edma2_irq_init()
221 if (fsl_edma->txirq == fsl_edma->errirq) { in fsl_edma_irq_exit()
222 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
224 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); in fsl_edma_irq_exit()
225 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); in fsl_edma_irq_exit()
234 clk_disable_unprepare(fsl_edma->muxclk[i]); in fsl_disable_clocks()
258 { .compatible = "fsl,vf610-edma", .data = &vf610_data},
259 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
260 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
268 of_match_device(fsl_edma_dt_ids, &pdev->dev); in fsl_edma_probe()
269 struct device_node *np = pdev->dev.of_node; in fsl_edma_probe()
279 drvdata = of_id->data; in fsl_edma_probe()
281 dev_err(&pdev->dev, "unable to find driver data\n"); in fsl_edma_probe()
282 return -EINVAL; in fsl_edma_probe()
285 ret = of_property_read_u32(np, "dma-channels", &chans); in fsl_edma_probe()
287 dev_err(&pdev->dev, "Can't get dma-channels.\n"); in fsl_edma_probe()
292 fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); in fsl_edma_probe()
294 return -ENOMEM; in fsl_edma_probe()
296 fsl_edma->drvdata = drvdata; in fsl_edma_probe()
297 fsl_edma->n_chans = chans; in fsl_edma_probe()
298 mutex_init(&fsl_edma->fsl_edma_mutex); in fsl_edma_probe()
301 fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res); in fsl_edma_probe()
302 if (IS_ERR(fsl_edma->membase)) in fsl_edma_probe()
303 return PTR_ERR(fsl_edma->membase); in fsl_edma_probe()
306 regs = &fsl_edma->regs; in fsl_edma_probe()
308 if (drvdata->has_dmaclk) { in fsl_edma_probe()
309 fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma"); in fsl_edma_probe()
310 if (IS_ERR(fsl_edma->dmaclk)) { in fsl_edma_probe()
311 dev_err(&pdev->dev, "Missing DMA block clock.\n"); in fsl_edma_probe()
312 return PTR_ERR(fsl_edma->dmaclk); in fsl_edma_probe()
315 ret = clk_prepare_enable(fsl_edma->dmaclk); in fsl_edma_probe()
317 dev_err(&pdev->dev, "DMA clk block failed.\n"); in fsl_edma_probe()
322 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { in fsl_edma_probe()
326 fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res); in fsl_edma_probe()
327 if (IS_ERR(fsl_edma->muxbase[i])) { in fsl_edma_probe()
330 return PTR_ERR(fsl_edma->muxbase[i]); in fsl_edma_probe()
334 fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname); in fsl_edma_probe()
335 if (IS_ERR(fsl_edma->muxclk[i])) { in fsl_edma_probe()
336 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); in fsl_edma_probe()
339 return PTR_ERR(fsl_edma->muxclk[i]); in fsl_edma_probe()
342 ret = clk_prepare_enable(fsl_edma->muxclk[i]); in fsl_edma_probe()
349 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); in fsl_edma_probe()
351 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); in fsl_edma_probe()
352 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_probe()
353 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; in fsl_edma_probe()
355 fsl_chan->edma = fsl_edma; in fsl_edma_probe()
356 fsl_chan->pm_state = RUNNING; in fsl_edma_probe()
357 fsl_chan->slave_id = 0; in fsl_edma_probe()
358 fsl_chan->idle = true; in fsl_edma_probe()
359 fsl_chan->dma_dir = DMA_NONE; in fsl_edma_probe()
360 fsl_chan->vchan.desc_free = fsl_edma_free_desc; in fsl_edma_probe()
361 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); in fsl_edma_probe()
363 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr); in fsl_edma_probe()
367 edma_writel(fsl_edma, ~0, regs->intl); in fsl_edma_probe()
368 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); in fsl_edma_probe()
372 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
373 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
374 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); in fsl_edma_probe()
376 fsl_edma->dma_dev.dev = &pdev->dev; in fsl_edma_probe()
377 fsl_edma->dma_dev.device_alloc_chan_resources in fsl_edma_probe()
379 fsl_edma->dma_dev.device_free_chan_resources in fsl_edma_probe()
381 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; in fsl_edma_probe()
382 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; in fsl_edma_probe()
383 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; in fsl_edma_probe()
384 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; in fsl_edma_probe()
385 fsl_edma->dma_dev.device_pause = fsl_edma_pause; in fsl_edma_probe()
386 fsl_edma->dma_dev.device_resume = fsl_edma_resume; in fsl_edma_probe()
387 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; in fsl_edma_probe()
388 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; in fsl_edma_probe()
389 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; in fsl_edma_probe()
391 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
392 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; in fsl_edma_probe()
393 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in fsl_edma_probe()
397 ret = dma_async_device_register(&fsl_edma->dma_dev); in fsl_edma_probe()
399 dev_err(&pdev->dev, in fsl_edma_probe()
400 "Can't register Freescale eDMA engine. (%d)\n", ret); in fsl_edma_probe()
401 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_probe()
407 dev_err(&pdev->dev, in fsl_edma_probe()
408 "Can't register Freescale eDMA of_dma. (%d)\n", ret); in fsl_edma_probe()
409 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_probe()
410 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_probe()
415 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_probe()
422 struct device_node *np = pdev->dev.of_node; in fsl_edma_remove()
426 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); in fsl_edma_remove()
428 dma_async_device_unregister(&fsl_edma->dma_dev); in fsl_edma_remove()
429 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); in fsl_edma_remove()
441 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_suspend_late()
442 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_suspend_late()
443 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); in fsl_edma_suspend_late()
445 if (unlikely(!fsl_chan->idle)) { in fsl_edma_suspend_late()
446 dev_warn(dev, "WARN: There is non-idle channel."); in fsl_edma_suspend_late()
451 fsl_chan->pm_state = SUSPENDED; in fsl_edma_suspend_late()
452 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); in fsl_edma_suspend_late()
462 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_resume_early()
465 for (i = 0; i < fsl_edma->n_chans; i++) { in fsl_edma_resume_early()
466 fsl_chan = &fsl_edma->chans[i]; in fsl_edma_resume_early()
467 fsl_chan->pm_state = RUNNING; in fsl_edma_resume_early()
468 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr); in fsl_edma_resume_early()
469 if (fsl_chan->slave_id != 0) in fsl_edma_resume_early()
470 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true); in fsl_edma_resume_early()
473 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); in fsl_edma_resume_early()
479 * eDMA provides the service to others, so it should be suspend late
480 * and resume early. When eDMA suspend, all of the clients should stop
490 .name = "fsl-edma",
510 MODULE_ALIAS("platform:fsl-edma");
511 MODULE_DESCRIPTION("Freescale eDMA engine driver");