Lines Matching +full:lo +full:- +full:sideband
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2010-2014 Xilinx, Inc. All rights reserved.
11 * core that provides high-bandwidth direct memory access between memory
12 * and AXI4-Stream type video target peripherals. The core provides efficient
18 * registers are accessed through an AXI4-Lite slave interface.
21 * provides high-bandwidth one dimensional direct memory access between memory
22 * and AXI4-Stream target peripherals. It supports one receive and one
25 * The AXI CDMA, is a soft IP, which provides high-bandwidth Direct Memory
26 * Access (DMA) between a memory-mapped source address and a memory-mapped
30 * Xilinx IP that provides high-bandwidth direct memory access between
31 * memory and AXI4-Stream target peripherals. It provides scatter gather
50 #include <linux/io-64-nonatomic-lo-hi.h>
219 * struct xilinx_vdma_desc_hw - Hardware Descriptor
240 * struct xilinx_axidma_desc_hw - Hardware Descriptor for AXI DMA
249 * @app: APP Fields @0x20 - 0x30
264 * struct xilinx_aximcdma_desc_hw - Hardware Descriptor for AXI MCDMA
272 * @sideband_status: Status of sideband signals @0x1C
273 * @app: APP Fields @0x20 - 0x30
288 * struct xilinx_cdma_desc_hw - Hardware Descriptor
310 * struct xilinx_vdma_tx_segment - Descriptor segment
322 * struct xilinx_axidma_tx_segment - Descriptor segment
334 * struct xilinx_aximcdma_tx_segment - Descriptor segment
346 * struct xilinx_cdma_tx_segment - Descriptor segment
358 * struct xilinx_dma_tx_descriptor - Per Transaction structure
376 * struct xilinx_dma_chan - Driver specific DMA channel structure
454 * enum xdma_ip_type - DMA IP type.
479 * struct xilinx_dma_device - DMA device structure
488 * @axi_clk: DMA Axi4-lite interace clock
522 readl_poll_timeout_atomic(chan->xdev->regs + chan->ctrl_offset + reg, \
528 return ioread32(chan->xdev->regs + reg); in dma_read()
533 iowrite32(value, chan->xdev->regs + reg); in dma_write()
539 dma_write(chan, chan->desc_offset + reg, value); in vdma_desc_write()
544 return dma_read(chan, chan->ctrl_offset + reg); in dma_ctrl_read()
550 dma_write(chan, chan->ctrl_offset + reg, value); in dma_ctrl_write()
566 * vdma_desc_write_64 - 64-bit descriptor write
580 writel(value_lsb, chan->xdev->regs + chan->desc_offset + reg); in vdma_desc_write_64()
583 writel(value_msb, chan->xdev->regs + chan->desc_offset + reg + 4); in vdma_desc_write_64()
588 lo_hi_writeq(value, chan->xdev->regs + chan->ctrl_offset + reg); in dma_writeq()
594 if (chan->ext_addr) in xilinx_write()
605 if (chan->ext_addr) { in xilinx_axidma_buf()
606 hw->buf_addr = lower_32_bits(buf_addr + sg_used + period_len); in xilinx_axidma_buf()
607 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used + in xilinx_axidma_buf()
610 hw->buf_addr = buf_addr + sg_used + period_len; in xilinx_axidma_buf()
618 if (chan->ext_addr) { in xilinx_aximcdma_buf()
619 hw->buf_addr = lower_32_bits(buf_addr + sg_used); in xilinx_aximcdma_buf()
620 hw->buf_addr_msb = upper_32_bits(buf_addr + sg_used); in xilinx_aximcdma_buf()
622 hw->buf_addr = buf_addr + sg_used; in xilinx_aximcdma_buf()
626 /* -----------------------------------------------------------------------------
631 * xilinx_vdma_alloc_tx_segment - Allocate transaction segment
642 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); in xilinx_vdma_alloc_tx_segment()
646 segment->phys = phys; in xilinx_vdma_alloc_tx_segment()
652 * xilinx_cdma_alloc_tx_segment - Allocate transaction segment
663 segment = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &phys); in xilinx_cdma_alloc_tx_segment()
667 segment->phys = phys; in xilinx_cdma_alloc_tx_segment()
673 * xilinx_axidma_alloc_tx_segment - Allocate transaction segment
684 spin_lock_irqsave(&chan->lock, flags); in xilinx_axidma_alloc_tx_segment()
685 if (!list_empty(&chan->free_seg_list)) { in xilinx_axidma_alloc_tx_segment()
686 segment = list_first_entry(&chan->free_seg_list, in xilinx_axidma_alloc_tx_segment()
689 list_del(&segment->node); in xilinx_axidma_alloc_tx_segment()
691 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_axidma_alloc_tx_segment()
694 dev_dbg(chan->dev, "Could not find free tx segment\n"); in xilinx_axidma_alloc_tx_segment()
700 * xilinx_aximcdma_alloc_tx_segment - Allocate transaction segment
711 spin_lock_irqsave(&chan->lock, flags); in xilinx_aximcdma_alloc_tx_segment()
712 if (!list_empty(&chan->free_seg_list)) { in xilinx_aximcdma_alloc_tx_segment()
713 segment = list_first_entry(&chan->free_seg_list, in xilinx_aximcdma_alloc_tx_segment()
716 list_del(&segment->node); in xilinx_aximcdma_alloc_tx_segment()
718 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_aximcdma_alloc_tx_segment()
725 u32 next_desc = hw->next_desc; in xilinx_dma_clean_hw_desc()
726 u32 next_desc_msb = hw->next_desc_msb; in xilinx_dma_clean_hw_desc()
730 hw->next_desc = next_desc; in xilinx_dma_clean_hw_desc()
731 hw->next_desc_msb = next_desc_msb; in xilinx_dma_clean_hw_desc()
736 u32 next_desc = hw->next_desc; in xilinx_mcdma_clean_hw_desc()
737 u32 next_desc_msb = hw->next_desc_msb; in xilinx_mcdma_clean_hw_desc()
741 hw->next_desc = next_desc; in xilinx_mcdma_clean_hw_desc()
742 hw->next_desc_msb = next_desc_msb; in xilinx_mcdma_clean_hw_desc()
746 * xilinx_dma_free_tx_segment - Free transaction segment
753 xilinx_dma_clean_hw_desc(&segment->hw); in xilinx_dma_free_tx_segment()
755 list_add_tail(&segment->node, &chan->free_seg_list); in xilinx_dma_free_tx_segment()
759 * xilinx_mcdma_free_tx_segment - Free transaction segment
767 xilinx_mcdma_clean_hw_desc(&segment->hw); in xilinx_mcdma_free_tx_segment()
769 list_add_tail(&segment->node, &chan->free_seg_list); in xilinx_mcdma_free_tx_segment()
773 * xilinx_cdma_free_tx_segment - Free transaction segment
780 dma_pool_free(chan->desc_pool, segment, segment->phys); in xilinx_cdma_free_tx_segment()
784 * xilinx_vdma_free_tx_segment - Free transaction segment
791 dma_pool_free(chan->desc_pool, segment, segment->phys); in xilinx_vdma_free_tx_segment()
795 * xilinx_dma_tx_descriptor - Allocate transaction descriptor
809 INIT_LIST_HEAD(&desc->segments); in xilinx_dma_alloc_tx_descriptor()
815 * xilinx_dma_free_tx_descriptor - Free transaction descriptor
831 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_free_tx_descriptor()
832 list_for_each_entry_safe(segment, next, &desc->segments, node) { in xilinx_dma_free_tx_descriptor()
833 list_del(&segment->node); in xilinx_dma_free_tx_descriptor()
836 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_free_tx_descriptor()
838 &desc->segments, node) { in xilinx_dma_free_tx_descriptor()
839 list_del(&cdma_segment->node); in xilinx_dma_free_tx_descriptor()
842 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_free_tx_descriptor()
844 &desc->segments, node) { in xilinx_dma_free_tx_descriptor()
845 list_del(&axidma_segment->node); in xilinx_dma_free_tx_descriptor()
850 &desc->segments, node) { in xilinx_dma_free_tx_descriptor()
851 list_del(&aximcdma_segment->node); in xilinx_dma_free_tx_descriptor()
862 * xilinx_dma_free_desc_list - Free descriptors list
872 list_del(&desc->node); in xilinx_dma_free_desc_list()
878 * xilinx_dma_free_descriptors - Free channel descriptors
885 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_descriptors()
887 xilinx_dma_free_desc_list(chan, &chan->pending_list); in xilinx_dma_free_descriptors()
888 xilinx_dma_free_desc_list(chan, &chan->done_list); in xilinx_dma_free_descriptors()
889 xilinx_dma_free_desc_list(chan, &chan->active_list); in xilinx_dma_free_descriptors()
891 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_descriptors()
895 * xilinx_dma_free_chan_resources - Free channel resources
903 dev_dbg(chan->dev, "Free all channel resources.\n"); in xilinx_dma_free_chan_resources()
907 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_free_chan_resources()
908 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_chan_resources()
909 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_free_chan_resources()
910 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_chan_resources()
913 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * in xilinx_dma_free_chan_resources()
914 XILINX_DMA_NUM_DESCS, chan->seg_v, in xilinx_dma_free_chan_resources()
915 chan->seg_p); in xilinx_dma_free_chan_resources()
918 dma_free_coherent(chan->dev, sizeof(*chan->cyclic_seg_v), in xilinx_dma_free_chan_resources()
919 chan->cyclic_seg_v, chan->cyclic_seg_p); in xilinx_dma_free_chan_resources()
922 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_free_chan_resources()
923 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_free_chan_resources()
924 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_free_chan_resources()
925 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_free_chan_resources()
928 dma_free_coherent(chan->dev, sizeof(*chan->seg_mv) * in xilinx_dma_free_chan_resources()
929 XILINX_DMA_NUM_DESCS, chan->seg_mv, in xilinx_dma_free_chan_resources()
930 chan->seg_p); in xilinx_dma_free_chan_resources()
933 if (chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA && in xilinx_dma_free_chan_resources()
934 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA) { in xilinx_dma_free_chan_resources()
935 dma_pool_destroy(chan->desc_pool); in xilinx_dma_free_chan_resources()
936 chan->desc_pool = NULL; in xilinx_dma_free_chan_resources()
942 * xilinx_dma_get_residue - Compute residue for a given descriptor
960 list_for_each(entry, &desc->segments) { in xilinx_dma_get_residue()
961 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_get_residue()
965 cdma_hw = &cdma_seg->hw; in xilinx_dma_get_residue()
966 residue += (cdma_hw->control - cdma_hw->status) & in xilinx_dma_get_residue()
967 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
968 } else if (chan->xdev->dma_config->dmatype == in xilinx_dma_get_residue()
973 axidma_hw = &axidma_seg->hw; in xilinx_dma_get_residue()
974 residue += (axidma_hw->control - axidma_hw->status) & in xilinx_dma_get_residue()
975 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
981 aximcdma_hw = &aximcdma_seg->hw; in xilinx_dma_get_residue()
983 (aximcdma_hw->control - aximcdma_hw->status) & in xilinx_dma_get_residue()
984 chan->xdev->max_buffer_len; in xilinx_dma_get_residue()
992 * xilinx_dma_chan_handle_cyclic - Cyclic dma callback
1004 callback = desc->async_tx.callback; in xilinx_dma_chan_handle_cyclic()
1005 callback_param = desc->async_tx.callback_param; in xilinx_dma_chan_handle_cyclic()
1007 spin_unlock_irqrestore(&chan->lock, *flags); in xilinx_dma_chan_handle_cyclic()
1009 spin_lock_irqsave(&chan->lock, *flags); in xilinx_dma_chan_handle_cyclic()
1014 * xilinx_dma_chan_desc_cleanup - Clean channel descriptors
1022 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1024 list_for_each_entry_safe(desc, next, &chan->done_list, node) { in xilinx_dma_chan_desc_cleanup()
1027 if (desc->cyclic) { in xilinx_dma_chan_desc_cleanup()
1033 list_del(&desc->node); in xilinx_dma_chan_desc_cleanup()
1035 if (unlikely(desc->err)) { in xilinx_dma_chan_desc_cleanup()
1036 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_dma_chan_desc_cleanup()
1044 result.residue = desc->residue; in xilinx_dma_chan_desc_cleanup()
1047 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1048 dmaengine_desc_get_callback_invoke(&desc->async_tx, &result); in xilinx_dma_chan_desc_cleanup()
1049 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1052 dma_run_dependencies(&desc->async_tx); in xilinx_dma_chan_desc_cleanup()
1059 if (chan->terminating) in xilinx_dma_chan_desc_cleanup()
1063 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_chan_desc_cleanup()
1067 * xilinx_dma_do_tasklet - Schedule completion tasklet
1078 * xilinx_dma_alloc_chan_resources - Allocate channel resources
1089 if (chan->desc_pool) in xilinx_dma_alloc_chan_resources()
1096 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_alloc_chan_resources()
1098 chan->seg_v = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1099 sizeof(*chan->seg_v) * XILINX_DMA_NUM_DESCS, in xilinx_dma_alloc_chan_resources()
1100 &chan->seg_p, GFP_KERNEL); in xilinx_dma_alloc_chan_resources()
1101 if (!chan->seg_v) { in xilinx_dma_alloc_chan_resources()
1102 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1104 chan->id); in xilinx_dma_alloc_chan_resources()
1105 return -ENOMEM; in xilinx_dma_alloc_chan_resources()
1113 chan->cyclic_seg_v = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1114 sizeof(*chan->cyclic_seg_v), in xilinx_dma_alloc_chan_resources()
1115 &chan->cyclic_seg_p, in xilinx_dma_alloc_chan_resources()
1117 if (!chan->cyclic_seg_v) { in xilinx_dma_alloc_chan_resources()
1118 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1120 dma_free_coherent(chan->dev, sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1121 XILINX_DMA_NUM_DESCS, chan->seg_v, in xilinx_dma_alloc_chan_resources()
1122 chan->seg_p); in xilinx_dma_alloc_chan_resources()
1123 return -ENOMEM; in xilinx_dma_alloc_chan_resources()
1125 chan->cyclic_seg_v->phys = chan->cyclic_seg_p; in xilinx_dma_alloc_chan_resources()
1128 chan->seg_v[i].hw.next_desc = in xilinx_dma_alloc_chan_resources()
1129 lower_32_bits(chan->seg_p + sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1131 chan->seg_v[i].hw.next_desc_msb = in xilinx_dma_alloc_chan_resources()
1132 upper_32_bits(chan->seg_p + sizeof(*chan->seg_v) * in xilinx_dma_alloc_chan_resources()
1134 chan->seg_v[i].phys = chan->seg_p + in xilinx_dma_alloc_chan_resources()
1135 sizeof(*chan->seg_v) * i; in xilinx_dma_alloc_chan_resources()
1136 list_add_tail(&chan->seg_v[i].node, in xilinx_dma_alloc_chan_resources()
1137 &chan->free_seg_list); in xilinx_dma_alloc_chan_resources()
1139 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_alloc_chan_resources()
1141 chan->seg_mv = dma_alloc_coherent(chan->dev, in xilinx_dma_alloc_chan_resources()
1142 sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1144 &chan->seg_p, GFP_KERNEL); in xilinx_dma_alloc_chan_resources()
1145 if (!chan->seg_mv) { in xilinx_dma_alloc_chan_resources()
1146 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1148 chan->id); in xilinx_dma_alloc_chan_resources()
1149 return -ENOMEM; in xilinx_dma_alloc_chan_resources()
1152 chan->seg_mv[i].hw.next_desc = in xilinx_dma_alloc_chan_resources()
1153 lower_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1155 chan->seg_mv[i].hw.next_desc_msb = in xilinx_dma_alloc_chan_resources()
1156 upper_32_bits(chan->seg_p + sizeof(*chan->seg_mv) * in xilinx_dma_alloc_chan_resources()
1158 chan->seg_mv[i].phys = chan->seg_p + in xilinx_dma_alloc_chan_resources()
1159 sizeof(*chan->seg_mv) * i; in xilinx_dma_alloc_chan_resources()
1160 list_add_tail(&chan->seg_mv[i].node, in xilinx_dma_alloc_chan_resources()
1161 &chan->free_seg_list); in xilinx_dma_alloc_chan_resources()
1163 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_alloc_chan_resources()
1164 chan->desc_pool = dma_pool_create("xilinx_cdma_desc_pool", in xilinx_dma_alloc_chan_resources()
1165 chan->dev, in xilinx_dma_alloc_chan_resources()
1170 chan->desc_pool = dma_pool_create("xilinx_vdma_desc_pool", in xilinx_dma_alloc_chan_resources()
1171 chan->dev, in xilinx_dma_alloc_chan_resources()
1177 if (!chan->desc_pool && in xilinx_dma_alloc_chan_resources()
1178 ((chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIDMA) && in xilinx_dma_alloc_chan_resources()
1179 chan->xdev->dma_config->dmatype != XDMA_TYPE_AXIMCDMA)) { in xilinx_dma_alloc_chan_resources()
1180 dev_err(chan->dev, in xilinx_dma_alloc_chan_resources()
1182 chan->id); in xilinx_dma_alloc_chan_resources()
1183 return -ENOMEM; in xilinx_dma_alloc_chan_resources()
1188 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_alloc_chan_resources()
1196 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) in xilinx_dma_alloc_chan_resources()
1204 * xilinx_dma_calc_copysize - Calculate the amount of data to copy
1216 copy = min_t(size_t, size - done, in xilinx_dma_calc_copysize()
1217 chan->xdev->max_buffer_len); in xilinx_dma_calc_copysize()
1220 chan->xdev->common.copy_align) { in xilinx_dma_calc_copysize()
1226 (1 << chan->xdev->common.copy_align)); in xilinx_dma_calc_copysize()
1232 * xilinx_dma_tx_status - Get DMA transaction status
1253 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_tx_status()
1254 if (!list_empty(&chan->active_list)) { in xilinx_dma_tx_status()
1255 desc = list_last_entry(&chan->active_list, in xilinx_dma_tx_status()
1261 if (chan->has_sg && chan->xdev->dma_config->dmatype != XDMA_TYPE_VDMA) in xilinx_dma_tx_status()
1264 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_tx_status()
1272 * xilinx_dma_stop_transfer - Halt DMA channel
1290 * xilinx_cdma_stop_transfer - Wait for the current transfer to complete
1305 * xilinx_dma_start - Start DMA channel
1321 dev_err(chan->dev, "Cannot start channel %p: %x\n", in xilinx_dma_start()
1324 chan->err = true; in xilinx_dma_start()
1329 * xilinx_vdma_start_transfer - Starts VDMA transfer
1334 struct xilinx_vdma_config *config = &chan->config; in xilinx_vdma_start_transfer()
1341 if (chan->err) in xilinx_vdma_start_transfer()
1344 if (!chan->idle) in xilinx_vdma_start_transfer()
1347 if (list_empty(&chan->pending_list)) in xilinx_vdma_start_transfer()
1350 desc = list_first_entry(&chan->pending_list, in xilinx_vdma_start_transfer()
1354 if (chan->has_vflip) { in xilinx_vdma_start_transfer()
1357 reg |= config->vflip_en; in xilinx_vdma_start_transfer()
1364 if (config->frm_cnt_en) in xilinx_vdma_start_transfer()
1370 if (config->park) in xilinx_vdma_start_transfer()
1377 j = chan->desc_submitcount; in xilinx_vdma_start_transfer()
1379 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_vdma_start_transfer()
1391 if (chan->err) in xilinx_vdma_start_transfer()
1395 if (chan->desc_submitcount < chan->num_frms) in xilinx_vdma_start_transfer()
1396 i = chan->desc_submitcount; in xilinx_vdma_start_transfer()
1398 list_for_each_entry(segment, &desc->segments, node) { in xilinx_vdma_start_transfer()
1399 if (chan->ext_addr) in xilinx_vdma_start_transfer()
1402 segment->hw.buf_addr, in xilinx_vdma_start_transfer()
1403 segment->hw.buf_addr_msb); in xilinx_vdma_start_transfer()
1407 segment->hw.buf_addr); in xilinx_vdma_start_transfer()
1416 vdma_desc_write(chan, XILINX_DMA_REG_HSIZE, last->hw.hsize); in xilinx_vdma_start_transfer()
1418 last->hw.stride); in xilinx_vdma_start_transfer()
1419 vdma_desc_write(chan, XILINX_DMA_REG_VSIZE, last->hw.vsize); in xilinx_vdma_start_transfer()
1421 chan->desc_submitcount++; in xilinx_vdma_start_transfer()
1422 chan->desc_pendingcount--; in xilinx_vdma_start_transfer()
1423 list_del(&desc->node); in xilinx_vdma_start_transfer()
1424 list_add_tail(&desc->node, &chan->active_list); in xilinx_vdma_start_transfer()
1425 if (chan->desc_submitcount == chan->num_frms) in xilinx_vdma_start_transfer()
1426 chan->desc_submitcount = 0; in xilinx_vdma_start_transfer()
1428 chan->idle = false; in xilinx_vdma_start_transfer()
1432 * xilinx_cdma_start_transfer - Starts cdma transfer
1441 if (chan->err) in xilinx_cdma_start_transfer()
1444 if (!chan->idle) in xilinx_cdma_start_transfer()
1447 if (list_empty(&chan->pending_list)) in xilinx_cdma_start_transfer()
1450 head_desc = list_first_entry(&chan->pending_list, in xilinx_cdma_start_transfer()
1452 tail_desc = list_last_entry(&chan->pending_list, in xilinx_cdma_start_transfer()
1454 tail_segment = list_last_entry(&tail_desc->segments, in xilinx_cdma_start_transfer()
1457 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { in xilinx_cdma_start_transfer()
1459 ctrl_reg |= chan->desc_pendingcount << in xilinx_cdma_start_transfer()
1464 if (chan->has_sg) { in xilinx_cdma_start_transfer()
1472 head_desc->async_tx.phys); in xilinx_cdma_start_transfer()
1476 tail_segment->phys); in xilinx_cdma_start_transfer()
1482 segment = list_first_entry(&head_desc->segments, in xilinx_cdma_start_transfer()
1486 hw = &segment->hw; in xilinx_cdma_start_transfer()
1489 xilinx_prep_dma_addr_t(hw->src_addr)); in xilinx_cdma_start_transfer()
1491 xilinx_prep_dma_addr_t(hw->dest_addr)); in xilinx_cdma_start_transfer()
1495 hw->control & chan->xdev->max_buffer_len); in xilinx_cdma_start_transfer()
1498 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_cdma_start_transfer()
1499 chan->desc_pendingcount = 0; in xilinx_cdma_start_transfer()
1500 chan->idle = false; in xilinx_cdma_start_transfer()
1504 * xilinx_dma_start_transfer - Starts DMA transfer
1513 if (chan->err) in xilinx_dma_start_transfer()
1516 if (list_empty(&chan->pending_list)) in xilinx_dma_start_transfer()
1519 if (!chan->idle) in xilinx_dma_start_transfer()
1522 head_desc = list_first_entry(&chan->pending_list, in xilinx_dma_start_transfer()
1524 tail_desc = list_last_entry(&chan->pending_list, in xilinx_dma_start_transfer()
1526 tail_segment = list_last_entry(&tail_desc->segments, in xilinx_dma_start_transfer()
1531 if (chan->desc_pendingcount <= XILINX_DMA_COALESCE_MAX) { in xilinx_dma_start_transfer()
1533 reg |= chan->desc_pendingcount << in xilinx_dma_start_transfer()
1538 if (chan->has_sg) in xilinx_dma_start_transfer()
1540 head_desc->async_tx.phys); in xilinx_dma_start_transfer()
1544 if (chan->err) in xilinx_dma_start_transfer()
1548 if (chan->has_sg) { in xilinx_dma_start_transfer()
1549 if (chan->cyclic) in xilinx_dma_start_transfer()
1551 chan->cyclic_seg_v->phys); in xilinx_dma_start_transfer()
1554 tail_segment->phys); in xilinx_dma_start_transfer()
1559 segment = list_first_entry(&head_desc->segments, in xilinx_dma_start_transfer()
1562 hw = &segment->hw; in xilinx_dma_start_transfer()
1565 xilinx_prep_dma_addr_t(hw->buf_addr)); in xilinx_dma_start_transfer()
1569 hw->control & chan->xdev->max_buffer_len); in xilinx_dma_start_transfer()
1572 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_dma_start_transfer()
1573 chan->desc_pendingcount = 0; in xilinx_dma_start_transfer()
1574 chan->idle = false; in xilinx_dma_start_transfer()
1578 * xilinx_mcdma_start_transfer - Starts MCDMA transfer
1592 if (chan->err) in xilinx_mcdma_start_transfer()
1595 if (!chan->idle) in xilinx_mcdma_start_transfer()
1598 if (list_empty(&chan->pending_list)) in xilinx_mcdma_start_transfer()
1601 head_desc = list_first_entry(&chan->pending_list, in xilinx_mcdma_start_transfer()
1603 tail_desc = list_last_entry(&chan->pending_list, in xilinx_mcdma_start_transfer()
1605 tail_segment = list_last_entry(&tail_desc->segments, in xilinx_mcdma_start_transfer()
1608 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); in xilinx_mcdma_start_transfer()
1610 if (chan->desc_pendingcount <= XILINX_MCDMA_COALESCE_MAX) { in xilinx_mcdma_start_transfer()
1612 reg |= chan->desc_pendingcount << in xilinx_mcdma_start_transfer()
1617 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); in xilinx_mcdma_start_transfer()
1620 xilinx_write(chan, XILINX_MCDMA_CHAN_CDESC_OFFSET(chan->tdest), in xilinx_mcdma_start_transfer()
1621 head_desc->async_tx.phys); in xilinx_mcdma_start_transfer()
1625 reg |= BIT(chan->tdest); in xilinx_mcdma_start_transfer()
1629 reg = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest)); in xilinx_mcdma_start_transfer()
1631 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_CR_OFFSET(chan->tdest), reg); in xilinx_mcdma_start_transfer()
1635 if (chan->err) in xilinx_mcdma_start_transfer()
1639 xilinx_write(chan, XILINX_MCDMA_CHAN_TDESC_OFFSET(chan->tdest), in xilinx_mcdma_start_transfer()
1640 tail_segment->phys); in xilinx_mcdma_start_transfer()
1642 list_splice_tail_init(&chan->pending_list, &chan->active_list); in xilinx_mcdma_start_transfer()
1643 chan->desc_pendingcount = 0; in xilinx_mcdma_start_transfer()
1644 chan->idle = false; in xilinx_mcdma_start_transfer()
1648 * xilinx_dma_issue_pending - Issue pending transactions
1656 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_issue_pending()
1657 chan->start_transfer(chan); in xilinx_dma_issue_pending()
1658 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_issue_pending()
1662 * xilinx_dma_complete_descriptor - Mark the active descriptor as complete
1672 if (list_empty(&chan->active_list)) in xilinx_dma_complete_descriptor()
1675 list_for_each_entry_safe(desc, next, &chan->active_list, node) { in xilinx_dma_complete_descriptor()
1676 if (chan->has_sg && chan->xdev->dma_config->dmatype != in xilinx_dma_complete_descriptor()
1678 desc->residue = xilinx_dma_get_residue(chan, desc); in xilinx_dma_complete_descriptor()
1680 desc->residue = 0; in xilinx_dma_complete_descriptor()
1681 desc->err = chan->err; in xilinx_dma_complete_descriptor()
1683 list_del(&desc->node); in xilinx_dma_complete_descriptor()
1684 if (!desc->cyclic) in xilinx_dma_complete_descriptor()
1685 dma_cookie_complete(&desc->async_tx); in xilinx_dma_complete_descriptor()
1686 list_add_tail(&desc->node, &chan->done_list); in xilinx_dma_complete_descriptor()
1691 * xilinx_dma_reset - Reset DMA channel
1709 dev_err(chan->dev, "reset timeout, cr %x, sr %x\n", in xilinx_dma_reset()
1712 return -ETIMEDOUT; in xilinx_dma_reset()
1715 chan->err = false; in xilinx_dma_reset()
1716 chan->idle = true; in xilinx_dma_reset()
1717 chan->desc_pendingcount = 0; in xilinx_dma_reset()
1718 chan->desc_submitcount = 0; in xilinx_dma_reset()
1724 * xilinx_dma_chan_reset - Reset DMA channel and enable interrupts
1746 * xilinx_mcdma_irq_handler - MCDMA Interrupt handler
1757 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_mcdma_irq_handler()
1769 if (chan->direction == DMA_DEV_TO_MEM) in xilinx_mcdma_irq_handler()
1770 chan_offset = chan->xdev->dma_config->max_channels / 2; in xilinx_mcdma_irq_handler()
1772 chan_offset = chan_offset + (chan_id - 1); in xilinx_mcdma_irq_handler()
1773 chan = chan->xdev->chan[chan_offset]; in xilinx_mcdma_irq_handler()
1775 status = dma_ctrl_read(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest)); in xilinx_mcdma_irq_handler()
1779 dma_ctrl_write(chan, XILINX_MCDMA_CHAN_SR_OFFSET(chan->tdest), in xilinx_mcdma_irq_handler()
1783 dev_err(chan->dev, "Channel %p has errors %x cdr %x tdr %x\n", in xilinx_mcdma_irq_handler()
1787 (chan->tdest)), in xilinx_mcdma_irq_handler()
1789 (chan->tdest))); in xilinx_mcdma_irq_handler()
1790 chan->err = true; in xilinx_mcdma_irq_handler()
1798 dev_dbg(chan->dev, "Inter-packet latency too long\n"); in xilinx_mcdma_irq_handler()
1802 spin_lock(&chan->lock); in xilinx_mcdma_irq_handler()
1804 chan->idle = true; in xilinx_mcdma_irq_handler()
1805 chan->start_transfer(chan); in xilinx_mcdma_irq_handler()
1806 spin_unlock(&chan->lock); in xilinx_mcdma_irq_handler()
1809 tasklet_schedule(&chan->tasklet); in xilinx_mcdma_irq_handler()
1814 * xilinx_dma_irq_handler - DMA Interrupt handler
1846 if (!chan->flush_on_fsync || in xilinx_dma_irq_handler()
1848 dev_err(chan->dev, in xilinx_dma_irq_handler()
1853 chan->err = true; in xilinx_dma_irq_handler()
1862 dev_dbg(chan->dev, "Inter-packet latency too long\n"); in xilinx_dma_irq_handler()
1866 spin_lock(&chan->lock); in xilinx_dma_irq_handler()
1868 chan->idle = true; in xilinx_dma_irq_handler()
1869 chan->start_transfer(chan); in xilinx_dma_irq_handler()
1870 spin_unlock(&chan->lock); in xilinx_dma_irq_handler()
1873 tasklet_schedule(&chan->tasklet); in xilinx_dma_irq_handler()
1878 * append_desc_queue - Queuing descriptor
1891 if (list_empty(&chan->pending_list)) in append_desc_queue()
1898 tail_desc = list_last_entry(&chan->pending_list, in append_desc_queue()
1900 if (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in append_desc_queue()
1901 tail_segment = list_last_entry(&tail_desc->segments, in append_desc_queue()
1904 tail_segment->hw.next_desc = (u32)desc->async_tx.phys; in append_desc_queue()
1905 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in append_desc_queue()
1906 cdma_tail_segment = list_last_entry(&tail_desc->segments, in append_desc_queue()
1909 cdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; in append_desc_queue()
1910 } else if (chan->xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in append_desc_queue()
1911 axidma_tail_segment = list_last_entry(&tail_desc->segments, in append_desc_queue()
1914 axidma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; in append_desc_queue()
1917 list_last_entry(&tail_desc->segments, in append_desc_queue()
1920 aximcdma_tail_segment->hw.next_desc = (u32)desc->async_tx.phys; in append_desc_queue()
1928 list_add_tail(&desc->node, &chan->pending_list); in append_desc_queue()
1929 chan->desc_pendingcount++; in append_desc_queue()
1931 if (chan->has_sg && (chan->xdev->dma_config->dmatype == XDMA_TYPE_VDMA) in append_desc_queue()
1932 && unlikely(chan->desc_pendingcount > chan->num_frms)) { in append_desc_queue()
1933 dev_dbg(chan->dev, "desc pendingcount is too high\n"); in append_desc_queue()
1934 chan->desc_pendingcount = chan->num_frms; in append_desc_queue()
1939 * xilinx_dma_tx_submit - Submit DMA transaction
1947 struct xilinx_dma_chan *chan = to_xilinx_chan(tx->chan); in xilinx_dma_tx_submit()
1952 if (chan->cyclic) { in xilinx_dma_tx_submit()
1954 return -EBUSY; in xilinx_dma_tx_submit()
1957 if (chan->err) { in xilinx_dma_tx_submit()
1967 spin_lock_irqsave(&chan->lock, flags); in xilinx_dma_tx_submit()
1974 if (desc->cyclic) in xilinx_dma_tx_submit()
1975 chan->cyclic = true; in xilinx_dma_tx_submit()
1977 chan->terminating = false; in xilinx_dma_tx_submit()
1979 spin_unlock_irqrestore(&chan->lock, flags); in xilinx_dma_tx_submit()
1985 * xilinx_vdma_dma_prep_interleaved - prepare a descriptor for a
2003 if (!is_slave_direction(xt->dir)) in xilinx_vdma_dma_prep_interleaved()
2006 if (!xt->numf || !xt->sgl[0].size) in xilinx_vdma_dma_prep_interleaved()
2009 if (xt->frame_size != 1) in xilinx_vdma_dma_prep_interleaved()
2017 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_vdma_dma_prep_interleaved()
2018 desc->async_tx.tx_submit = xilinx_dma_tx_submit; in xilinx_vdma_dma_prep_interleaved()
2019 async_tx_ack(&desc->async_tx); in xilinx_vdma_dma_prep_interleaved()
2027 hw = &segment->hw; in xilinx_vdma_dma_prep_interleaved()
2028 hw->vsize = xt->numf; in xilinx_vdma_dma_prep_interleaved()
2029 hw->hsize = xt->sgl[0].size; in xilinx_vdma_dma_prep_interleaved()
2030 hw->stride = (xt->sgl[0].icg + xt->sgl[0].size) << in xilinx_vdma_dma_prep_interleaved()
2032 hw->stride |= chan->config.frm_dly << in xilinx_vdma_dma_prep_interleaved()
2035 if (xt->dir != DMA_MEM_TO_DEV) { in xilinx_vdma_dma_prep_interleaved()
2036 if (chan->ext_addr) { in xilinx_vdma_dma_prep_interleaved()
2037 hw->buf_addr = lower_32_bits(xt->dst_start); in xilinx_vdma_dma_prep_interleaved()
2038 hw->buf_addr_msb = upper_32_bits(xt->dst_start); in xilinx_vdma_dma_prep_interleaved()
2040 hw->buf_addr = xt->dst_start; in xilinx_vdma_dma_prep_interleaved()
2043 if (chan->ext_addr) { in xilinx_vdma_dma_prep_interleaved()
2044 hw->buf_addr = lower_32_bits(xt->src_start); in xilinx_vdma_dma_prep_interleaved()
2045 hw->buf_addr_msb = upper_32_bits(xt->src_start); in xilinx_vdma_dma_prep_interleaved()
2047 hw->buf_addr = xt->src_start; in xilinx_vdma_dma_prep_interleaved()
2052 list_add_tail(&segment->node, &desc->segments); in xilinx_vdma_dma_prep_interleaved()
2055 segment = list_first_entry(&desc->segments, in xilinx_vdma_dma_prep_interleaved()
2057 desc->async_tx.phys = segment->phys; in xilinx_vdma_dma_prep_interleaved()
2059 return &desc->async_tx; in xilinx_vdma_dma_prep_interleaved()
2067 * xilinx_cdma_prep_memcpy - prepare descriptors for a memcpy transaction
2085 if (!len || len > chan->xdev->max_buffer_len) in xilinx_cdma_prep_memcpy()
2092 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_cdma_prep_memcpy()
2093 desc->async_tx.tx_submit = xilinx_dma_tx_submit; in xilinx_cdma_prep_memcpy()
2100 hw = &segment->hw; in xilinx_cdma_prep_memcpy()
2101 hw->control = len; in xilinx_cdma_prep_memcpy()
2102 hw->src_addr = dma_src; in xilinx_cdma_prep_memcpy()
2103 hw->dest_addr = dma_dst; in xilinx_cdma_prep_memcpy()
2104 if (chan->ext_addr) { in xilinx_cdma_prep_memcpy()
2105 hw->src_addr_msb = upper_32_bits(dma_src); in xilinx_cdma_prep_memcpy()
2106 hw->dest_addr_msb = upper_32_bits(dma_dst); in xilinx_cdma_prep_memcpy()
2110 list_add_tail(&segment->node, &desc->segments); in xilinx_cdma_prep_memcpy()
2112 desc->async_tx.phys = segment->phys; in xilinx_cdma_prep_memcpy()
2113 hw->next_desc = segment->phys; in xilinx_cdma_prep_memcpy()
2115 return &desc->async_tx; in xilinx_cdma_prep_memcpy()
2123 * xilinx_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2155 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_dma_prep_slave_sg()
2156 desc->async_tx.tx_submit = xilinx_dma_tx_submit; in xilinx_dma_prep_slave_sg()
2177 hw = &segment->hw; in xilinx_dma_prep_slave_sg()
2183 hw->control = copy; in xilinx_dma_prep_slave_sg()
2185 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_dma_prep_slave_sg()
2187 memcpy(hw->app, app_w, sizeof(u32) * in xilinx_dma_prep_slave_sg()
2197 list_add_tail(&segment->node, &desc->segments); in xilinx_dma_prep_slave_sg()
2201 segment = list_first_entry(&desc->segments, in xilinx_dma_prep_slave_sg()
2203 desc->async_tx.phys = segment->phys; in xilinx_dma_prep_slave_sg()
2206 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_dma_prep_slave_sg()
2207 segment->hw.control |= XILINX_DMA_BD_SOP; in xilinx_dma_prep_slave_sg()
2208 segment = list_last_entry(&desc->segments, in xilinx_dma_prep_slave_sg()
2211 segment->hw.control |= XILINX_DMA_BD_EOP; in xilinx_dma_prep_slave_sg()
2214 return &desc->async_tx; in xilinx_dma_prep_slave_sg()
2222 * xilinx_dma_prep_dma_cyclic - prepare descriptors for a DMA_SLAVE transaction
2261 chan->direction = direction; in xilinx_dma_prep_dma_cyclic()
2262 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_dma_prep_dma_cyclic()
2263 desc->async_tx.tx_submit = xilinx_dma_tx_submit; in xilinx_dma_prep_dma_cyclic()
2282 hw = &segment->hw; in xilinx_dma_prep_dma_cyclic()
2285 hw->control = copy; in xilinx_dma_prep_dma_cyclic()
2288 prev->hw.next_desc = segment->phys; in xilinx_dma_prep_dma_cyclic()
2297 list_add_tail(&segment->node, &desc->segments); in xilinx_dma_prep_dma_cyclic()
2301 head_segment = list_first_entry(&desc->segments, in xilinx_dma_prep_dma_cyclic()
2303 desc->async_tx.phys = head_segment->phys; in xilinx_dma_prep_dma_cyclic()
2305 desc->cyclic = true; in xilinx_dma_prep_dma_cyclic()
2310 segment = list_last_entry(&desc->segments, in xilinx_dma_prep_dma_cyclic()
2313 segment->hw.next_desc = (u32) head_segment->phys; in xilinx_dma_prep_dma_cyclic()
2317 head_segment->hw.control |= XILINX_DMA_BD_SOP; in xilinx_dma_prep_dma_cyclic()
2318 segment->hw.control |= XILINX_DMA_BD_EOP; in xilinx_dma_prep_dma_cyclic()
2321 return &desc->async_tx; in xilinx_dma_prep_dma_cyclic()
2329 * xilinx_mcdma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
2362 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); in xilinx_mcdma_prep_slave_sg()
2363 desc->async_tx.tx_submit = xilinx_dma_tx_submit; in xilinx_mcdma_prep_slave_sg()
2382 copy = min_t(size_t, sg_dma_len(sg) - sg_used, in xilinx_mcdma_prep_slave_sg()
2383 chan->xdev->max_buffer_len); in xilinx_mcdma_prep_slave_sg()
2384 hw = &segment->hw; in xilinx_mcdma_prep_slave_sg()
2389 hw->control = copy; in xilinx_mcdma_prep_slave_sg()
2391 if (chan->direction == DMA_MEM_TO_DEV && app_w) { in xilinx_mcdma_prep_slave_sg()
2392 memcpy(hw->app, app_w, sizeof(u32) * in xilinx_mcdma_prep_slave_sg()
2401 list_add_tail(&segment->node, &desc->segments); in xilinx_mcdma_prep_slave_sg()
2405 segment = list_first_entry(&desc->segments, in xilinx_mcdma_prep_slave_sg()
2407 desc->async_tx.phys = segment->phys; in xilinx_mcdma_prep_slave_sg()
2410 if (chan->direction == DMA_MEM_TO_DEV) { in xilinx_mcdma_prep_slave_sg()
2411 segment->hw.control |= XILINX_MCDMA_BD_SOP; in xilinx_mcdma_prep_slave_sg()
2412 segment = list_last_entry(&desc->segments, in xilinx_mcdma_prep_slave_sg()
2415 segment->hw.control |= XILINX_MCDMA_BD_EOP; in xilinx_mcdma_prep_slave_sg()
2418 return &desc->async_tx; in xilinx_mcdma_prep_slave_sg()
2427 * xilinx_dma_terminate_all - Halt the channel and free descriptors
2438 if (!chan->cyclic) { in xilinx_dma_terminate_all()
2439 err = chan->stop_transfer(chan); in xilinx_dma_terminate_all()
2441 dev_err(chan->dev, "Cannot stop channel %p: %x\n", in xilinx_dma_terminate_all()
2444 chan->err = true; in xilinx_dma_terminate_all()
2450 chan->terminating = true; in xilinx_dma_terminate_all()
2452 chan->idle = true; in xilinx_dma_terminate_all()
2454 if (chan->cyclic) { in xilinx_dma_terminate_all()
2458 chan->cyclic = false; in xilinx_dma_terminate_all()
2461 if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg) in xilinx_dma_terminate_all()
2469 * xilinx_dma_channel_set_config - Configure VDMA channel
2470 * Run-time configuration for Axi VDMA, supports:
2472 * . configure interrupt coalescing and inter-packet delay threshold
2487 if (cfg->reset) in xilinx_vdma_channel_set_config()
2492 chan->config.frm_dly = cfg->frm_dly; in xilinx_vdma_channel_set_config()
2493 chan->config.park = cfg->park; in xilinx_vdma_channel_set_config()
2496 chan->config.gen_lock = cfg->gen_lock; in xilinx_vdma_channel_set_config()
2497 chan->config.master = cfg->master; in xilinx_vdma_channel_set_config()
2500 if (cfg->gen_lock && chan->genlock) { in xilinx_vdma_channel_set_config()
2503 dmacr |= cfg->master << XILINX_DMA_DMACR_MASTER_SHIFT; in xilinx_vdma_channel_set_config()
2506 chan->config.frm_cnt_en = cfg->frm_cnt_en; in xilinx_vdma_channel_set_config()
2507 chan->config.vflip_en = cfg->vflip_en; in xilinx_vdma_channel_set_config()
2509 if (cfg->park) in xilinx_vdma_channel_set_config()
2510 chan->config.park_frm = cfg->park_frm; in xilinx_vdma_channel_set_config()
2512 chan->config.park_frm = -1; in xilinx_vdma_channel_set_config()
2514 chan->config.coalesc = cfg->coalesc; in xilinx_vdma_channel_set_config()
2515 chan->config.delay = cfg->delay; in xilinx_vdma_channel_set_config()
2517 if (cfg->coalesc <= XILINX_DMA_DMACR_FRAME_COUNT_MAX) { in xilinx_vdma_channel_set_config()
2519 dmacr |= cfg->coalesc << XILINX_DMA_DMACR_FRAME_COUNT_SHIFT; in xilinx_vdma_channel_set_config()
2520 chan->config.coalesc = cfg->coalesc; in xilinx_vdma_channel_set_config()
2523 if (cfg->delay <= XILINX_DMA_DMACR_DELAY_MAX) { in xilinx_vdma_channel_set_config()
2525 dmacr |= cfg->delay << XILINX_DMA_DMACR_DELAY_SHIFT; in xilinx_vdma_channel_set_config()
2526 chan->config.delay = cfg->delay; in xilinx_vdma_channel_set_config()
2531 dmacr |= cfg->ext_fsync << XILINX_DMA_DMACR_FSYNCSRC_SHIFT; in xilinx_vdma_channel_set_config()
2539 /* -----------------------------------------------------------------------------
2544 * xilinx_dma_chan_remove - Per Channel remove function
2553 if (chan->irq > 0) in xilinx_dma_chan_remove()
2554 free_irq(chan->irq, chan); in xilinx_dma_chan_remove()
2556 tasklet_kill(&chan->tasklet); in xilinx_dma_chan_remove()
2558 list_del(&chan->common.device_node); in xilinx_dma_chan_remove()
2569 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); in axidma_clk_init()
2571 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); in axidma_clk_init()
2573 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); in axidma_clk_init()
2577 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); in axidma_clk_init()
2581 *sg_clk = devm_clk_get(&pdev->dev, "m_axi_sg_aclk"); in axidma_clk_init()
2587 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); in axidma_clk_init()
2593 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); in axidma_clk_init()
2599 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); in axidma_clk_init()
2605 dev_err(&pdev->dev, "failed to enable sg_clk (%d)\n", err); in axidma_clk_init()
2631 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); in axicdma_clk_init()
2633 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); in axicdma_clk_init()
2635 *dev_clk = devm_clk_get(&pdev->dev, "m_axi_aclk"); in axicdma_clk_init()
2637 return dev_err_probe(&pdev->dev, PTR_ERR(*dev_clk), "failed to get dev_clk\n"); in axicdma_clk_init()
2641 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", err); in axicdma_clk_init()
2647 dev_err(&pdev->dev, "failed to enable dev_clk (%d)\n", err); in axicdma_clk_init()
2665 *axi_clk = devm_clk_get(&pdev->dev, "s_axi_lite_aclk"); in axivdma_clk_init()
2667 return dev_err_probe(&pdev->dev, PTR_ERR(*axi_clk), "failed to get axi_aclk\n"); in axivdma_clk_init()
2669 *tx_clk = devm_clk_get(&pdev->dev, "m_axi_mm2s_aclk"); in axivdma_clk_init()
2673 *txs_clk = devm_clk_get(&pdev->dev, "m_axis_mm2s_aclk"); in axivdma_clk_init()
2677 *rx_clk = devm_clk_get(&pdev->dev, "m_axi_s2mm_aclk"); in axivdma_clk_init()
2681 *rxs_clk = devm_clk_get(&pdev->dev, "s_axis_s2mm_aclk"); in axivdma_clk_init()
2687 dev_err(&pdev->dev, "failed to enable axi_clk (%d)\n", in axivdma_clk_init()
2694 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err); in axivdma_clk_init()
2700 dev_err(&pdev->dev, "failed to enable txs_clk (%d)\n", err); in axivdma_clk_init()
2706 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err); in axivdma_clk_init()
2712 dev_err(&pdev->dev, "failed to enable rxs_clk (%d)\n", err); in axivdma_clk_init()
2732 clk_disable_unprepare(xdev->rxs_clk); in xdma_disable_allclks()
2733 clk_disable_unprepare(xdev->rx_clk); in xdma_disable_allclks()
2734 clk_disable_unprepare(xdev->txs_clk); in xdma_disable_allclks()
2735 clk_disable_unprepare(xdev->tx_clk); in xdma_disable_allclks()
2736 clk_disable_unprepare(xdev->axi_clk); in xdma_disable_allclks()
2740 * xilinx_dma_chan_probe - Per Channel Probing
2758 chan = devm_kzalloc(xdev->dev, sizeof(*chan), GFP_KERNEL); in xilinx_dma_chan_probe()
2760 return -ENOMEM; in xilinx_dma_chan_probe()
2762 chan->dev = xdev->dev; in xilinx_dma_chan_probe()
2763 chan->xdev = xdev; in xilinx_dma_chan_probe()
2764 chan->desc_pendingcount = 0x0; in xilinx_dma_chan_probe()
2765 chan->ext_addr = xdev->ext_addr; in xilinx_dma_chan_probe()
2771 chan->idle = true; in xilinx_dma_chan_probe()
2773 spin_lock_init(&chan->lock); in xilinx_dma_chan_probe()
2774 INIT_LIST_HEAD(&chan->pending_list); in xilinx_dma_chan_probe()
2775 INIT_LIST_HEAD(&chan->done_list); in xilinx_dma_chan_probe()
2776 INIT_LIST_HEAD(&chan->active_list); in xilinx_dma_chan_probe()
2777 INIT_LIST_HEAD(&chan->free_seg_list); in xilinx_dma_chan_probe()
2780 has_dre = of_property_read_bool(node, "xlnx,include-dre"); in xilinx_dma_chan_probe()
2782 chan->genlock = of_property_read_bool(node, "xlnx,genlock-mode"); in xilinx_dma_chan_probe()
2786 dev_err(xdev->dev, "missing xlnx,datawidth property\n"); in xilinx_dma_chan_probe()
2796 xdev->common.copy_align = (enum dmaengine_alignment)fls(width - 1); in xilinx_dma_chan_probe()
2798 if (of_device_is_compatible(node, "xlnx,axi-vdma-mm2s-channel") || in xilinx_dma_chan_probe()
2799 of_device_is_compatible(node, "xlnx,axi-dma-mm2s-channel") || in xilinx_dma_chan_probe()
2800 of_device_is_compatible(node, "xlnx,axi-cdma-channel")) { in xilinx_dma_chan_probe()
2801 chan->direction = DMA_MEM_TO_DEV; in xilinx_dma_chan_probe()
2802 chan->id = xdev->mm2s_chan_id++; in xilinx_dma_chan_probe()
2803 chan->tdest = chan->id; in xilinx_dma_chan_probe()
2805 chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET; in xilinx_dma_chan_probe()
2806 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_chan_probe()
2807 chan->desc_offset = XILINX_VDMA_MM2S_DESC_OFFSET; in xilinx_dma_chan_probe()
2808 chan->config.park = 1; in xilinx_dma_chan_probe()
2810 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || in xilinx_dma_chan_probe()
2811 xdev->flush_on_fsync == XILINX_DMA_FLUSH_MM2S) in xilinx_dma_chan_probe()
2812 chan->flush_on_fsync = true; in xilinx_dma_chan_probe()
2815 "xlnx,axi-vdma-s2mm-channel") || in xilinx_dma_chan_probe()
2817 "xlnx,axi-dma-s2mm-channel")) { in xilinx_dma_chan_probe()
2818 chan->direction = DMA_DEV_TO_MEM; in xilinx_dma_chan_probe()
2819 chan->id = xdev->s2mm_chan_id++; in xilinx_dma_chan_probe()
2820 chan->tdest = chan->id - xdev->dma_config->max_channels / 2; in xilinx_dma_chan_probe()
2821 chan->has_vflip = of_property_read_bool(node, in xilinx_dma_chan_probe()
2822 "xlnx,enable-vert-flip"); in xilinx_dma_chan_probe()
2823 if (chan->has_vflip) { in xilinx_dma_chan_probe()
2824 chan->config.vflip_en = dma_read(chan, in xilinx_dma_chan_probe()
2829 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) in xilinx_dma_chan_probe()
2830 chan->ctrl_offset = XILINX_MCDMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
2832 chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET; in xilinx_dma_chan_probe()
2834 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_chan_probe()
2835 chan->desc_offset = XILINX_VDMA_S2MM_DESC_OFFSET; in xilinx_dma_chan_probe()
2836 chan->config.park = 1; in xilinx_dma_chan_probe()
2838 if (xdev->flush_on_fsync == XILINX_DMA_FLUSH_BOTH || in xilinx_dma_chan_probe()
2839 xdev->flush_on_fsync == XILINX_DMA_FLUSH_S2MM) in xilinx_dma_chan_probe()
2840 chan->flush_on_fsync = true; in xilinx_dma_chan_probe()
2843 dev_err(xdev->dev, "Invalid channel compatible node\n"); in xilinx_dma_chan_probe()
2844 return -EINVAL; in xilinx_dma_chan_probe()
2848 chan->irq = irq_of_parse_and_map(node, chan->tdest); in xilinx_dma_chan_probe()
2849 err = request_irq(chan->irq, xdev->dma_config->irq_handler, in xilinx_dma_chan_probe()
2850 IRQF_SHARED, "xilinx-dma-controller", chan); in xilinx_dma_chan_probe()
2852 dev_err(xdev->dev, "unable to request IRQ %d\n", chan->irq); in xilinx_dma_chan_probe()
2856 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_chan_probe()
2857 chan->start_transfer = xilinx_dma_start_transfer; in xilinx_dma_chan_probe()
2858 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2859 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_chan_probe()
2860 chan->start_transfer = xilinx_mcdma_start_transfer; in xilinx_dma_chan_probe()
2861 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2862 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_chan_probe()
2863 chan->start_transfer = xilinx_cdma_start_transfer; in xilinx_dma_chan_probe()
2864 chan->stop_transfer = xilinx_cdma_stop_transfer; in xilinx_dma_chan_probe()
2866 chan->start_transfer = xilinx_vdma_start_transfer; in xilinx_dma_chan_probe()
2867 chan->stop_transfer = xilinx_dma_stop_transfer; in xilinx_dma_chan_probe()
2871 if (xdev->dma_config->dmatype != XDMA_TYPE_VDMA) { in xilinx_dma_chan_probe()
2872 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA || in xilinx_dma_chan_probe()
2875 chan->has_sg = true; in xilinx_dma_chan_probe()
2876 dev_dbg(chan->dev, "ch %d: SG %s\n", chan->id, in xilinx_dma_chan_probe()
2877 chan->has_sg ? "enabled" : "disabled"); in xilinx_dma_chan_probe()
2881 tasklet_setup(&chan->tasklet, xilinx_dma_do_tasklet); in xilinx_dma_chan_probe()
2887 chan->common.device = &xdev->common; in xilinx_dma_chan_probe()
2889 list_add_tail(&chan->common.device_node, &xdev->common.channels); in xilinx_dma_chan_probe()
2890 xdev->chan[chan->id] = chan; in xilinx_dma_chan_probe()
2895 dev_err(xdev->dev, "Reset channel failed\n"); in xilinx_dma_chan_probe()
2903 * xilinx_dma_child_probe - Per child node probe
2904 * It get number of dma-channels per child node from
2905 * device-tree and initializes all the channels.
2918 ret = of_property_read_u32(node, "dma-channels", &nr_channels); in xilinx_dma_child_probe()
2919 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA && ret < 0) in xilinx_dma_child_probe()
2920 dev_warn(xdev->dev, "missing dma-channels property\n"); in xilinx_dma_child_probe()
2929 * of_dma_xilinx_xlate - Translation function
2938 struct xilinx_dma_device *xdev = ofdma->of_dma_data; in of_dma_xilinx_xlate()
2939 int chan_id = dma_spec->args[0]; in of_dma_xilinx_xlate()
2941 if (chan_id >= xdev->dma_config->max_channels || !xdev->chan[chan_id]) in of_dma_xilinx_xlate()
2944 return dma_get_slave_channel(&xdev->chan[chan_id]->common); in of_dma_xilinx_xlate()
2975 { .compatible = "xlnx,axi-dma-1.00.a", .data = &axidma_config },
2976 { .compatible = "xlnx,axi-cdma-1.00.a", .data = &axicdma_config },
2977 { .compatible = "xlnx,axi-vdma-1.00.a", .data = &axivdma_config },
2978 { .compatible = "xlnx,axi-mcdma-1.00.a", .data = &aximcdma_config },
2984 * xilinx_dma_probe - Driver probe function
2994 struct device_node *node = pdev->dev.of_node; in xilinx_dma_probe()
2996 struct device_node *child, *np = pdev->dev.of_node; in xilinx_dma_probe()
3001 xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); in xilinx_dma_probe()
3003 return -ENOMEM; in xilinx_dma_probe()
3005 xdev->dev = &pdev->dev; in xilinx_dma_probe()
3010 if (match && match->data) { in xilinx_dma_probe()
3011 xdev->dma_config = match->data; in xilinx_dma_probe()
3012 clk_init = xdev->dma_config->clk_init; in xilinx_dma_probe()
3016 err = clk_init(pdev, &xdev->axi_clk, &xdev->tx_clk, &xdev->txs_clk, in xilinx_dma_probe()
3017 &xdev->rx_clk, &xdev->rxs_clk); in xilinx_dma_probe()
3022 xdev->regs = devm_platform_ioremap_resource(pdev, 0); in xilinx_dma_probe()
3023 if (IS_ERR(xdev->regs)) { in xilinx_dma_probe()
3024 err = PTR_ERR(xdev->regs); in xilinx_dma_probe()
3028 xdev->max_buffer_len = GENMASK(XILINX_DMA_MAX_TRANS_LEN_MAX - 1, 0); in xilinx_dma_probe()
3029 xdev->s2mm_chan_id = xdev->dma_config->max_channels / 2; in xilinx_dma_probe()
3031 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA || in xilinx_dma_probe()
3032 xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_probe()
3033 if (!of_property_read_u32(node, "xlnx,sg-length-width", in xilinx_dma_probe()
3037 dev_warn(xdev->dev, in xilinx_dma_probe()
3038 "invalid xlnx,sg-length-width property value. Using default width\n"); in xilinx_dma_probe()
3041 dev_warn(xdev->dev, "Please ensure that IP supports buffer length > 23 bits\n"); in xilinx_dma_probe()
3042 xdev->max_buffer_len = in xilinx_dma_probe()
3043 GENMASK(len_width - 1, 0); in xilinx_dma_probe()
3048 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_probe()
3049 err = of_property_read_u32(node, "xlnx,num-fstores", in xilinx_dma_probe()
3052 dev_err(xdev->dev, in xilinx_dma_probe()
3053 "missing xlnx,num-fstores property\n"); in xilinx_dma_probe()
3057 err = of_property_read_u32(node, "xlnx,flush-fsync", in xilinx_dma_probe()
3058 &xdev->flush_on_fsync); in xilinx_dma_probe()
3060 dev_warn(xdev->dev, in xilinx_dma_probe()
3061 "missing xlnx,flush-fsync property\n"); in xilinx_dma_probe()
3066 dev_warn(xdev->dev, "missing xlnx,addrwidth property\n"); in xilinx_dma_probe()
3069 xdev->ext_addr = true; in xilinx_dma_probe()
3071 xdev->ext_addr = false; in xilinx_dma_probe()
3074 err = dma_set_mask_and_coherent(xdev->dev, DMA_BIT_MASK(addr_width)); in xilinx_dma_probe()
3076 dev_err(xdev->dev, "DMA mask error %d\n", err); in xilinx_dma_probe()
3081 xdev->common.dev = &pdev->dev; in xilinx_dma_probe()
3083 INIT_LIST_HEAD(&xdev->common.channels); in xilinx_dma_probe()
3084 if (!(xdev->dma_config->dmatype == XDMA_TYPE_CDMA)) { in xilinx_dma_probe()
3085 dma_cap_set(DMA_SLAVE, xdev->common.cap_mask); in xilinx_dma_probe()
3086 dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask); in xilinx_dma_probe()
3089 xdev->common.device_alloc_chan_resources = in xilinx_dma_probe()
3091 xdev->common.device_free_chan_resources = in xilinx_dma_probe()
3093 xdev->common.device_terminate_all = xilinx_dma_terminate_all; in xilinx_dma_probe()
3094 xdev->common.device_tx_status = xilinx_dma_tx_status; in xilinx_dma_probe()
3095 xdev->common.device_issue_pending = xilinx_dma_issue_pending; in xilinx_dma_probe()
3096 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) { in xilinx_dma_probe()
3097 dma_cap_set(DMA_CYCLIC, xdev->common.cap_mask); in xilinx_dma_probe()
3098 xdev->common.device_prep_slave_sg = xilinx_dma_prep_slave_sg; in xilinx_dma_probe()
3099 xdev->common.device_prep_dma_cyclic = in xilinx_dma_probe()
3102 xdev->common.residue_granularity = in xilinx_dma_probe()
3104 } else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) { in xilinx_dma_probe()
3105 dma_cap_set(DMA_MEMCPY, xdev->common.cap_mask); in xilinx_dma_probe()
3106 xdev->common.device_prep_dma_memcpy = xilinx_cdma_prep_memcpy; in xilinx_dma_probe()
3108 xdev->common.residue_granularity = in xilinx_dma_probe()
3110 } else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) { in xilinx_dma_probe()
3111 xdev->common.device_prep_slave_sg = xilinx_mcdma_prep_slave_sg; in xilinx_dma_probe()
3113 xdev->common.device_prep_interleaved_dma = in xilinx_dma_probe()
3128 if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) { in xilinx_dma_probe()
3129 for (i = 0; i < xdev->dma_config->max_channels; i++) in xilinx_dma_probe()
3130 if (xdev->chan[i]) in xilinx_dma_probe()
3131 xdev->chan[i]->num_frms = num_frames; in xilinx_dma_probe()
3135 err = dma_async_device_register(&xdev->common); in xilinx_dma_probe()
3137 dev_err(xdev->dev, "failed to register the dma device\n"); in xilinx_dma_probe()
3144 dev_err(&pdev->dev, "Unable to register DMA to DT\n"); in xilinx_dma_probe()
3145 dma_async_device_unregister(&xdev->common); in xilinx_dma_probe()
3149 if (xdev->dma_config->dmatype == XDMA_TYPE_AXIDMA) in xilinx_dma_probe()
3150 dev_info(&pdev->dev, "Xilinx AXI DMA Engine Driver Probed!!\n"); in xilinx_dma_probe()
3151 else if (xdev->dma_config->dmatype == XDMA_TYPE_CDMA) in xilinx_dma_probe()
3152 dev_info(&pdev->dev, "Xilinx AXI CDMA Engine Driver Probed!!\n"); in xilinx_dma_probe()
3153 else if (xdev->dma_config->dmatype == XDMA_TYPE_AXIMCDMA) in xilinx_dma_probe()
3154 dev_info(&pdev->dev, "Xilinx AXI MCDMA Engine Driver Probed!!\n"); in xilinx_dma_probe()
3156 dev_info(&pdev->dev, "Xilinx AXI VDMA Engine Driver Probed!!\n"); in xilinx_dma_probe()
3161 for (i = 0; i < xdev->dma_config->max_channels; i++) in xilinx_dma_probe()
3162 if (xdev->chan[i]) in xilinx_dma_probe()
3163 xilinx_dma_chan_remove(xdev->chan[i]); in xilinx_dma_probe()
3171 * xilinx_dma_remove - Driver remove function
3181 of_dma_controller_free(pdev->dev.of_node); in xilinx_dma_remove()
3183 dma_async_device_unregister(&xdev->common); in xilinx_dma_remove()
3185 for (i = 0; i < xdev->dma_config->max_channels; i++) in xilinx_dma_remove()
3186 if (xdev->chan[i]) in xilinx_dma_remove()
3187 xilinx_dma_chan_remove(xdev->chan[i]); in xilinx_dma_remove()
3196 .name = "xilinx-vdma",