Lines Matching +full:interleave +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
24 #include <asm/intel-family.h>
68 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
69 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
70 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
71 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
72 0x100, 0x108, 0x110, 0x118, /* 20-23 */
105 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
106 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
107 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, /* 10-14 */
108 0xdc, 0xe4, 0xec, 0xf4, 0xfc, /* 15-19 */
109 0x104, 0x10c, 0x114, 0x11c, /* 20-23 */
144 int interleave) in sad_pkg() argument
146 return GET_BITFIELD(reg, table[interleave].start, in sad_pkg()
147 table[interleave].end); in sad_pkg()
205 /* Device 15, functions 2-5 */
251 /* Device 16, functions 2-7 */
291 #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */
480 /* Optional, mode 2HA */
507 * - 1 IMC
508 * - 3 DDR3 channels, 2 DPC per channel
510 * - 1 or 2 IMC
511 * - 4 DDR4 channels, 3 DPC per channel
513 * - 2 IMC
514 * - 4 DDR4 channels, 3 DPC per channel
516 * - 2 IMC
517 * - each IMC interfaces with a SMI 2 channel
518 * - each SMI channel interfaces with a scalable memory buffer
519 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
583 /* Memory controller, TAD tables, error injection - 2-8-0, 2-9-0 (2 of these) */
585 /* DRAM channel stuff; bank addrs, dimmmtr, etc.. 2-8-2 - 2-9-4 (6 of these) */
587 /* kdrwdbu TAD limits/offsets, MCMTR - 2-10-1, 2-11-1 (2 of these) */
589 /* CHA broadcast registers, dram rules - 1-29-0 (1 of these) */
591 /* SAD target - 1-29-1 (1 of these) */
595 /* Device with TOLM and TOHM, 0-5-0 (1 of these) */
624 * - 1 IMC
625 * - 2 DDR3 channels, 2 DPC per channel
627 * - 1 or 2 IMC
628 * - 4 DDR4 channels, 3 DPC per channel
630 * - 2 IMC
631 * - 4 DDR4 channels, 3 DPC per channel
633 * - 2 IMC
634 * - each IMC interfaces with a SMI 2 channel
635 * - each SMI channel interfaces with a scalable memory buffer
636 * - each scalable memory buffer supports 4 DDR3/DDR4 channels, 3 DPC
702 return -EINVAL; in numrank()
715 return -EINVAL; in numrow()
728 return -EINVAL; in numcol()
749 sbridge_dev = list_entry(prev ? prev->list.next in get_sbridge_dev()
753 if ((sbridge_dev->seg == seg) && (sbridge_dev->bus == bus) && in get_sbridge_dev()
754 (dom == SOCK || dom == sbridge_dev->dom)) in get_sbridge_dev()
770 sbridge_dev->pdev = kcalloc(table->n_devs_per_imc, in alloc_sbridge_dev()
771 sizeof(*sbridge_dev->pdev), in alloc_sbridge_dev()
773 if (!sbridge_dev->pdev) { in alloc_sbridge_dev()
778 sbridge_dev->seg = seg; in alloc_sbridge_dev()
779 sbridge_dev->bus = bus; in alloc_sbridge_dev()
780 sbridge_dev->dom = dom; in alloc_sbridge_dev()
781 sbridge_dev->n_devs = table->n_devs_per_imc; in alloc_sbridge_dev()
782 list_add_tail(&sbridge_dev->list, &sbridge_edac_list); in alloc_sbridge_dev()
789 list_del(&sbridge_dev->list); in free_sbridge_dev()
790 kfree(sbridge_dev->pdev); in free_sbridge_dev()
799 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); in sbridge_get_tolm()
807 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); in sbridge_get_tohm()
815 pci_read_config_dword(pvt->pci_br1, TOLM, ®); in ibridge_get_tolm()
824 pci_read_config_dword(pvt->pci_br1, TOHM, ®); in ibridge_get_tohm()
882 if (pvt->pci_ddrio) { in get_memory_type()
883 pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr, in get_memory_type()
902 if (!pvt->pci_ddrio) in haswell_get_memory_type()
905 pci_read_config_dword(pvt->pci_ddrio, in haswell_get_memory_type()
911 pci_read_config_dword(pvt->pci_ta, MCMTR, ®); in haswell_get_memory_type()
983 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); in get_node_id()
991 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in haswell_get_node_id()
999 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in knl_get_node_id()
1016 * home agent bank (7, 8), or one of the per-channel memory
1023 return bank - 7; in ibridge_get_ha()
1025 return (bank - 9) / 4; in ibridge_get_ha()
1041 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); in haswell_get_tolm()
1050 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); in haswell_get_tohm()
1052 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); in haswell_get_tohm()
1062 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, ®); in knl_get_tolm()
1071 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, ®_lo); in knl_get_tohm()
1072 pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, ®_hi); in knl_get_tohm()
1080 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; in haswell_rir_limit()
1140 * @ways: output number of interleave ways
1159 pci_mc = pvt->knl.pci_mc0; in knl_get_tad()
1162 pci_mc = pvt->knl.pci_mc1; in knl_get_tad()
1166 return -EINVAL; in knl_get_tad()
1178 return -ENODEV; in knl_get_tad()
1189 return -ENODEV; in knl_get_tad()
1214 * (This is the per-tile mapping of logical interleave targets to
1235 * (This is the per-tile mapping of logical interleave targets to
1263 * Render the EDC_ROUTE register in human-readable form.
1272 s[i*2+1] = '-'; in knl_show_edc_route()
1275 s[KNL_MAX_EDCS*2 - 1] = '\0'; in knl_show_edc_route()
1279 * Render the MC_ROUTE register in human-readable form.
1288 s[i*2+1] = '-'; in knl_show_mc_route()
1291 s[KNL_MAX_CHANNELS*2 - 1] = '\0'; in knl_show_mc_route()
1297 /* Is this dram rule backed by regular DRAM in flat mode? */
1316 * have to figure this out from the SAD rules, interleave lists, route tables,
1319 * SAD rules can have holes in them (e.g. the 3G-4G hole), so we have to
1335 * only work in flat mode, not in cache mode.
1367 pci_read_config_dword(pvt->knl.pci_cha[i], in knl_get_dimm_capacity()
1370 if (i > 0 && edc_route_reg[i] != edc_route_reg[i-1]) { in knl_get_dimm_capacity()
1371 knl_show_edc_route(edc_route_reg[i-1], in knl_get_dimm_capacity()
1373 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1377 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1378 cur_reg_start, i-1, edc_route_string); in knl_get_dimm_capacity()
1382 knl_show_edc_route(edc_route_reg[i-1], edc_route_string); in knl_get_dimm_capacity()
1383 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1387 edac_dbg(0, "edc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1388 cur_reg_start, i-1, edc_route_string); in knl_get_dimm_capacity()
1393 pci_read_config_dword(pvt->knl.pci_cha[i], in knl_get_dimm_capacity()
1396 if (i > 0 && mc_route_reg[i] != mc_route_reg[i-1]) { in knl_get_dimm_capacity()
1397 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); in knl_get_dimm_capacity()
1398 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1402 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1403 cur_reg_start, i-1, mc_route_string); in knl_get_dimm_capacity()
1407 knl_show_mc_route(mc_route_reg[i-1], mc_route_string); in knl_get_dimm_capacity()
1408 if (cur_reg_start == i-1) in knl_get_dimm_capacity()
1412 edac_dbg(0, "mc route table for CHA %d-%d: %s\n", in knl_get_dimm_capacity()
1413 cur_reg_start, i-1, mc_route_string); in knl_get_dimm_capacity()
1416 for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) { in knl_get_dimm_capacity()
1420 pci_read_config_dword(pvt->pci_sad0, in knl_get_dimm_capacity()
1421 pvt->info.dram_rule[sad_rule], &dram_rule); in knl_get_dimm_capacity()
1428 sad_limit = pvt->info.sad_limit(dram_rule)+1; in knl_get_dimm_capacity()
1430 pci_read_config_dword(pvt->pci_sad0, in knl_get_dimm_capacity()
1431 pvt->info.interleave_list[sad_rule], &interleave_reg); in knl_get_dimm_capacity()
1437 first_pkg = sad_pkg(pvt->info.interleave_pkg, in knl_get_dimm_capacity()
1440 pkg = sad_pkg(pvt->info.interleave_pkg, in knl_get_dimm_capacity()
1445 * 0 bit means memory is non-local, in knl_get_dimm_capacity()
1448 edac_dbg(0, "Unexpected interleave target %d\n", in knl_get_dimm_capacity()
1450 return -1; in knl_get_dimm_capacity()
1459 edac_dbg(3, "dram rule %d (base 0x%llx, limit 0x%llx), %d way interleave%s\n", in knl_get_dimm_capacity()
1492 tad_size = (tad_limit+1) - in knl_get_dimm_capacity()
1495 tad_base = (tad_limit+1) - tad_size; in knl_get_dimm_capacity()
1499 …edac_dbg(0, "TAD region overlaps lower SAD boundary -- TAD tables may be configured incorrectly.\n… in knl_get_dimm_capacity()
1502 …edac_dbg(0, "TAD region overlaps upper SAD boundary -- TAD tables may be configured incorrectly.\n… in knl_get_dimm_capacity()
1505 edac_dbg(3, "TAD region %d 0x%llx - 0x%llx (%lld bytes) table%d\n", in knl_get_dimm_capacity()
1524 /* Figure out which channels participate in interleave. */ in knl_get_dimm_capacity()
1565 struct sbridge_pvt *pvt = mci->pvt_info; in get_source_id()
1568 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL || in get_source_id()
1569 pvt->info.type == KNIGHTS_LANDING) in get_source_id()
1570 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); in get_source_id()
1572 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); in get_source_id()
1574 if (pvt->info.type == KNIGHTS_LANDING) in get_source_id()
1575 pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg); in get_source_id()
1577 pvt->sbridge_dev->source_id = SOURCE_ID(reg); in get_source_id()
1582 enum edac_type mode) in __populate_dimms() argument
1584 struct sbridge_pvt *pvt = mci->pvt_info; in __populate_dimms()
1585 int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS in __populate_dimms()
1592 mtype = pvt->info.get_memory_type(pvt); in __populate_dimms()
1610 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1612 if (!pvt->knl.pci_channel[i]) in __populate_dimms()
1616 if (!pvt->pci_tad[i]) in __populate_dimms()
1622 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1623 pci_read_config_dword(pvt->knl.pci_channel[i], in __populate_dimms()
1626 pci_read_config_dword(pvt->pci_tad[i], in __populate_dimms()
1631 if (!IS_ECC_ENABLED(pvt->info.mcmtr)) { in __populate_dimms()
1633 pvt->sbridge_dev->source_id, in __populate_dimms()
1634 pvt->sbridge_dev->dom, i); in __populate_dimms()
1635 return -ENODEV; in __populate_dimms()
1637 pvt->channel[i].dimms++; in __populate_dimms()
1639 ranks = numrank(pvt->info.type, mtr); in __populate_dimms()
1641 if (pvt->info.type == KNIGHTS_LANDING) { in __populate_dimms()
1651 size = ((u64)rows * cols * banks * ranks) >> (20 - 3); in __populate_dimms()
1655 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j, in __populate_dimms()
1659 dimm->nr_pages = npages; in __populate_dimms()
1660 dimm->grain = 32; in __populate_dimms()
1661 dimm->dtype = pvt->info.get_width(pvt, mtr); in __populate_dimms()
1662 dimm->mtype = mtype; in __populate_dimms()
1663 dimm->edac_mode = mode; in __populate_dimms()
1664 snprintf(dimm->label, sizeof(dimm->label), in __populate_dimms()
1666 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j); in __populate_dimms()
1676 struct sbridge_pvt *pvt = mci->pvt_info; in get_dimm_config()
1678 enum edac_type mode; in get_dimm_config() local
1681 pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt); in get_dimm_config()
1683 pvt->sbridge_dev->mc, in get_dimm_config()
1684 pvt->sbridge_dev->node_id, in get_dimm_config()
1685 pvt->sbridge_dev->source_id); in get_dimm_config()
1690 if (pvt->info.type == KNIGHTS_LANDING) { in get_dimm_config()
1691 mode = EDAC_S4ECD4ED; in get_dimm_config()
1692 pvt->mirror_mode = NON_MIRRORING; in get_dimm_config()
1693 pvt->is_cur_addr_mirrored = false; in get_dimm_config()
1696 return -1; in get_dimm_config()
1697 if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) { in get_dimm_config()
1699 return -ENODEV; in get_dimm_config()
1702 if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { in get_dimm_config()
1703 if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®)) { in get_dimm_config()
1705 return -ENODEV; in get_dimm_config()
1707 pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21); in get_dimm_config()
1709 pvt->mirror_mode = ADDR_RANGE_MIRRORING; in get_dimm_config()
1714 if (pci_read_config_dword(pvt->pci_ras, RASENABLES, ®)) { in get_dimm_config()
1716 return -ENODEV; in get_dimm_config()
1719 pvt->mirror_mode = FULL_MIRRORING; in get_dimm_config()
1722 pvt->mirror_mode = NON_MIRRORING; in get_dimm_config()
1727 if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) { in get_dimm_config()
1729 return -ENODEV; in get_dimm_config()
1731 if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) { in get_dimm_config()
1733 mode = EDAC_S8ECD8ED; in get_dimm_config()
1734 pvt->is_lockstep = true; in get_dimm_config()
1737 mode = EDAC_S4ECD4ED; in get_dimm_config()
1738 pvt->is_lockstep = false; in get_dimm_config()
1740 if (IS_CLOSE_PG(pvt->info.mcmtr)) { in get_dimm_config()
1741 edac_dbg(0, "address map is on closed page mode\n"); in get_dimm_config()
1742 pvt->is_close_pg = true; in get_dimm_config()
1744 edac_dbg(0, "address map is on open page mode\n"); in get_dimm_config()
1745 pvt->is_close_pg = false; in get_dimm_config()
1749 return __populate_dimms(mci, knl_mc_sizes, mode); in get_dimm_config()
1754 struct sbridge_pvt *pvt = mci->pvt_info; in get_memory_layout()
1766 pvt->tolm = pvt->info.get_tolm(pvt); in get_memory_layout()
1767 tmp_mb = (1 + pvt->tolm) >> 20; in get_memory_layout()
1771 gb, (mb*1000)/1024, (u64)pvt->tolm); in get_memory_layout()
1774 pvt->tohm = pvt->info.get_tohm(pvt); in get_memory_layout()
1775 tmp_mb = (1 + pvt->tohm) >> 20; in get_memory_layout()
1779 gb, (mb*1000)/1024, (u64)pvt->tohm); in get_memory_layout()
1782 * Step 2) Get SAD range and SAD Interleave list in get_memory_layout()
1783 * TAD registers contain the interleave wayness. However, it in get_memory_layout()
1788 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { in get_memory_layout()
1790 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], in get_memory_layout()
1792 limit = pvt->info.sad_limit(reg); in get_memory_layout()
1802 edac_dbg(0, "SAD#%d %s up to %u.%03u GB (0x%016Lx) Interleave: %s reg=0x%08x\n", in get_memory_layout()
1804 show_dram_attr(pvt->info.dram_attr(reg)), in get_memory_layout()
1807 get_intlv_mode_str(reg, pvt->info.type), in get_memory_layout()
1811 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], in get_memory_layout()
1813 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_layout()
1815 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); in get_memory_layout()
1819 edac_dbg(0, "SAD#%d, interleave #%d: %d\n", in get_memory_layout()
1824 if (pvt->info.type == KNIGHTS_LANDING) in get_memory_layout()
1832 pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], ®); in get_memory_layout()
1839 …edac_dbg(0, "TAD#%d: up to %u.%03u GB (0x%016Lx), socket interleave %d, memory interleave %d, TGT:… in get_memory_layout()
1856 if (!pvt->channel[i].dimms) in get_memory_layout()
1859 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1876 if (!pvt->channel[i].dimms) in get_memory_layout()
1879 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1886 tmp_mb = pvt->info.rir_limit(reg) >> 20; in get_memory_layout()
1897 pci_read_config_dword(pvt->pci_tad[i], in get_memory_layout()
1900 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; in get_memory_layout()
1907 (u32)RIR_RNK_TGT(pvt->info.type, reg), in get_memory_layout()
1919 if (sbridge_dev->node_id == node_id && sbridge_dev->dom == ha) in get_mci_for_node_id()
1920 return sbridge_dev->mci; in get_mci_for_node_id()
1933 struct sbridge_pvt *pvt = mci->pvt_info; in get_memory_error_data()
1954 if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) { in get_memory_error_data()
1956 return -EINVAL; in get_memory_error_data()
1958 if (addr >= (u64)pvt->tohm) { in get_memory_error_data()
1960 return -EINVAL; in get_memory_error_data()
1966 for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) { in get_memory_error_data()
1967 pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads], in get_memory_error_data()
1973 limit = pvt->info.sad_limit(reg); in get_memory_error_data()
1976 return -EINVAL; in get_memory_error_data()
1982 if (n_sads == pvt->info.max_sad) { in get_memory_error_data()
1984 return -EINVAL; in get_memory_error_data()
1987 *area_type = show_dram_attr(pvt->info.dram_attr(dram_rule)); in get_memory_error_data()
1988 interleave_mode = pvt->info.interleave_mode(dram_rule); in get_memory_error_data()
1990 pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads], in get_memory_error_data()
1993 if (pvt->info.type == SANDY_BRIDGE) { in get_memory_error_data()
1994 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_error_data()
1996 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); in get_memory_error_data()
2000 edac_dbg(0, "SAD interleave #%d: %d\n", in get_memory_error_data()
2003 edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n", in get_memory_error_data()
2004 pvt->sbridge_dev->mc, in get_memory_error_data()
2027 sprintf(msg, "Can't discover socket interleave"); in get_memory_error_data()
2028 return -EINVAL; in get_memory_error_data()
2031 edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n", in get_memory_error_data()
2033 } else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) { in get_memory_error_data()
2037 /* A7 mode swaps P9 with P6 */ in get_memory_error_data()
2044 /* interleave mode will XOR {8,7,6} with {18,17,16} */ in get_memory_error_data()
2050 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
2056 pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, ®); in get_memory_error_data()
2060 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %i, shiftup: %i\n", in get_memory_error_data()
2063 /* Ivy Bridge's SAD mode doesn't support XOR interleave mode */ in get_memory_error_data()
2065 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
2068 edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n", in get_memory_error_data()
2082 return -EINVAL; in get_memory_error_data()
2085 pvt = mci->pvt_info; in get_memory_error_data()
2091 pci_ha = pvt->pci_ha; in get_memory_error_data()
2097 return -EINVAL; in get_memory_error_data()
2105 return -EINVAL; in get_memory_error_data()
2115 if (pvt->is_chan_hash) in get_memory_error_data()
2138 return -EINVAL; in get_memory_error_data()
2142 pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset); in get_memory_error_data()
2144 if (pvt->mirror_mode == FULL_MIRRORING || in get_memory_error_data()
2145 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) { in get_memory_error_data()
2154 return -EINVAL; in get_memory_error_data()
2157 pvt->is_cur_addr_mirrored = true; in get_memory_error_data()
2160 pvt->is_cur_addr_mirrored = false; in get_memory_error_data()
2163 if (pvt->is_lockstep) in get_memory_error_data()
2168 …edac_dbg(0, "TAD#%d: address 0x%016Lx < 0x%016Lx, socket interleave %d, channel interleave %d (off… in get_memory_error_data()
2185 return -EINVAL; in get_memory_error_data()
2188 ch_addr = addr - offset; in get_memory_error_data()
2192 ch_addr |= addr & ((1 << (6 + shiftup)) - 1); in get_memory_error_data()
2198 pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], ®); in get_memory_error_data()
2203 limit = pvt->info.rir_limit(reg); in get_memory_error_data()
2216 return -EINVAL; in get_memory_error_data()
2220 if (pvt->is_close_pg) in get_memory_error_data()
2226 pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], ®); in get_memory_error_data()
2227 *rank = RIR_RNK_TGT(pvt->info.type, reg); in get_memory_error_data()
2229 edac_dbg(0, "RIR#%d: channel address 0x%08Lx < 0x%08Lx, RIR interleave %d, index %d\n", in get_memory_error_data()
2244 u32 reg, channel = GET_BITFIELD(m->status, 0, 3); in get_memory_error_data_from_mce()
2252 return -EINVAL; in get_memory_error_data_from_mce()
2255 pvt = mci->pvt_info; in get_memory_error_data_from_mce()
2256 if (!pvt->info.get_ha) { in get_memory_error_data_from_mce()
2258 return -EINVAL; in get_memory_error_data_from_mce()
2260 *ha = pvt->info.get_ha(m->bank); in get_memory_error_data_from_mce()
2262 sprintf(msg, "Impossible bank %d", m->bank); in get_memory_error_data_from_mce()
2263 return -EINVAL; in get_memory_error_data_from_mce()
2266 *socket = m->socketid; in get_memory_error_data_from_mce()
2270 return -EINVAL; in get_memory_error_data_from_mce()
2273 pvt = new_mci->pvt_info; in get_memory_error_data_from_mce()
2274 pci_ha = pvt->pci_ha; in get_memory_error_data_from_mce()
2276 tad0 = m->addr <= TAD_LIMIT(reg); in get_memory_error_data_from_mce()
2279 if (pvt->mirror_mode == FULL_MIRRORING || in get_memory_error_data_from_mce()
2280 (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) { in get_memory_error_data_from_mce()
2282 pvt->is_cur_addr_mirrored = true; in get_memory_error_data_from_mce()
2284 pvt->is_cur_addr_mirrored = false; in get_memory_error_data_from_mce()
2287 if (pvt->is_lockstep) in get_memory_error_data_from_mce()
2306 for (i = 0; i < sbridge_dev->n_devs; i++) { in sbridge_put_devices()
2307 struct pci_dev *pdev = sbridge_dev->pdev[i]; in sbridge_put_devices()
2311 pdev->bus->number, in sbridge_put_devices()
2312 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); in sbridge_put_devices()
2334 const struct pci_id_descr *dev_descr = &table->descr[devno]; in sbridge_get_onedevice()
2342 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2345 dev_descr->dev_id, *prev); in sbridge_get_onedevice()
2353 if (dev_descr->optional) in sbridge_get_onedevice()
2358 return -ENODEV; in sbridge_get_onedevice()
2362 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2365 return -ENODEV; in sbridge_get_onedevice()
2367 seg = pci_domain_nr(pdev->bus); in sbridge_get_onedevice()
2368 bus = pdev->bus->number; in sbridge_get_onedevice()
2371 sbridge_dev = get_sbridge_dev(seg, bus, dev_descr->dom, in sbridge_get_onedevice()
2375 if (dev_descr->dom == IMC1 && devno != 1) { in sbridge_get_onedevice()
2377 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2382 if (dev_descr->dom == SOCK) in sbridge_get_onedevice()
2385 sbridge_dev = alloc_sbridge_dev(seg, bus, dev_descr->dom, table); in sbridge_get_onedevice()
2388 return -ENOMEM; in sbridge_get_onedevice()
2393 if (sbridge_dev->pdev[sbridge_dev->i_devs]) { in sbridge_get_onedevice()
2396 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2398 return -ENODEV; in sbridge_get_onedevice()
2401 sbridge_dev->pdev[sbridge_dev->i_devs++] = pdev; in sbridge_get_onedevice()
2407 if (dev_descr->dom == SOCK && i < table->n_imcs_per_sock) in sbridge_get_onedevice()
2415 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2416 return -ENODEV; in sbridge_get_onedevice()
2420 PCI_VENDOR_ID_INTEL, dev_descr->dev_id); in sbridge_get_onedevice()
2435 * sbridge_get_all_devices - Find and perform 'get' operation on the MCH's
2451 if (table->type == KNIGHTS_LANDING) in sbridge_get_all_devices()
2453 while (table && table->descr) { in sbridge_get_all_devices()
2454 for (i = 0; i < table->n_devs_per_sock; i++) { in sbridge_get_all_devices()
2456 table->descr[i].dev_id != in sbridge_get_all_devices()
2457 table->descr[i-1].dev_id) { in sbridge_get_all_devices()
2465 i = table->n_devs_per_sock; in sbridge_get_all_devices()
2469 return -ENODEV; in sbridge_get_all_devices()
2484 #define TAD_DEV_TO_CHAN(dev) (((dev) & 0xf) - 0xa)
2489 struct sbridge_pvt *pvt = mci->pvt_info; in sbridge_mci_bind_devs()
2494 for (i = 0; i < sbridge_dev->n_devs; i++) { in sbridge_mci_bind_devs()
2495 pdev = sbridge_dev->pdev[i]; in sbridge_mci_bind_devs()
2499 switch (pdev->device) { in sbridge_mci_bind_devs()
2501 pvt->pci_sad0 = pdev; in sbridge_mci_bind_devs()
2504 pvt->pci_sad1 = pdev; in sbridge_mci_bind_devs()
2507 pvt->pci_br0 = pdev; in sbridge_mci_bind_devs()
2510 pvt->pci_ha = pdev; in sbridge_mci_bind_devs()
2513 pvt->pci_ta = pdev; in sbridge_mci_bind_devs()
2516 pvt->pci_ras = pdev; in sbridge_mci_bind_devs()
2523 int id = TAD_DEV_TO_CHAN(pdev->device); in sbridge_mci_bind_devs()
2524 pvt->pci_tad[id] = pdev; in sbridge_mci_bind_devs()
2529 pvt->pci_ddrio = pdev; in sbridge_mci_bind_devs()
2536 pdev->vendor, pdev->device, in sbridge_mci_bind_devs()
2537 sbridge_dev->bus, in sbridge_mci_bind_devs()
2542 if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha || in sbridge_mci_bind_devs()
2543 !pvt->pci_ras || !pvt->pci_ta) in sbridge_mci_bind_devs()
2552 return -ENODEV; in sbridge_mci_bind_devs()
2556 PCI_VENDOR_ID_INTEL, pdev->device); in sbridge_mci_bind_devs()
2557 return -EINVAL; in sbridge_mci_bind_devs()
2563 struct sbridge_pvt *pvt = mci->pvt_info; in ibridge_mci_bind_devs()
2568 for (i = 0; i < sbridge_dev->n_devs; i++) { in ibridge_mci_bind_devs()
2569 pdev = sbridge_dev->pdev[i]; in ibridge_mci_bind_devs()
2573 switch (pdev->device) { in ibridge_mci_bind_devs()
2576 pvt->pci_ha = pdev; in ibridge_mci_bind_devs()
2580 pvt->pci_ta = pdev; in ibridge_mci_bind_devs()
2584 pvt->pci_ras = pdev; in ibridge_mci_bind_devs()
2595 int id = TAD_DEV_TO_CHAN(pdev->device); in ibridge_mci_bind_devs()
2596 pvt->pci_tad[id] = pdev; in ibridge_mci_bind_devs()
2601 pvt->pci_ddrio = pdev; in ibridge_mci_bind_devs()
2604 pvt->pci_ddrio = pdev; in ibridge_mci_bind_devs()
2607 pvt->pci_sad0 = pdev; in ibridge_mci_bind_devs()
2610 pvt->pci_br0 = pdev; in ibridge_mci_bind_devs()
2613 pvt->pci_br1 = pdev; in ibridge_mci_bind_devs()
2620 sbridge_dev->bus, in ibridge_mci_bind_devs()
2621 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in ibridge_mci_bind_devs()
2626 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 || in ibridge_mci_bind_devs()
2627 !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta) in ibridge_mci_bind_devs()
2630 if (saw_chan_mask != 0x0f && /* -EN/-EX */ in ibridge_mci_bind_devs()
2631 saw_chan_mask != 0x03) /* -EP */ in ibridge_mci_bind_devs()
2637 return -ENODEV; in ibridge_mci_bind_devs()
2642 pdev->device); in ibridge_mci_bind_devs()
2643 return -EINVAL; in ibridge_mci_bind_devs()
2649 struct sbridge_pvt *pvt = mci->pvt_info; in haswell_mci_bind_devs()
2655 if (pvt->info.pci_vtd == NULL) in haswell_mci_bind_devs()
2657 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, in haswell_mci_bind_devs()
2661 for (i = 0; i < sbridge_dev->n_devs; i++) { in haswell_mci_bind_devs()
2662 pdev = sbridge_dev->pdev[i]; in haswell_mci_bind_devs()
2666 switch (pdev->device) { in haswell_mci_bind_devs()
2668 pvt->pci_sad0 = pdev; in haswell_mci_bind_devs()
2671 pvt->pci_sad1 = pdev; in haswell_mci_bind_devs()
2675 pvt->pci_ha = pdev; in haswell_mci_bind_devs()
2679 pvt->pci_ta = pdev; in haswell_mci_bind_devs()
2683 pvt->pci_ras = pdev; in haswell_mci_bind_devs()
2694 int id = TAD_DEV_TO_CHAN(pdev->device); in haswell_mci_bind_devs()
2695 pvt->pci_tad[id] = pdev; in haswell_mci_bind_devs()
2703 if (!pvt->pci_ddrio) in haswell_mci_bind_devs()
2704 pvt->pci_ddrio = pdev; in haswell_mci_bind_devs()
2711 sbridge_dev->bus, in haswell_mci_bind_devs()
2712 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in haswell_mci_bind_devs()
2717 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || in haswell_mci_bind_devs()
2718 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) in haswell_mci_bind_devs()
2721 if (saw_chan_mask != 0x0f && /* -EN/-EX */ in haswell_mci_bind_devs()
2722 saw_chan_mask != 0x03) /* -EP */ in haswell_mci_bind_devs()
2728 return -ENODEV; in haswell_mci_bind_devs()
2734 struct sbridge_pvt *pvt = mci->pvt_info; in broadwell_mci_bind_devs()
2740 if (pvt->info.pci_vtd == NULL) in broadwell_mci_bind_devs()
2742 pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL, in broadwell_mci_bind_devs()
2746 for (i = 0; i < sbridge_dev->n_devs; i++) { in broadwell_mci_bind_devs()
2747 pdev = sbridge_dev->pdev[i]; in broadwell_mci_bind_devs()
2751 switch (pdev->device) { in broadwell_mci_bind_devs()
2753 pvt->pci_sad0 = pdev; in broadwell_mci_bind_devs()
2756 pvt->pci_sad1 = pdev; in broadwell_mci_bind_devs()
2760 pvt->pci_ha = pdev; in broadwell_mci_bind_devs()
2764 pvt->pci_ta = pdev; in broadwell_mci_bind_devs()
2768 pvt->pci_ras = pdev; in broadwell_mci_bind_devs()
2779 int id = TAD_DEV_TO_CHAN(pdev->device); in broadwell_mci_bind_devs()
2780 pvt->pci_tad[id] = pdev; in broadwell_mci_bind_devs()
2785 pvt->pci_ddrio = pdev; in broadwell_mci_bind_devs()
2792 sbridge_dev->bus, in broadwell_mci_bind_devs()
2793 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), in broadwell_mci_bind_devs()
2798 if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 || in broadwell_mci_bind_devs()
2799 !pvt->pci_ras || !pvt->pci_ta || !pvt->info.pci_vtd) in broadwell_mci_bind_devs()
2802 if (saw_chan_mask != 0x0f && /* -EN/-EX */ in broadwell_mci_bind_devs()
2803 saw_chan_mask != 0x03) /* -EP */ in broadwell_mci_bind_devs()
2809 return -ENODEV; in broadwell_mci_bind_devs()
2815 struct sbridge_pvt *pvt = mci->pvt_info; in knl_mci_bind_devs()
2822 for (i = 0; i < sbridge_dev->n_devs; i++) { in knl_mci_bind_devs()
2823 pdev = sbridge_dev->pdev[i]; in knl_mci_bind_devs()
2828 dev = (pdev->devfn >> 3) & 0x1f; in knl_mci_bind_devs()
2829 func = pdev->devfn & 0x7; in knl_mci_bind_devs()
2831 switch (pdev->device) { in knl_mci_bind_devs()
2834 pvt->knl.pci_mc0 = pdev; in knl_mci_bind_devs()
2836 pvt->knl.pci_mc1 = pdev; in knl_mci_bind_devs()
2846 pvt->pci_sad0 = pdev; in knl_mci_bind_devs()
2850 pvt->pci_sad1 = pdev; in knl_mci_bind_devs()
2857 devidx = ((dev-14)*8)+func; in knl_mci_bind_devs()
2866 WARN_ON(pvt->knl.pci_cha[devidx] != NULL); in knl_mci_bind_devs()
2868 pvt->knl.pci_cha[devidx] = pdev; in knl_mci_bind_devs()
2872 devidx = -1; in knl_mci_bind_devs()
2875 * MC0 channels 0-2 are device 9 function 2-4, in knl_mci_bind_devs()
2876 * MC1 channels 3-5 are device 8 function 2-4. in knl_mci_bind_devs()
2880 devidx = func-2; in knl_mci_bind_devs()
2882 devidx = 3 + (func-2); in knl_mci_bind_devs()
2891 WARN_ON(pvt->knl.pci_channel[devidx] != NULL); in knl_mci_bind_devs()
2892 pvt->knl.pci_channel[devidx] = pdev; in knl_mci_bind_devs()
2896 pvt->knl.pci_mc_info = pdev; in knl_mci_bind_devs()
2900 pvt->pci_ta = pdev; in knl_mci_bind_devs()
2905 pdev->device); in knl_mci_bind_devs()
2910 if (!pvt->knl.pci_mc0 || !pvt->knl.pci_mc1 || in knl_mci_bind_devs()
2911 !pvt->pci_sad0 || !pvt->pci_sad1 || in knl_mci_bind_devs()
2912 !pvt->pci_ta) { in knl_mci_bind_devs()
2917 if (!pvt->knl.pci_channel[i]) { in knl_mci_bind_devs()
2924 if (!pvt->knl.pci_cha[i]) { in knl_mci_bind_devs()
2934 return -ENODEV; in knl_mci_bind_devs()
2951 struct sbridge_pvt *pvt = mci->pvt_info; in sbridge_mce_output_error()
2954 bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0); in sbridge_mce_output_error()
2955 bool overflow = GET_BITFIELD(m->status, 62, 62); in sbridge_mce_output_error()
2956 bool uncorrected_error = GET_BITFIELD(m->status, 61, 61); in sbridge_mce_output_error()
2958 u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52); in sbridge_mce_output_error()
2959 u32 mscod = GET_BITFIELD(m->status, 16, 31); in sbridge_mce_output_error()
2960 u32 errcode = GET_BITFIELD(m->status, 0, 15); in sbridge_mce_output_error()
2961 u32 channel = GET_BITFIELD(m->status, 0, 3); in sbridge_mce_output_error()
2962 u32 optypenum = GET_BITFIELD(m->status, 4, 6); in sbridge_mce_output_error()
2964 * Bits 5-0 of MCi_MISC give the least significant bit that is valid. in sbridge_mce_output_error()
2968 u32 lsb = GET_BITFIELD(m->misc, 0, 5); in sbridge_mce_output_error()
2974 if (pvt->info.type != SANDY_BRIDGE) in sbridge_mce_output_error()
2977 recoverable = GET_BITFIELD(m->status, 56, 56); in sbridge_mce_output_error()
2991 * According with Table 15-9 of the Intel Architecture spec vol 3A, in sbridge_mce_output_error()
3022 if (pvt->info.type == KNIGHTS_LANDING) { in sbridge_mce_output_error()
3029 m->bank); in sbridge_mce_output_error()
3034 * Reported channel is in range 0-2, so we can't map it in sbridge_mce_output_error()
3039 channel = knl_channel_remap(m->bank == 16, channel); in sbridge_mce_output_error()
3049 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, in sbridge_mce_output_error()
3050 channel, 0, -1, in sbridge_mce_output_error()
3055 rc = get_memory_error_data(mci, m->addr, &socket, &ha, in sbridge_mce_output_error()
3071 pvt = mci->pvt_info; in sbridge_mce_output_error()
3076 dimm = -1; in sbridge_mce_output_error()
3090 if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg) in sbridge_mce_output_error()
3108 channel = -1; in sbridge_mce_output_error()
3112 m->addr >> PAGE_SHIFT, m->addr & ~PAGE_MASK, 0, in sbridge_mce_output_error()
3113 channel, dimm, -1, in sbridge_mce_output_error()
3118 -1, -1, -1, in sbridge_mce_output_error()
3134 if (mce->kflags & MCE_HANDLED_CEC) in sbridge_mce_check_error()
3140 * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0. in sbridge_mce_check_error()
3143 if ((mce->status & 0xefff) >> 7 != 1) in sbridge_mce_check_error()
3147 if (!GET_BITFIELD(mce->status, 58, 58)) in sbridge_mce_check_error()
3151 if (!GET_BITFIELD(mce->status, 59, 59)) in sbridge_mce_check_error()
3155 if (GET_BITFIELD(mce->misc, 6, 8) != 2) in sbridge_mce_check_error()
3158 mci = get_mci_for_node_id(mce->socketid, IMC0); in sbridge_mce_check_error()
3162 if (mce->mcgstatus & MCG_STATUS_MCIP) in sbridge_mce_check_error()
3170 "Bank %d: %016Lx\n", mce->extcpu, type, in sbridge_mce_check_error()
3171 mce->mcgstatus, mce->bank, mce->status); in sbridge_mce_check_error()
3172 sbridge_mc_printk(mci, KERN_DEBUG, "TSC %llx ", mce->tsc); in sbridge_mce_check_error()
3173 sbridge_mc_printk(mci, KERN_DEBUG, "ADDR %llx ", mce->addr); in sbridge_mce_check_error()
3174 sbridge_mc_printk(mci, KERN_DEBUG, "MISC %llx ", mce->misc); in sbridge_mce_check_error()
3177 "%u APIC %x\n", mce->cpuvendor, mce->cpuid, in sbridge_mce_check_error()
3178 mce->time, mce->socketid, mce->apicid); in sbridge_mce_check_error()
3183 mce->kflags |= MCE_HANDLED_EDAC; in sbridge_mce_check_error()
3198 struct mem_ctl_info *mci = sbridge_dev->mci; in sbridge_unregister_mci()
3200 if (unlikely(!mci || !mci->pvt_info)) { in sbridge_unregister_mci()
3201 edac_dbg(0, "MC: dev = %p\n", &sbridge_dev->pdev[0]->dev); in sbridge_unregister_mci()
3208 mci, &sbridge_dev->pdev[0]->dev); in sbridge_unregister_mci()
3211 edac_mc_del_mc(mci->pdev); in sbridge_unregister_mci()
3213 edac_dbg(1, "%s: free mci struct\n", mci->ctl_name); in sbridge_unregister_mci()
3214 kfree(mci->ctl_name); in sbridge_unregister_mci()
3216 sbridge_dev->mci = NULL; in sbridge_unregister_mci()
3224 struct pci_dev *pdev = sbridge_dev->pdev[0]; in sbridge_register_mci()
3235 mci = edac_mc_alloc(sbridge_dev->mc, ARRAY_SIZE(layers), layers, in sbridge_register_mci()
3239 return -ENOMEM; in sbridge_register_mci()
3242 mci, &pdev->dev); in sbridge_register_mci()
3244 pvt = mci->pvt_info; in sbridge_register_mci()
3248 pvt->sbridge_dev = sbridge_dev; in sbridge_register_mci()
3249 sbridge_dev->mci = mci; in sbridge_register_mci()
3251 mci->mtype_cap = type == KNIGHTS_LANDING ? in sbridge_register_mci()
3253 mci->edac_ctl_cap = EDAC_FLAG_NONE; in sbridge_register_mci()
3254 mci->edac_cap = EDAC_FLAG_NONE; in sbridge_register_mci()
3255 mci->mod_name = EDAC_MOD_STR; in sbridge_register_mci()
3256 mci->dev_name = pci_name(pdev); in sbridge_register_mci()
3257 mci->ctl_page_to_phys = NULL; in sbridge_register_mci()
3259 pvt->info.type = type; in sbridge_register_mci()
3262 pvt->info.rankcfgr = IB_RANK_CFG_A; in sbridge_register_mci()
3263 pvt->info.get_tolm = ibridge_get_tolm; in sbridge_register_mci()
3264 pvt->info.get_tohm = ibridge_get_tohm; in sbridge_register_mci()
3265 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3266 pvt->info.get_memory_type = get_memory_type; in sbridge_register_mci()
3267 pvt->info.get_node_id = get_node_id; in sbridge_register_mci()
3268 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3269 pvt->info.rir_limit = rir_limit; in sbridge_register_mci()
3270 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3271 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3272 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3273 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3274 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3275 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3276 pvt->info.get_width = ibridge_get_width; in sbridge_register_mci()
3283 mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge SrcID#%d_Ha#%d", in sbridge_register_mci()
3284 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3287 pvt->info.rankcfgr = SB_RANK_CFG_A; in sbridge_register_mci()
3288 pvt->info.get_tolm = sbridge_get_tolm; in sbridge_register_mci()
3289 pvt->info.get_tohm = sbridge_get_tohm; in sbridge_register_mci()
3290 pvt->info.dram_rule = sbridge_dram_rule; in sbridge_register_mci()
3291 pvt->info.get_memory_type = get_memory_type; in sbridge_register_mci()
3292 pvt->info.get_node_id = get_node_id; in sbridge_register_mci()
3293 pvt->info.get_ha = sbridge_get_ha; in sbridge_register_mci()
3294 pvt->info.rir_limit = rir_limit; in sbridge_register_mci()
3295 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3296 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3297 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3298 pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule); in sbridge_register_mci()
3299 pvt->info.interleave_list = sbridge_interleave_list; in sbridge_register_mci()
3300 pvt->info.interleave_pkg = sbridge_interleave_pkg; in sbridge_register_mci()
3301 pvt->info.get_width = sbridge_get_width; in sbridge_register_mci()
3308 mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge SrcID#%d_Ha#%d", in sbridge_register_mci()
3309 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3313 pvt->info.get_tolm = haswell_get_tolm; in sbridge_register_mci()
3314 pvt->info.get_tohm = haswell_get_tohm; in sbridge_register_mci()
3315 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3316 pvt->info.get_memory_type = haswell_get_memory_type; in sbridge_register_mci()
3317 pvt->info.get_node_id = haswell_get_node_id; in sbridge_register_mci()
3318 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3319 pvt->info.rir_limit = haswell_rir_limit; in sbridge_register_mci()
3320 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3321 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3322 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3323 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3324 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3325 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3326 pvt->info.get_width = ibridge_get_width; in sbridge_register_mci()
3333 mci->ctl_name = kasprintf(GFP_KERNEL, "Haswell SrcID#%d_Ha#%d", in sbridge_register_mci()
3334 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3338 pvt->info.get_tolm = haswell_get_tolm; in sbridge_register_mci()
3339 pvt->info.get_tohm = haswell_get_tohm; in sbridge_register_mci()
3340 pvt->info.dram_rule = ibridge_dram_rule; in sbridge_register_mci()
3341 pvt->info.get_memory_type = haswell_get_memory_type; in sbridge_register_mci()
3342 pvt->info.get_node_id = haswell_get_node_id; in sbridge_register_mci()
3343 pvt->info.get_ha = ibridge_get_ha; in sbridge_register_mci()
3344 pvt->info.rir_limit = haswell_rir_limit; in sbridge_register_mci()
3345 pvt->info.sad_limit = sad_limit; in sbridge_register_mci()
3346 pvt->info.interleave_mode = interleave_mode; in sbridge_register_mci()
3347 pvt->info.dram_attr = dram_attr; in sbridge_register_mci()
3348 pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule); in sbridge_register_mci()
3349 pvt->info.interleave_list = ibridge_interleave_list; in sbridge_register_mci()
3350 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3351 pvt->info.get_width = broadwell_get_width; in sbridge_register_mci()
3358 mci->ctl_name = kasprintf(GFP_KERNEL, "Broadwell SrcID#%d_Ha#%d", in sbridge_register_mci()
3359 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3362 /* pvt->info.rankcfgr == ??? */ in sbridge_register_mci()
3363 pvt->info.get_tolm = knl_get_tolm; in sbridge_register_mci()
3364 pvt->info.get_tohm = knl_get_tohm; in sbridge_register_mci()
3365 pvt->info.dram_rule = knl_dram_rule; in sbridge_register_mci()
3366 pvt->info.get_memory_type = knl_get_memory_type; in sbridge_register_mci()
3367 pvt->info.get_node_id = knl_get_node_id; in sbridge_register_mci()
3368 pvt->info.get_ha = knl_get_ha; in sbridge_register_mci()
3369 pvt->info.rir_limit = NULL; in sbridge_register_mci()
3370 pvt->info.sad_limit = knl_sad_limit; in sbridge_register_mci()
3371 pvt->info.interleave_mode = knl_interleave_mode; in sbridge_register_mci()
3372 pvt->info.dram_attr = dram_attr_knl; in sbridge_register_mci()
3373 pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule); in sbridge_register_mci()
3374 pvt->info.interleave_list = knl_interleave_list; in sbridge_register_mci()
3375 pvt->info.interleave_pkg = ibridge_interleave_pkg; in sbridge_register_mci()
3376 pvt->info.get_width = knl_get_width; in sbridge_register_mci()
3382 mci->ctl_name = kasprintf(GFP_KERNEL, "Knights Landing SrcID#%d_Ha#%d", in sbridge_register_mci()
3383 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom); in sbridge_register_mci()
3387 if (!mci->ctl_name) { in sbridge_register_mci()
3388 rc = -ENOMEM; in sbridge_register_mci()
3401 mci->pdev = &pdev->dev; in sbridge_register_mci()
3406 rc = -EINVAL; in sbridge_register_mci()
3413 kfree(mci->ctl_name); in sbridge_register_mci()
3416 sbridge_dev->mci = NULL; in sbridge_register_mci()
3442 int rc = -ENODEV; in sbridge_probe()
3445 struct pci_id_table *ptable = (struct pci_id_table *)id->driver_data; in sbridge_probe()
3461 sbridge_dev->mc = mc++; in sbridge_probe()
3462 rc = sbridge_register_mci(sbridge_dev, ptable->type); in sbridge_probe()
3511 return -EBUSY; in sbridge_init()
3514 return -ENODEV; in sbridge_init()
3518 return -ENODEV; in sbridge_init()
3556 MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "