Lines Matching +full:bank +full:- +full:width
5 * Copyright (C) 2012 - 2014 Xilinx, Inc.
154 /* DDR Control Register width definitions */
275 * struct ecc_error_info - ECC error log information.
278 * @bank: Bank number.
281 * @bankgrpnr: Bank group number.
287 u32 bank; member
295 * struct synps_ecc_status - ECC status information to report.
309 * struct synps_edac_priv - DDR memory controller private instance data.
319 * @bank_shift: Bit shifts for bank bit.
320 * @bankgrp_shift: Bit shifts for bank group bit.
341 * struct synps_platform_data - synps platform data structure.
357 * zynq_get_error_info - Get the current ECC error info.
368 base = priv->baseaddr; in zynq_get_error_info()
369 p = &priv->stat; in zynq_get_error_info()
375 p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; in zynq_get_error_info()
376 p->ue_cnt = regval & STAT_UECNT_MASK; in zynq_get_error_info()
379 if (!(p->ce_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
382 p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; in zynq_get_error_info()
384 p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
385 p->ceinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
386 p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
387 p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); in zynq_get_error_info()
388 edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, in zynq_get_error_info()
389 p->ceinfo.data); in zynq_get_error_info()
394 if (!(p->ue_cnt && (regval & LOG_VALID))) in zynq_get_error_info()
398 p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; in zynq_get_error_info()
399 p->ueinfo.col = regval & ADDR_COL_MASK; in zynq_get_error_info()
400 p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; in zynq_get_error_info()
401 p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); in zynq_get_error_info()
412 * zynqmp_get_error_info - Get the current ECC error info.
423 base = priv->baseaddr; in zynqmp_get_error_info()
424 p = &priv->stat; in zynqmp_get_error_info()
427 p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; in zynqmp_get_error_info()
428 p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; in zynqmp_get_error_info()
429 if (!p->ce_cnt) in zynqmp_get_error_info()
436 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); in zynqmp_get_error_info()
439 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
441 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
443 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
445 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
446 p->ceinfo.data = readl(base + ECC_CSYND0_OFST); in zynqmp_get_error_info()
451 if (!p->ue_cnt) in zynqmp_get_error_info()
455 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); in zynqmp_get_error_info()
457 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> in zynqmp_get_error_info()
459 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> in zynqmp_get_error_info()
461 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); in zynqmp_get_error_info()
462 p->ueinfo.data = readl(base + ECC_UESYND0_OFST); in zynqmp_get_error_info()
473 * handle_error - Handle Correctable and Uncorrectable errors.
481 struct synps_edac_priv *priv = mci->pvt_info; in handle_error()
484 if (p->ce_cnt) { in handle_error()
485 pinf = &p->ceinfo; in handle_error()
486 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
487 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
488 …"DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0… in handle_error()
489 "CE", pinf->row, pinf->bank, in handle_error()
490 pinf->bankgrpnr, pinf->blknr, in handle_error()
491 pinf->bitpos, pinf->data); in handle_error()
493 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
494 "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x", in handle_error()
495 "CE", pinf->row, pinf->bank, pinf->col, in handle_error()
496 pinf->bitpos, pinf->data); in handle_error()
500 p->ce_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
501 priv->message, ""); in handle_error()
504 if (p->ue_cnt) { in handle_error()
505 pinf = &p->ueinfo; in handle_error()
506 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in handle_error()
507 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
508 "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d", in handle_error()
509 "UE", pinf->row, pinf->bank, in handle_error()
510 pinf->bankgrpnr, pinf->blknr); in handle_error()
512 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, in handle_error()
513 "DDR ECC error type :%s Row %d Bank %d Col %d ", in handle_error()
514 "UE", pinf->row, pinf->bank, pinf->col); in handle_error()
518 p->ue_cnt, 0, 0, 0, 0, 0, -1, in handle_error()
519 priv->message, ""); in handle_error()
526 * intr_handler - Interrupt Handler for ECC interrupts.
539 priv = mci->pvt_info; in intr_handler()
540 p_data = priv->p_data; in intr_handler()
542 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
547 status = p_data->get_error_info(priv); in intr_handler()
551 priv->ce_cnt += priv->stat.ce_cnt; in intr_handler()
552 priv->ue_cnt += priv->stat.ue_cnt; in intr_handler()
553 handle_error(mci, &priv->stat); in intr_handler()
556 priv->ce_cnt, priv->ue_cnt); in intr_handler()
557 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); in intr_handler()
562 * check_errors - Check controller for ECC errors.
573 priv = mci->pvt_info; in check_errors()
574 p_data = priv->p_data; in check_errors()
576 status = p_data->get_error_info(priv); in check_errors()
580 priv->ce_cnt += priv->stat.ce_cnt; in check_errors()
581 priv->ue_cnt += priv->stat.ue_cnt; in check_errors()
582 handle_error(mci, &priv->stat); in check_errors()
585 priv->ce_cnt, priv->ue_cnt); in check_errors()
589 * zynq_get_dtype - Return the controller memory width.
592 * Get the EDAC device type width appropriate for the current controller
595 * Return: a device type width enumeration.
600 u32 width; in zynq_get_dtype() local
602 width = readl(base + CTRL_OFST); in zynq_get_dtype()
603 width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT; in zynq_get_dtype()
605 switch (width) { in zynq_get_dtype()
620 * zynqmp_get_dtype - Return the controller memory width.
623 * Get the EDAC device type width appropriate for the current controller
626 * Return: a device type width enumeration.
631 u32 width; in zynqmp_get_dtype() local
633 width = readl(base + CTRL_OFST); in zynqmp_get_dtype()
634 width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; in zynqmp_get_dtype()
635 switch (width) { in zynqmp_get_dtype()
653 * zynq_get_ecc_state - Return the controller ECC enable/disable status.
677 * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
682 * Return: a ECC status boolean i.e true/false - enabled/disabled.
702 * get_memsize - Read the size of the attached memory device.
716 * zynq_get_mtype - Return the controller memory type.
740 * zynqmp_get_mtype - Returns controller memory type.
768 * init_csrows - Initialize the csrow data.
776 struct synps_edac_priv *priv = mci->pvt_info; in init_csrows()
783 p_data = priv->p_data; in init_csrows()
785 for (row = 0; row < mci->nr_csrows; row++) { in init_csrows()
786 csi = mci->csrows[row]; in init_csrows()
789 for (j = 0; j < csi->nr_channels; j++) { in init_csrows()
790 dimm = csi->channels[j]->dimm; in init_csrows()
791 dimm->edac_mode = EDAC_SECDED; in init_csrows()
792 dimm->mtype = p_data->get_mtype(priv->baseaddr); in init_csrows()
793 dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; in init_csrows()
794 dimm->grain = SYNPS_EDAC_ERR_GRAIN; in init_csrows()
795 dimm->dtype = p_data->get_dtype(priv->baseaddr); in init_csrows()
801 * mc_init - Initialize one driver instance.
806 * related driver-private data associated with the memory controller the
813 mci->pdev = &pdev->dev; in mc_init()
814 priv = mci->pvt_info; in mc_init()
818 mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; in mc_init()
819 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; in mc_init()
820 mci->scrub_cap = SCRUB_HW_SRC; in mc_init()
821 mci->scrub_mode = SCRUB_NONE; in mc_init()
823 mci->edac_cap = EDAC_FLAG_SECDED; in mc_init()
824 mci->ctl_name = "synps_ddr_controller"; in mc_init()
825 mci->dev_name = SYNPS_EDAC_MOD_STRING; in mc_init()
826 mci->mod_name = SYNPS_EDAC_MOD_VER; in mc_init()
828 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_init()
832 mci->edac_check = check_errors; in mc_init()
835 mci->ctl_page_to_phys = NULL; in mc_init()
844 priv->baseaddr + DDR_QOS_IRQ_EN_OFST); in enable_intr()
851 priv->baseaddr + DDR_QOS_IRQ_DB_OFST); in disable_intr()
857 struct synps_edac_priv *priv = mci->pvt_info; in setup_irq()
867 ret = devm_request_irq(&pdev->dev, irq, intr_handler, in setup_irq()
868 0, dev_name(&pdev->dev), mci); in setup_irq()
901 .compatible = "xlnx,zynq-ddrc-a05",
905 .compatible = "xlnx,zynqmp-ddrc-2.40a",
919 * ddr_poison_setup - Update poison registers.
927 int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval; in ddr_poison_setup() local
931 hif_addr = priv->poison_addr >> 3; in ddr_poison_setup()
934 if (priv->row_shift[index]) in ddr_poison_setup()
935 row |= (((hif_addr >> priv->row_shift[index]) & in ddr_poison_setup()
942 if (priv->col_shift[index] || index < 3) in ddr_poison_setup()
943 col |= (((hif_addr >> priv->col_shift[index]) & in ddr_poison_setup()
950 if (priv->bank_shift[index]) in ddr_poison_setup()
951 bank |= (((hif_addr >> priv->bank_shift[index]) & in ddr_poison_setup()
958 if (priv->bankgrp_shift[index]) in ddr_poison_setup()
959 bankgrp |= (((hif_addr >> priv->bankgrp_shift[index]) in ddr_poison_setup()
965 if (priv->rank_shift[0]) in ddr_poison_setup()
966 rank = (hif_addr >> priv->rank_shift[0]) & BIT(0); in ddr_poison_setup()
970 writel(regval, priv->baseaddr + ECC_POISON0_OFST); in ddr_poison_setup()
973 regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK; in ddr_poison_setup()
975 writel(regval, priv->baseaddr + ECC_POISON1_OFST); in ddr_poison_setup()
983 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_show()
987 readl(priv->baseaddr + ECC_POISON0_OFST), in inject_data_error_show()
988 readl(priv->baseaddr + ECC_POISON1_OFST), in inject_data_error_show()
989 priv->poison_addr); in inject_data_error_show()
997 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_error_store()
999 if (kstrtoul(data, 0, &priv->poison_addr)) in inject_data_error_store()
1000 return -EINVAL; in inject_data_error_store()
1012 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_show()
1015 (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3) in inject_data_poison_show()
1024 struct synps_edac_priv *priv = mci->pvt_info; in inject_data_poison_store()
1026 writel(0, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1028 writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1030 writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); in inject_data_poison_store()
1031 writel(1, priv->baseaddr + DDRC_SWCTL); in inject_data_poison_store()
1043 rc = device_create_file(&mci->dev, &dev_attr_inject_data_error); in edac_create_sysfs_attributes()
1046 rc = device_create_file(&mci->dev, &dev_attr_inject_data_poison); in edac_create_sysfs_attributes()
1054 device_remove_file(&mci->dev, &dev_attr_inject_data_error); in edac_remove_sysfs_attributes()
1055 device_remove_file(&mci->dev, &dev_attr_inject_data_poison); in edac_remove_sysfs_attributes()
1063 priv->row_shift[0] = (addrmap[5] & ROW_MAX_VAL_MASK) + ROW_B0_BASE; in setup_row_address_map()
1064 priv->row_shift[1] = ((addrmap[5] >> 8) & in setup_row_address_map()
1070 priv->row_shift[index] = addrmap_row_b2_10 + in setup_row_address_map()
1074 priv->row_shift[2] = (addrmap[9] & in setup_row_address_map()
1076 priv->row_shift[3] = ((addrmap[9] >> 8) & in setup_row_address_map()
1078 priv->row_shift[4] = ((addrmap[9] >> 16) & in setup_row_address_map()
1080 priv->row_shift[5] = ((addrmap[9] >> 24) & in setup_row_address_map()
1082 priv->row_shift[6] = (addrmap[10] & in setup_row_address_map()
1084 priv->row_shift[7] = ((addrmap[10] >> 8) & in setup_row_address_map()
1086 priv->row_shift[8] = ((addrmap[10] >> 16) & in setup_row_address_map()
1088 priv->row_shift[9] = ((addrmap[10] >> 24) & in setup_row_address_map()
1090 priv->row_shift[10] = (addrmap[11] & in setup_row_address_map()
1094 priv->row_shift[11] = (((addrmap[5] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1097 priv->row_shift[12] = ((addrmap[6] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1100 priv->row_shift[13] = (((addrmap[6] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1103 priv->row_shift[14] = (((addrmap[6] >> 16) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1106 priv->row_shift[15] = (((addrmap[6] >> 24) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1109 priv->row_shift[16] = ((addrmap[7] & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1112 priv->row_shift[17] = (((addrmap[7] >> 8) & ROW_MAX_VAL_MASK) == in setup_row_address_map()
1119 u32 width, memtype; in setup_column_address_map() local
1122 memtype = readl(priv->baseaddr + CTRL_OFST); in setup_column_address_map()
1123 width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; in setup_column_address_map()
1125 priv->col_shift[0] = 0; in setup_column_address_map()
1126 priv->col_shift[1] = 1; in setup_column_address_map()
1127 priv->col_shift[2] = (addrmap[2] & COL_MAX_VAL_MASK) + COL_B2_BASE; in setup_column_address_map()
1128 priv->col_shift[3] = ((addrmap[2] >> 8) & in setup_column_address_map()
1130 priv->col_shift[4] = (((addrmap[2] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1133 priv->col_shift[5] = (((addrmap[2] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1136 priv->col_shift[6] = ((addrmap[3] & COL_MAX_VAL_MASK) == in setup_column_address_map()
1139 priv->col_shift[7] = (((addrmap[3] >> 8) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1142 priv->col_shift[8] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1145 priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) == in setup_column_address_map()
1148 if (width == DDRCTL_EWDTH_64) { in setup_column_address_map()
1150 priv->col_shift[10] = ((addrmap[4] & in setup_column_address_map()
1154 priv->col_shift[11] = (((addrmap[4] >> 8) & in setup_column_address_map()
1159 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1163 priv->col_shift[13] = (((addrmap[4] >> 8) & in setup_column_address_map()
1168 } else if (width == DDRCTL_EWDTH_32) { in setup_column_address_map()
1170 priv->col_shift[10] = (((addrmap[3] >> 24) & in setup_column_address_map()
1174 priv->col_shift[11] = ((addrmap[4] & in setup_column_address_map()
1179 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1183 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1190 priv->col_shift[10] = (((addrmap[3] >> 16) & in setup_column_address_map()
1194 priv->col_shift[11] = (((addrmap[3] >> 24) & in setup_column_address_map()
1198 priv->col_shift[13] = ((addrmap[4] & in setup_column_address_map()
1203 priv->col_shift[11] = (((addrmap[3] >> 16) & in setup_column_address_map()
1207 priv->col_shift[13] = (((addrmap[3] >> 24) & in setup_column_address_map()
1214 if (width) { in setup_column_address_map()
1215 for (index = 9; index > width; index--) { in setup_column_address_map()
1216 priv->col_shift[index] = priv->col_shift[index - width]; in setup_column_address_map()
1217 priv->col_shift[index - width] = 0; in setup_column_address_map()
1225 priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE; in setup_bank_address_map()
1226 priv->bank_shift[1] = ((addrmap[1] >> 8) & in setup_bank_address_map()
1228 priv->bank_shift[2] = (((addrmap[1] >> 16) & in setup_bank_address_map()
1237 priv->bankgrp_shift[0] = (addrmap[8] & in setup_bg_address_map()
1239 priv->bankgrp_shift[1] = (((addrmap[8] >> 8) & BANKGRP_MAX_VAL_MASK) == in setup_bg_address_map()
1247 priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) == in setup_rank_address_map()
1253 * setup_address_map - Set Address Map by querying ADDRMAP registers.
1269 addrmap[index] = readl(priv->baseaddr + addrmap_offset); in setup_address_map()
1285 * mc_probe - Check controller and bind driver.
1304 baseaddr = devm_ioremap_resource(&pdev->dev, res); in mc_probe()
1308 p_data = of_device_get_match_data(&pdev->dev); in mc_probe()
1310 return -ENODEV; in mc_probe()
1312 if (!p_data->get_ecc_state(baseaddr)) { in mc_probe()
1314 return -ENXIO; in mc_probe()
1329 return -ENOMEM; in mc_probe()
1332 priv = mci->pvt_info; in mc_probe()
1333 priv->baseaddr = baseaddr; in mc_probe()
1334 priv->p_data = p_data; in mc_probe()
1338 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { in mc_probe()
1352 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) { in mc_probe()
1360 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_probe()
1368 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)) in mc_probe()
1380 * mc_remove - Unbind driver from controller.
1388 struct synps_edac_priv *priv = mci->pvt_info; in mc_remove()
1390 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) in mc_remove()
1394 if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) in mc_remove()
1398 edac_mc_del_mc(&pdev->dev); in mc_remove()
1406 .name = "synopsys-edac",