67 	void __iomem *reg_base;  member
83 static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,  in bcm_kona_gpio_write_lock_regs()  argument
86 	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);  in bcm_kona_gpio_write_lock_regs()
87 	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_write_lock_regs()
99 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_lock_gpio()
101 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_lock_gpio()
115 	val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));  in bcm_kona_gpio_unlock_gpio()
117 	bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);  in bcm_kona_gpio_unlock_gpio()
125 	void __iomem *reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get_dir()  local
128 	val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;  in bcm_kona_gpio_get_dir()
135 	void __iomem *reg_base;  in bcm_kona_gpio_set()  local
142 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set()
151 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_set()
153 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_set()
162 	void __iomem *reg_base;  in bcm_kona_gpio_get()  local
169 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_get()
178 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_get()
204 	void __iomem *reg_base;  in bcm_kona_gpio_direction_input()  local
209 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_input()
212 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
215 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_input()
226 	void __iomem *reg_base;  in bcm_kona_gpio_direction_output()  local
233 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_direction_output()
236 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
239 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_direction_output()
242 	val = readl(reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
244 	writel(val, reg_base + reg_offset);  in bcm_kona_gpio_direction_output()
265 	void __iomem *reg_base;  in bcm_kona_gpio_set_debounce()  local
270 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_set_debounce()
292 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
303 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_set_debounce()
340 	void __iomem *reg_base;  in bcm_kona_gpio_irq_ack()  local
348 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_ack()
351 	val = readl(reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
353 	writel(val, reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_ack()
361 	void __iomem *reg_base;  in bcm_kona_gpio_irq_mask()  local
369 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_mask()
372 	val = readl(reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
374 	writel(val, reg_base + GPIO_INT_MASK(bank_id));  in bcm_kona_gpio_irq_mask()
383 	void __iomem *reg_base;  in bcm_kona_gpio_irq_unmask()  local
391 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_unmask()
394 	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
396 	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));  in bcm_kona_gpio_irq_unmask()
405 	void __iomem *reg_base;  in bcm_kona_gpio_irq_set_type()  local
412 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_irq_set_type()
437 	val = readl(reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
440 	writel(val, reg_base + GPIO_CONTROL(gpio));  in bcm_kona_gpio_irq_set_type()
449 	void __iomem *reg_base;  in bcm_kona_gpio_irq_handler()  local
462 	reg_base = bank->kona_gpio->reg_base;  in bcm_kona_gpio_irq_handler()
465 	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &  in bcm_kona_gpio_irq_handler()
466 		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {  in bcm_kona_gpio_irq_handler()
476 			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |  in bcm_kona_gpio_irq_handler()
477 			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));  in bcm_kona_gpio_irq_handler()
551 	void __iomem *reg_base;  in bcm_kona_gpio_reset()  local
554 	reg_base = kona_gpio->reg_base;  in bcm_kona_gpio_reset()
558 		bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);  in bcm_kona_gpio_reset()
559 		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));  in bcm_kona_gpio_reset()
560 		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));  in bcm_kona_gpio_reset()
562 		bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);  in bcm_kona_gpio_reset()
623 	kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);  in bcm_kona_gpio_probe()
624 	if (IS_ERR(kona_gpio->reg_base)) {  in bcm_kona_gpio_probe()
625 		ret = PTR_ERR(kona_gpio->reg_base);  in bcm_kona_gpio_probe()