52 	struct ep93xx_gpio_irq_chip	*eic;  member
66 	return egc->eic;  in to_ep93xx_gpio_irq_chip()
81 					  struct ep93xx_gpio_irq_chip *eic)  in ep93xx_gpio_update_int_params()  argument
83 	writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);  in ep93xx_gpio_update_int_params()
85 	writeb_relaxed(eic->int_type2,  in ep93xx_gpio_update_int_params()
86 		       epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);  in ep93xx_gpio_update_int_params()
88 	writeb_relaxed(eic->int_type1,  in ep93xx_gpio_update_int_params()
89 		       epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);  in ep93xx_gpio_update_int_params()
91 	writeb_relaxed(eic->int_unmasked & eic->int_enabled,  in ep93xx_gpio_update_int_params()
92 		       epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);  in ep93xx_gpio_update_int_params()
99 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_int_debounce()  local
103 		eic->int_debounce |= port_mask;  in ep93xx_gpio_int_debounce()
105 		eic->int_debounce &= ~port_mask;  in ep93xx_gpio_int_debounce()
107 	writeb(eic->int_debounce,  in ep93xx_gpio_int_debounce()
108 	       epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);  in ep93xx_gpio_int_debounce()
160 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_ack()  local
165 		eic->int_type2 ^= port_mask; /* switch edge direction */  in ep93xx_gpio_irq_ack()
166 		ep93xx_gpio_update_int_params(epg, eic);  in ep93xx_gpio_irq_ack()
169 	writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);  in ep93xx_gpio_irq_ack()
175 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_mask_ack()  local
180 		eic->int_type2 ^= port_mask; /* switch edge direction */  in ep93xx_gpio_irq_mask_ack()
182 	eic->int_unmasked &= ~port_mask;  in ep93xx_gpio_irq_mask_ack()
183 	ep93xx_gpio_update_int_params(epg, eic);  in ep93xx_gpio_irq_mask_ack()
185 	writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);  in ep93xx_gpio_irq_mask_ack()
191 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_mask()  local
194 	eic->int_unmasked &= ~BIT(d->irq & 7);  in ep93xx_gpio_irq_mask()
195 	ep93xx_gpio_update_int_params(epg, eic);  in ep93xx_gpio_irq_mask()
201 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_unmask()  local
204 	eic->int_unmasked |= BIT(d->irq & 7);  in ep93xx_gpio_irq_unmask()
205 	ep93xx_gpio_update_int_params(epg, eic);  in ep93xx_gpio_irq_unmask()
216 	struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);  in ep93xx_gpio_irq_type()  local
226 		eic->int_type1 |= port_mask;  in ep93xx_gpio_irq_type()
227 		eic->int_type2 |= port_mask;  in ep93xx_gpio_irq_type()
231 		eic->int_type1 |= port_mask;  in ep93xx_gpio_irq_type()
232 		eic->int_type2 &= ~port_mask;  in ep93xx_gpio_irq_type()
236 		eic->int_type1 &= ~port_mask;  in ep93xx_gpio_irq_type()
237 		eic->int_type2 |= port_mask;  in ep93xx_gpio_irq_type()
241 		eic->int_type1 &= ~port_mask;  in ep93xx_gpio_irq_type()
242 		eic->int_type2 &= ~port_mask;  in ep93xx_gpio_irq_type()
246 		eic->int_type1 |= port_mask;  in ep93xx_gpio_irq_type()
249 			eic->int_type2 &= ~port_mask; /* falling */  in ep93xx_gpio_irq_type()
251 			eic->int_type2 |= port_mask; /* rising */  in ep93xx_gpio_irq_type()
260 	eic->int_enabled |= port_mask;  in ep93xx_gpio_irq_type()
262 	ep93xx_gpio_update_int_params(epg, eic);  in ep93xx_gpio_irq_type()
359 		egc->eic = devm_kcalloc(dev, 1,  in ep93xx_gpio_add_bank()
360 					sizeof(*egc->eic),  in ep93xx_gpio_add_bank()
362 		if (!egc->eic)  in ep93xx_gpio_add_bank()
364 		egc->eic->irq_offset = bank->irq;  in ep93xx_gpio_add_bank()
365 		ic = &egc->eic->ic;  in ep93xx_gpio_add_bank()