Lines Matching +full:edge +full:- +full:offset
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2008-2014,2016 Intel Corporation.
33 * structure, to get a bit offset for a pin (use GPDR as an example):
36 * reg = offset / 32;
37 * bit = offset % 32;
40 * so the bit of reg_addr is to control pin offset's GPDR feature
44 GPLR = 0, /* pin level read-only */
48 GRER, /* rising edge detect */
49 GFER, /* falling edge detect */
50 GEDR, /* edge detect result */
67 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset, in gpio_reg() argument
71 unsigned nreg = chip->ngpio / 32; in gpio_reg()
72 u8 reg = offset / 32; in gpio_reg()
74 return priv->reg_base + reg_type * nreg * 4 + reg * 4; in gpio_reg()
77 static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset, in gpio_reg_2bit() argument
81 unsigned nreg = chip->ngpio / 32; in gpio_reg_2bit()
82 u8 reg = offset / 16; in gpio_reg_2bit()
84 return priv->reg_base + reg_type * nreg * 4 + reg * 4; in gpio_reg_2bit()
87 static int intel_gpio_request(struct gpio_chip *chip, unsigned offset) in intel_gpio_request() argument
89 void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR); in intel_gpio_request()
91 int shift = (offset % 16) << 1, af = (value >> shift) & 3; in intel_gpio_request()
100 static int intel_gpio_get(struct gpio_chip *chip, unsigned offset) in intel_gpio_get() argument
102 void __iomem *gplr = gpio_reg(chip, offset, GPLR); in intel_gpio_get()
104 return !!(readl(gplr) & BIT(offset % 32)); in intel_gpio_get()
107 static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value) in intel_gpio_set() argument
112 gpsr = gpio_reg(chip, offset, GPSR); in intel_gpio_set()
113 writel(BIT(offset % 32), gpsr); in intel_gpio_set()
115 gpcr = gpio_reg(chip, offset, GPCR); in intel_gpio_set()
116 writel(BIT(offset % 32), gpcr); in intel_gpio_set()
120 static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset) in intel_gpio_direction_input() argument
123 void __iomem *gpdr = gpio_reg(chip, offset, GPDR); in intel_gpio_direction_input()
127 if (priv->pdev) in intel_gpio_direction_input()
128 pm_runtime_get(&priv->pdev->dev); in intel_gpio_direction_input()
130 spin_lock_irqsave(&priv->lock, flags); in intel_gpio_direction_input()
132 value &= ~BIT(offset % 32); in intel_gpio_direction_input()
134 spin_unlock_irqrestore(&priv->lock, flags); in intel_gpio_direction_input()
136 if (priv->pdev) in intel_gpio_direction_input()
137 pm_runtime_put(&priv->pdev->dev); in intel_gpio_direction_input()
143 unsigned offset, int value) in intel_gpio_direction_output() argument
146 void __iomem *gpdr = gpio_reg(chip, offset, GPDR); in intel_gpio_direction_output()
149 intel_gpio_set(chip, offset, value); in intel_gpio_direction_output()
151 if (priv->pdev) in intel_gpio_direction_output()
152 pm_runtime_get(&priv->pdev->dev); in intel_gpio_direction_output()
154 spin_lock_irqsave(&priv->lock, flags); in intel_gpio_direction_output()
156 value |= BIT(offset % 32); in intel_gpio_direction_output()
158 spin_unlock_irqrestore(&priv->lock, flags); in intel_gpio_direction_output()
160 if (priv->pdev) in intel_gpio_direction_output()
161 pm_runtime_put(&priv->pdev->dev); in intel_gpio_direction_output()
173 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); in intel_mid_irq_type()
174 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); in intel_mid_irq_type()
176 if (gpio >= priv->chip.ngpio) in intel_mid_irq_type()
177 return -EINVAL; in intel_mid_irq_type()
179 if (priv->pdev) in intel_mid_irq_type()
180 pm_runtime_get(&priv->pdev->dev); in intel_mid_irq_type()
182 spin_lock_irqsave(&priv->lock, flags); in intel_mid_irq_type()
194 spin_unlock_irqrestore(&priv->lock, flags); in intel_mid_irq_type()
196 if (priv->pdev) in intel_mid_irq_type()
197 pm_runtime_put(&priv->pdev->dev); in intel_mid_irq_type()
211 .name = "INTEL_MID-GPIO",
281 for (base = 0; base < priv->chip.ngpio; base += 32) { in intel_mid_irq_handler()
282 gedr = gpio_reg(&priv->chip, base, GEDR); in intel_mid_irq_handler()
286 /* Clear before handling so we can't lose an edge */ in intel_mid_irq_handler()
288 generic_handle_irq(irq_find_mapping(gc->irq.domain, in intel_mid_irq_handler()
293 chip->irq_eoi(data); in intel_mid_irq_handler()
302 for (base = 0; base < priv->chip.ngpio; base += 32) { in intel_mid_irq_init_hw()
303 /* Clear the rising-edge detect register */ in intel_mid_irq_init_hw()
304 reg = gpio_reg(&priv->chip, base, GRER); in intel_mid_irq_init_hw()
306 /* Clear the falling-edge detect register */ in intel_mid_irq_init_hw()
307 reg = gpio_reg(&priv->chip, base, GFER); in intel_mid_irq_init_hw()
309 /* Clear the edge detect status register */ in intel_mid_irq_init_hw()
310 reg = gpio_reg(&priv->chip, base, GEDR); in intel_mid_irq_init_hw()
320 return err ?: -EBUSY; in intel_gpio_runtime_idle()
337 (struct intel_mid_gpio_ddata *)id->driver_data; in intel_gpio_probe()
345 dev_err(&pdev->dev, "I/O memory mapping error\n"); in intel_gpio_probe()
357 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in intel_gpio_probe()
359 return -ENOMEM; in intel_gpio_probe()
361 priv->reg_base = pcim_iomap_table(pdev)[0]; in intel_gpio_probe()
362 priv->chip.label = dev_name(&pdev->dev); in intel_gpio_probe()
363 priv->chip.parent = &pdev->dev; in intel_gpio_probe()
364 priv->chip.request = intel_gpio_request; in intel_gpio_probe()
365 priv->chip.direction_input = intel_gpio_direction_input; in intel_gpio_probe()
366 priv->chip.direction_output = intel_gpio_direction_output; in intel_gpio_probe()
367 priv->chip.get = intel_gpio_get; in intel_gpio_probe()
368 priv->chip.set = intel_gpio_set; in intel_gpio_probe()
369 priv->chip.base = gpio_base; in intel_gpio_probe()
370 priv->chip.ngpio = ddata->ngpio; in intel_gpio_probe()
371 priv->chip.can_sleep = false; in intel_gpio_probe()
372 priv->pdev = pdev; in intel_gpio_probe()
374 spin_lock_init(&priv->lock); in intel_gpio_probe()
376 girq = &priv->chip.irq; in intel_gpio_probe()
377 girq->chip = &intel_mid_irqchip; in intel_gpio_probe()
378 girq->init_hw = intel_mid_irq_init_hw; in intel_gpio_probe()
379 girq->parent_handler = intel_mid_irq_handler; in intel_gpio_probe()
380 girq->num_parents = 1; in intel_gpio_probe()
381 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, in intel_gpio_probe()
382 sizeof(*girq->parents), in intel_gpio_probe()
384 if (!girq->parents) in intel_gpio_probe()
385 return -ENOMEM; in intel_gpio_probe()
386 girq->parents[0] = pdev->irq; in intel_gpio_probe()
387 girq->first = irq_base; in intel_gpio_probe()
388 girq->default_type = IRQ_TYPE_NONE; in intel_gpio_probe()
389 girq->handler = handle_simple_irq; in intel_gpio_probe()
393 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); in intel_gpio_probe()
395 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); in intel_gpio_probe()
399 pm_runtime_put_noidle(&pdev->dev); in intel_gpio_probe()
400 pm_runtime_allow(&pdev->dev); in intel_gpio_probe()