Lines Matching +full:gpio +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support functions for OMAP GPIO
5 * Copyright (C) 2003-2005 Nokia Corporation
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
25 #include <linux/gpio/driver.h>
27 #include <linux/platform_data/gpio-omap.h>
36 u32 ctrl; member
77 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
83 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
108 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, in omap_set_gpio_direction() argument
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, in omap_set_gpio_direction()
112 BIT(gpio), is_input); in omap_set_gpio_direction()
120 void __iomem *reg = bank->base; in omap_set_gpio_dataout_reg()
124 reg += bank->regs->set_dataout; in omap_set_gpio_dataout_reg()
125 bank->context.dataout |= l; in omap_set_gpio_dataout_reg()
127 reg += bank->regs->clr_dataout; in omap_set_gpio_dataout_reg()
128 bank->context.dataout &= ~l; in omap_set_gpio_dataout_reg()
138 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, in omap_set_gpio_dataout_mask()
144 if (bank->dbck_enable_mask && !bank->dbck_enabled) { in omap_gpio_dbck_enable()
145 clk_enable(bank->dbck); in omap_gpio_dbck_enable()
146 bank->dbck_enabled = true; in omap_gpio_dbck_enable()
148 writel_relaxed(bank->dbck_enable_mask, in omap_gpio_dbck_enable()
149 bank->base + bank->regs->debounce_en); in omap_gpio_dbck_enable()
155 if (bank->dbck_enable_mask && bank->dbck_enabled) { in omap_gpio_dbck_disable()
158 * enabled but the clock is not, GPIO module seems to be unable in omap_gpio_dbck_disable()
161 writel_relaxed(0, bank->base + bank->regs->debounce_en); in omap_gpio_dbck_disable()
163 clk_disable(bank->dbck); in omap_gpio_dbck_disable()
164 bank->dbck_enabled = false; in omap_gpio_dbck_disable()
169 * omap2_set_gpio_debounce - low level gpio debounce time
170 * @bank: the gpio bank we're acting upon
171 * @offset: the gpio number on this @bank
187 if (!bank->dbck_flag) in omap2_set_gpio_debounce()
188 return -ENOTSUPP; in omap2_set_gpio_debounce()
191 debounce = DIV_ROUND_UP(debounce, 31) - 1; in omap2_set_gpio_debounce()
193 return -EINVAL; in omap2_set_gpio_debounce()
198 clk_enable(bank->dbck); in omap2_set_gpio_debounce()
199 writel_relaxed(debounce, bank->base + bank->regs->debounce); in omap2_set_gpio_debounce()
201 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); in omap2_set_gpio_debounce()
202 bank->dbck_enable_mask = val; in omap2_set_gpio_debounce()
204 clk_disable(bank->dbck); in omap2_set_gpio_debounce()
214 if (bank->dbck_enable_mask) { in omap2_set_gpio_debounce()
215 bank->context.debounce = debounce; in omap2_set_gpio_debounce()
216 bank->context.debounce_en = val; in omap2_set_gpio_debounce()
223 * omap_clear_gpio_debounce - clear debounce settings for a gpio
224 * @bank: the gpio bank we're acting upon
225 * @offset: the gpio number on this @bank
227 * If a gpio is using debounce, then clear the debounce enable bit and if
228 * this is the only gpio in this bank using debounce, then clear the debounce
230 * if this is the only gpio in the bank using debounce.
236 if (!bank->dbck_flag) in omap_clear_gpio_debounce()
239 if (!(bank->dbck_enable_mask & gpio_bit)) in omap_clear_gpio_debounce()
242 bank->dbck_enable_mask &= ~gpio_bit; in omap_clear_gpio_debounce()
243 bank->context.debounce_en &= ~gpio_bit; in omap_clear_gpio_debounce()
244 writel_relaxed(bank->context.debounce_en, in omap_clear_gpio_debounce()
245 bank->base + bank->regs->debounce_en); in omap_clear_gpio_debounce()
247 if (!bank->dbck_enable_mask) { in omap_clear_gpio_debounce()
248 bank->context.debounce = 0; in omap_clear_gpio_debounce()
249 writel_relaxed(bank->context.debounce, bank->base + in omap_clear_gpio_debounce()
250 bank->regs->debounce); in omap_clear_gpio_debounce()
251 clk_disable(bank->dbck); in omap_clear_gpio_debounce()
252 bank->dbck_enabled = false; in omap_clear_gpio_debounce()
257 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
258 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
259 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
264 u32 no_wake = bank->non_wakeup_gpios; in omap_gpio_is_off_wakeup_capable()
272 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, in omap_set_gpio_trigger() argument
275 void __iomem *base = bank->base; in omap_set_gpio_trigger()
276 u32 gpio_bit = BIT(gpio); in omap_set_gpio_trigger()
278 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit, in omap_set_gpio_trigger()
280 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit, in omap_set_gpio_trigger()
284 * We need the edge detection enabled for to allow the GPIO block in omap_set_gpio_trigger()
288 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit, in omap_set_gpio_trigger()
290 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit, in omap_set_gpio_trigger()
293 bank->context.leveldetect0 = in omap_set_gpio_trigger()
294 readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_set_gpio_trigger()
295 bank->context.leveldetect1 = in omap_set_gpio_trigger()
296 readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_set_gpio_trigger()
297 bank->context.risingdetect = in omap_set_gpio_trigger()
298 readl_relaxed(bank->base + bank->regs->risingdetect); in omap_set_gpio_trigger()
299 bank->context.fallingdetect = in omap_set_gpio_trigger()
300 readl_relaxed(bank->base + bank->regs->fallingdetect); in omap_set_gpio_trigger()
302 bank->level_mask = bank->context.leveldetect0 | in omap_set_gpio_trigger()
303 bank->context.leveldetect1; in omap_set_gpio_trigger()
306 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { in omap_set_gpio_trigger()
308 * Log the edge gpio and manually trigger the IRQ in omap_set_gpio_trigger()
311 * Applies for omap2 non-wakeup gpio and all omap3 gpios in omap_set_gpio_trigger()
314 bank->enabled_non_wakeup_gpios |= gpio_bit; in omap_set_gpio_trigger()
316 bank->enabled_non_wakeup_gpios &= ~gpio_bit; in omap_set_gpio_trigger()
324 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) in omap_toggle_gpio_edge_triggering() argument
326 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) { in omap_toggle_gpio_edge_triggering()
327 void __iomem *reg = bank->base + bank->regs->irqctrl; in omap_toggle_gpio_edge_triggering()
329 writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg); in omap_toggle_gpio_edge_triggering()
333 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, in omap_set_gpio_triggering() argument
336 void __iomem *reg = bank->base; in omap_set_gpio_triggering()
339 if (bank->regs->leveldetect0 && bank->regs->wkup_en) { in omap_set_gpio_triggering()
340 omap_set_gpio_trigger(bank, gpio, trigger); in omap_set_gpio_triggering()
341 } else if (bank->regs->irqctrl) { in omap_set_gpio_triggering()
342 reg += bank->regs->irqctrl; in omap_set_gpio_triggering()
346 bank->toggle_mask |= BIT(gpio); in omap_set_gpio_triggering()
348 l |= BIT(gpio); in omap_set_gpio_triggering()
350 l &= ~(BIT(gpio)); in omap_set_gpio_triggering()
352 return -EINVAL; in omap_set_gpio_triggering()
355 } else if (bank->regs->edgectrl1) { in omap_set_gpio_triggering()
356 if (gpio & 0x08) in omap_set_gpio_triggering()
357 reg += bank->regs->edgectrl2; in omap_set_gpio_triggering()
359 reg += bank->regs->edgectrl1; in omap_set_gpio_triggering()
361 gpio &= 0x07; in omap_set_gpio_triggering()
363 l &= ~(3 << (gpio << 1)); in omap_set_gpio_triggering()
365 l |= 2 << (gpio << 1); in omap_set_gpio_triggering()
367 l |= BIT(gpio << 1); in omap_set_gpio_triggering()
375 if (bank->regs->pinctrl) { in omap_enable_gpio_module()
376 void __iomem *reg = bank->base + bank->regs->pinctrl; in omap_enable_gpio_module()
382 if (bank->regs->ctrl && !BANK_USED(bank)) { in omap_enable_gpio_module()
383 void __iomem *reg = bank->base + bank->regs->ctrl; in omap_enable_gpio_module()
384 u32 ctrl; in omap_enable_gpio_module() local
386 ctrl = readl_relaxed(reg); in omap_enable_gpio_module()
388 ctrl &= ~GPIO_MOD_CTRL_BIT; in omap_enable_gpio_module()
389 writel_relaxed(ctrl, reg); in omap_enable_gpio_module()
390 bank->context.ctrl = ctrl; in omap_enable_gpio_module()
396 if (bank->regs->ctrl && !BANK_USED(bank)) { in omap_disable_gpio_module()
397 void __iomem *reg = bank->base + bank->regs->ctrl; in omap_disable_gpio_module()
398 u32 ctrl; in omap_disable_gpio_module() local
400 ctrl = readl_relaxed(reg); in omap_disable_gpio_module()
402 ctrl |= GPIO_MOD_CTRL_BIT; in omap_disable_gpio_module()
403 writel_relaxed(ctrl, reg); in omap_disable_gpio_module()
404 bank->context.ctrl = ctrl; in omap_disable_gpio_module()
410 void __iomem *reg = bank->base + bank->regs->direction; in omap_gpio_is_input()
417 if (!LINE_USED(bank->mod_usage, offset)) { in omap_gpio_init_irq()
421 bank->irq_usage |= BIT(offset); in omap_gpio_init_irq()
429 unsigned offset = d->hwirq; in omap_gpio_irq_type()
432 return -EINVAL; in omap_gpio_irq_type()
434 if (!bank->regs->leveldetect0 && in omap_gpio_irq_type()
436 return -EINVAL; in omap_gpio_irq_type()
438 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_type()
441 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
446 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
447 retval = -EINVAL; in omap_gpio_irq_type()
450 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_type()
471 void __iomem *reg = bank->base; in omap_clear_gpio_irqbank()
473 reg += bank->regs->irqstatus; in omap_clear_gpio_irqbank()
476 /* Workaround for clearing DSP GPIO interrupts to allow retention */ in omap_clear_gpio_irqbank()
477 if (bank->regs->irqstatus2) { in omap_clear_gpio_irqbank()
478 reg = bank->base + bank->regs->irqstatus2; in omap_clear_gpio_irqbank()
494 void __iomem *reg = bank->base; in omap_get_gpio_irqbank_mask()
496 u32 mask = (BIT(bank->width)) - 1; in omap_get_gpio_irqbank_mask()
498 reg += bank->regs->irqenable; in omap_get_gpio_irqbank_mask()
500 if (bank->regs->irqenable_inv) in omap_get_gpio_irqbank_mask()
509 void __iomem *reg = bank->base; in omap_set_gpio_irqenable()
512 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) { in omap_set_gpio_irqenable()
514 reg += bank->regs->set_irqenable; in omap_set_gpio_irqenable()
515 bank->context.irqenable1 |= gpio_mask; in omap_set_gpio_irqenable()
517 reg += bank->regs->clr_irqenable; in omap_set_gpio_irqenable()
518 bank->context.irqenable1 &= ~gpio_mask; in omap_set_gpio_irqenable()
522 bank->context.irqenable1 = in omap_set_gpio_irqenable()
523 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask, in omap_set_gpio_irqenable()
524 enable ^ bank->regs->irqenable_inv); in omap_set_gpio_irqenable()
528 * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM in omap_set_gpio_irqenable()
533 if (bank->regs->wkup_en && in omap_set_gpio_irqenable()
534 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) { in omap_set_gpio_irqenable()
535 bank->context.wake_en = in omap_set_gpio_irqenable()
536 omap_gpio_rmw(bank->base + bank->regs->wkup_en, in omap_set_gpio_irqenable()
546 return irq_set_irq_wake(bank->irq, enable); in omap_gpio_wake_enable()
550 * We need to unmask the GPIO bank interrupt as soon as possible to
551 * avoid missing GPIO interrupts for other lines in the bank.
552 * Then we need to mask-read-clear-unmask the triggered GPIO lines
553 * in the bank to avoid missing nested interrupts for a GPIO line.
554 * If we wait to unmask individual GPIO lines in the bank after the
567 isr_reg = bank->base + bank->regs->irqstatus; in omap_gpio_irq_handler()
571 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), in omap_gpio_irq_handler()
572 "gpio irq%i while runtime suspended?\n", irq)) in omap_gpio_irq_handler()
576 raw_spin_lock_irqsave(&bank->lock, lock_flags); in omap_gpio_irq_handler()
586 edge = isr & ~bank->level_mask; in omap_gpio_irq_handler()
590 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); in omap_gpio_irq_handler()
599 raw_spin_lock_irqsave(&bank->lock, lock_flags); in omap_gpio_irq_handler()
607 if (bank->toggle_mask & (BIT(bit))) in omap_gpio_irq_handler()
610 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); in omap_gpio_irq_handler()
612 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); in omap_gpio_irq_handler()
614 generic_handle_irq(irq_find_mapping(bank->chip.irq.domain, in omap_gpio_irq_handler()
617 raw_spin_unlock_irqrestore(&bank->wa_lock, in omap_gpio_irq_handler()
629 unsigned offset = d->hwirq; in omap_gpio_irq_startup()
631 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_startup()
633 if (!LINE_USED(bank->mod_usage, offset)) in omap_gpio_irq_startup()
636 bank->irq_usage |= BIT(offset); in omap_gpio_irq_startup()
638 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_startup()
648 unsigned offset = d->hwirq; in omap_gpio_irq_shutdown()
650 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_irq_shutdown()
651 bank->irq_usage &= ~(BIT(offset)); in omap_gpio_irq_shutdown()
655 if (!LINE_USED(bank->mod_usage, offset)) in omap_gpio_irq_shutdown()
658 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_irq_shutdown()
665 pm_runtime_get_sync(bank->chip.parent); in omap_gpio_irq_bus_lock()
672 pm_runtime_put(bank->chip.parent); in gpio_irq_bus_sync_unlock()
678 unsigned offset = d->hwirq; in omap_gpio_mask_irq()
681 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_mask_irq()
684 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_mask_irq()
690 unsigned offset = d->hwirq; in omap_gpio_unmask_irq()
694 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_unmask_irq()
698 * For level-triggered GPIOs, clearing must be done after the source in omap_gpio_unmask_irq()
702 if (bank->regs->leveldetect0 && bank->regs->wkup_en && in omap_gpio_unmask_irq()
709 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_unmask_irq()
712 /*---------------------------------------------------------------------*/
717 void __iomem *mask_reg = bank->base + in omap_mpuio_suspend_noirq()
718 OMAP_MPUIO_GPIO_MASKIT / bank->stride; in omap_mpuio_suspend_noirq()
721 raw_spin_lock_irqsave(&bank->lock, flags); in omap_mpuio_suspend_noirq()
722 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); in omap_mpuio_suspend_noirq()
723 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_mpuio_suspend_noirq()
731 void __iomem *mask_reg = bank->base + in omap_mpuio_resume_noirq()
732 OMAP_MPUIO_GPIO_MASKIT / bank->stride; in omap_mpuio_resume_noirq()
735 raw_spin_lock_irqsave(&bank->lock, flags); in omap_mpuio_resume_noirq()
736 writel_relaxed(bank->context.wake_en, mask_reg); in omap_mpuio_resume_noirq()
737 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_mpuio_resume_noirq()
757 .id = -1,
772 /*---------------------------------------------------------------------*/
779 pm_runtime_get_sync(chip->parent); in omap_gpio_request()
781 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_request()
783 bank->mod_usage |= BIT(offset); in omap_gpio_request()
784 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_request()
794 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_free()
795 bank->mod_usage &= ~(BIT(offset)); in omap_gpio_free()
796 if (!LINE_USED(bank->irq_usage, offset)) { in omap_gpio_free()
801 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_free()
803 pm_runtime_put(chip->parent); in omap_gpio_free()
810 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset)) in omap_gpio_get_direction()
822 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_input()
824 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_input()
834 reg = bank->base + bank->regs->datain; in omap_gpio_get()
836 reg = bank->base + bank->regs->dataout; in omap_gpio_get()
847 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_output()
848 bank->set_dataout(bank, offset, value); in omap_gpio_output()
850 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_output()
858 void __iomem *base = bank->base; in omap_gpio_get_multiple()
861 direction = readl_relaxed(base + bank->regs->direction); in omap_gpio_get_multiple()
865 val |= readl_relaxed(base + bank->regs->datain) & m; in omap_gpio_get_multiple()
869 val |= readl_relaxed(base + bank->regs->dataout) & m; in omap_gpio_get_multiple()
885 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_debounce()
887 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_debounce()
890 dev_info(chip->parent, in omap_gpio_debounce()
901 int ret = -ENOTSUPP; in omap_gpio_set_config()
926 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_set()
927 bank->set_dataout(bank, offset, value); in omap_gpio_set()
928 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_set()
935 void __iomem *reg = bank->base + bank->regs->dataout; in omap_gpio_set_multiple()
939 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_set_multiple()
942 bank->context.dataout = l; in omap_gpio_set_multiple()
943 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_set_multiple()
946 /*---------------------------------------------------------------------*/
953 if (called || bank->regs->revision == USHRT_MAX) in omap_gpio_show_rev()
956 rev = readw_relaxed(bank->base + bank->regs->revision); in omap_gpio_show_rev()
957 pr_info("OMAP GPIO hardware version %d.%d\n", in omap_gpio_show_rev()
965 void __iomem *base = bank->base; in omap_gpio_mod_init()
968 if (bank->width == 16) in omap_gpio_mod_init()
971 if (bank->is_mpuio) { in omap_gpio_mod_init()
972 writel_relaxed(l, bank->base + bank->regs->irqenable); in omap_gpio_mod_init()
976 omap_gpio_rmw(base + bank->regs->irqenable, l, in omap_gpio_mod_init()
977 bank->regs->irqenable_inv); in omap_gpio_mod_init()
978 omap_gpio_rmw(base + bank->regs->irqstatus, l, in omap_gpio_mod_init()
979 !bank->regs->irqenable_inv); in omap_gpio_mod_init()
980 if (bank->regs->debounce_en) in omap_gpio_mod_init()
981 writel_relaxed(0, base + bank->regs->debounce_en); in omap_gpio_mod_init()
984 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); in omap_gpio_mod_init()
986 if (bank->regs->ctrl) in omap_gpio_mod_init()
987 writel_relaxed(0, base + bank->regs->ctrl); in omap_gpio_mod_init()
993 static int gpio; in omap_gpio_chip_init() local
999 * REVISIT eventually switch from OMAP-specific gpio structs in omap_gpio_chip_init()
1002 bank->chip.request = omap_gpio_request; in omap_gpio_chip_init()
1003 bank->chip.free = omap_gpio_free; in omap_gpio_chip_init()
1004 bank->chip.get_direction = omap_gpio_get_direction; in omap_gpio_chip_init()
1005 bank->chip.direction_input = omap_gpio_input; in omap_gpio_chip_init()
1006 bank->chip.get = omap_gpio_get; in omap_gpio_chip_init()
1007 bank->chip.get_multiple = omap_gpio_get_multiple; in omap_gpio_chip_init()
1008 bank->chip.direction_output = omap_gpio_output; in omap_gpio_chip_init()
1009 bank->chip.set_config = omap_gpio_set_config; in omap_gpio_chip_init()
1010 bank->chip.set = omap_gpio_set; in omap_gpio_chip_init()
1011 bank->chip.set_multiple = omap_gpio_set_multiple; in omap_gpio_chip_init()
1012 if (bank->is_mpuio) { in omap_gpio_chip_init()
1013 bank->chip.label = "mpuio"; in omap_gpio_chip_init()
1014 if (bank->regs->wkup_en) in omap_gpio_chip_init()
1015 bank->chip.parent = &omap_mpuio_device.dev; in omap_gpio_chip_init()
1016 bank->chip.base = OMAP_MPUIO(0); in omap_gpio_chip_init()
1018 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", in omap_gpio_chip_init()
1019 gpio, gpio + bank->width - 1); in omap_gpio_chip_init()
1021 return -ENOMEM; in omap_gpio_chip_init()
1022 bank->chip.label = label; in omap_gpio_chip_init()
1023 bank->chip.base = gpio; in omap_gpio_chip_init()
1025 bank->chip.ngpio = bank->width; in omap_gpio_chip_init()
1032 irq_base = devm_irq_alloc_descs(bank->chip.parent, in omap_gpio_chip_init()
1033 -1, 0, bank->width, 0); in omap_gpio_chip_init()
1035 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n"); in omap_gpio_chip_init()
1036 return -ENODEV; in omap_gpio_chip_init()
1041 if (bank->is_mpuio && !bank->regs->wkup_en) in omap_gpio_chip_init()
1042 irqc->irq_set_wake = NULL; in omap_gpio_chip_init()
1044 irq = &bank->chip.irq; in omap_gpio_chip_init()
1045 irq->chip = irqc; in omap_gpio_chip_init()
1046 irq->handler = handle_bad_irq; in omap_gpio_chip_init()
1047 irq->default_type = IRQ_TYPE_NONE; in omap_gpio_chip_init()
1048 irq->num_parents = 1; in omap_gpio_chip_init()
1049 irq->parents = &bank->irq; in omap_gpio_chip_init()
1050 irq->first = irq_base; in omap_gpio_chip_init()
1052 ret = gpiochip_add_data(&bank->chip, bank); in omap_gpio_chip_init()
1054 dev_err(bank->chip.parent, in omap_gpio_chip_init()
1055 "Could not register gpio chip %d\n", ret); in omap_gpio_chip_init()
1059 ret = devm_request_irq(bank->chip.parent, bank->irq, in omap_gpio_chip_init()
1061 0, dev_name(bank->chip.parent), bank); in omap_gpio_chip_init()
1063 gpiochip_remove(&bank->chip); in omap_gpio_chip_init()
1065 if (!bank->is_mpuio) in omap_gpio_chip_init()
1066 gpio += bank->width; in omap_gpio_chip_init()
1073 const struct omap_gpio_reg_offs *regs = p->regs; in omap_gpio_init_context()
1074 void __iomem *base = p->base; in omap_gpio_init_context()
1076 p->context.sysconfig = readl_relaxed(base + regs->sysconfig); in omap_gpio_init_context()
1077 p->context.ctrl = readl_relaxed(base + regs->ctrl); in omap_gpio_init_context()
1078 p->context.oe = readl_relaxed(base + regs->direction); in omap_gpio_init_context()
1079 p->context.wake_en = readl_relaxed(base + regs->wkup_en); in omap_gpio_init_context()
1080 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); in omap_gpio_init_context()
1081 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); in omap_gpio_init_context()
1082 p->context.risingdetect = readl_relaxed(base + regs->risingdetect); in omap_gpio_init_context()
1083 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); in omap_gpio_init_context()
1084 p->context.irqenable1 = readl_relaxed(base + regs->irqenable); in omap_gpio_init_context()
1085 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); in omap_gpio_init_context()
1086 p->context.dataout = readl_relaxed(base + regs->dataout); in omap_gpio_init_context()
1088 p->context_valid = true; in omap_gpio_init_context()
1093 const struct omap_gpio_reg_offs *regs = bank->regs; in omap_gpio_restore_context()
1094 void __iomem *base = bank->base; in omap_gpio_restore_context()
1096 writel_relaxed(bank->context.sysconfig, base + regs->sysconfig); in omap_gpio_restore_context()
1097 writel_relaxed(bank->context.wake_en, base + regs->wkup_en); in omap_gpio_restore_context()
1098 writel_relaxed(bank->context.ctrl, base + regs->ctrl); in omap_gpio_restore_context()
1099 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0); in omap_gpio_restore_context()
1100 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1); in omap_gpio_restore_context()
1101 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect); in omap_gpio_restore_context()
1102 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect); in omap_gpio_restore_context()
1103 writel_relaxed(bank->context.dataout, base + regs->dataout); in omap_gpio_restore_context()
1104 writel_relaxed(bank->context.oe, base + regs->direction); in omap_gpio_restore_context()
1106 if (bank->dbck_enable_mask) { in omap_gpio_restore_context()
1107 writel_relaxed(bank->context.debounce, base + regs->debounce); in omap_gpio_restore_context()
1108 writel_relaxed(bank->context.debounce_en, in omap_gpio_restore_context()
1109 base + regs->debounce_en); in omap_gpio_restore_context()
1112 writel_relaxed(bank->context.irqenable1, base + regs->irqenable); in omap_gpio_restore_context()
1113 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2); in omap_gpio_restore_context()
1118 struct device *dev = bank->chip.parent; in omap_gpio_idle()
1119 void __iomem *base = bank->base; in omap_gpio_idle()
1122 bank->saved_datain = readl_relaxed(base + bank->regs->datain); in omap_gpio_idle()
1125 if (bank->loses_context) in omap_gpio_idle()
1126 bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig); in omap_gpio_idle()
1128 if (!bank->enabled_non_wakeup_gpios) in omap_gpio_idle()
1132 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect; in omap_gpio_idle()
1133 mask &= ~bank->context.risingdetect; in omap_gpio_idle()
1134 bank->saved_datain |= mask; in omap_gpio_idle()
1137 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect; in omap_gpio_idle()
1138 mask &= ~bank->context.fallingdetect; in omap_gpio_idle()
1139 bank->saved_datain &= ~mask; in omap_gpio_idle()
1146 * non-wakeup GPIOs. Otherwise spurious IRQs will be in omap_gpio_idle()
1149 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { in omap_gpio_idle()
1150 nowake = bank->enabled_non_wakeup_gpios; in omap_gpio_idle()
1151 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake); in omap_gpio_idle()
1152 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake); in omap_gpio_idle()
1156 if (bank->get_context_loss_count) in omap_gpio_idle()
1157 bank->context_loss_count = in omap_gpio_idle()
1158 bank->get_context_loss_count(dev); in omap_gpio_idle()
1165 struct device *dev = bank->chip.parent; in omap_gpio_unidle()
1174 if (bank->loses_context && !bank->context_valid) { in omap_gpio_unidle()
1177 if (bank->get_context_loss_count) in omap_gpio_unidle()
1178 bank->context_loss_count = in omap_gpio_unidle()
1179 bank->get_context_loss_count(dev); in omap_gpio_unidle()
1184 if (bank->loses_context) { in omap_gpio_unidle()
1185 if (!bank->get_context_loss_count) { in omap_gpio_unidle()
1188 c = bank->get_context_loss_count(dev); in omap_gpio_unidle()
1189 if (c != bank->context_loss_count) { in omap_gpio_unidle()
1197 writel_relaxed(bank->context.fallingdetect, in omap_gpio_unidle()
1198 bank->base + bank->regs->fallingdetect); in omap_gpio_unidle()
1199 writel_relaxed(bank->context.risingdetect, in omap_gpio_unidle()
1200 bank->base + bank->regs->risingdetect); in omap_gpio_unidle()
1203 l = readl_relaxed(bank->base + bank->regs->datain); in omap_gpio_unidle()
1206 * Check if any of the non-wakeup interrupt GPIOs have changed in omap_gpio_unidle()
1211 l ^= bank->saved_datain; in omap_gpio_unidle()
1212 l &= bank->enabled_non_wakeup_gpios; in omap_gpio_unidle()
1215 * No need to generate IRQs for the rising edge for gpio IRQs in omap_gpio_unidle()
1218 gen0 = l & bank->context.fallingdetect; in omap_gpio_unidle()
1219 gen0 &= bank->saved_datain; in omap_gpio_unidle()
1221 gen1 = l & bank->context.risingdetect; in omap_gpio_unidle()
1222 gen1 &= ~(bank->saved_datain); in omap_gpio_unidle()
1224 /* FIXME: Consider GPIO IRQs with level detections properly! */ in omap_gpio_unidle()
1225 gen = l & (~(bank->context.fallingdetect) & in omap_gpio_unidle()
1226 ~(bank->context.risingdetect)); in omap_gpio_unidle()
1227 /* Consider all GPIO IRQs needed to be updated */ in omap_gpio_unidle()
1233 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); in omap_gpio_unidle()
1234 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); in omap_gpio_unidle()
1236 if (!bank->regs->irqstatus_raw0) { in omap_gpio_unidle()
1237 writel_relaxed(old0 | gen, bank->base + in omap_gpio_unidle()
1238 bank->regs->leveldetect0); in omap_gpio_unidle()
1239 writel_relaxed(old1 | gen, bank->base + in omap_gpio_unidle()
1240 bank->regs->leveldetect1); in omap_gpio_unidle()
1243 if (bank->regs->irqstatus_raw0) { in omap_gpio_unidle()
1244 writel_relaxed(old0 | l, bank->base + in omap_gpio_unidle()
1245 bank->regs->leveldetect0); in omap_gpio_unidle()
1246 writel_relaxed(old1 | l, bank->base + in omap_gpio_unidle()
1247 bank->regs->leveldetect1); in omap_gpio_unidle()
1249 writel_relaxed(old0, bank->base + bank->regs->leveldetect0); in omap_gpio_unidle()
1250 writel_relaxed(old1, bank->base + bank->regs->leveldetect1); in omap_gpio_unidle()
1264 raw_spin_lock_irqsave(&bank->lock, flags); in gpio_omap_cpu_notifier()
1265 if (bank->is_suspended) in gpio_omap_cpu_notifier()
1271 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask; in gpio_omap_cpu_notifier()
1285 raw_spin_unlock_irqrestore(&bank->lock, flags); in gpio_omap_cpu_notifier()
1306 .ctrl = OMAP24XX_GPIO_CTRL,
1332 .ctrl = OMAP4_GPIO_CTRL,
1360 .compatible = "ti,omap4-gpio",
1364 .compatible = "ti,omap3-gpio",
1368 .compatible = "ti,omap2-gpio",
1377 struct device *dev = &pdev->dev; in omap_gpio_probe()
1378 struct device_node *node = dev->of_node; in omap_gpio_probe()
1387 pdata = match ? match->data : dev_get_platdata(dev); in omap_gpio_probe()
1389 return -EINVAL; in omap_gpio_probe()
1393 return -ENOMEM; in omap_gpio_probe()
1397 return -ENOMEM; in omap_gpio_probe()
1399 irqc->irq_startup = omap_gpio_irq_startup, in omap_gpio_probe()
1400 irqc->irq_shutdown = omap_gpio_irq_shutdown, in omap_gpio_probe()
1401 irqc->irq_ack = dummy_irq_chip.irq_ack, in omap_gpio_probe()
1402 irqc->irq_mask = omap_gpio_mask_irq, in omap_gpio_probe()
1403 irqc->irq_unmask = omap_gpio_unmask_irq, in omap_gpio_probe()
1404 irqc->irq_set_type = omap_gpio_irq_type, in omap_gpio_probe()
1405 irqc->irq_set_wake = omap_gpio_wake_enable, in omap_gpio_probe()
1406 irqc->irq_bus_lock = omap_gpio_irq_bus_lock, in omap_gpio_probe()
1407 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, in omap_gpio_probe()
1408 irqc->name = dev_name(&pdev->dev); in omap_gpio_probe()
1409 irqc->flags = IRQCHIP_MASK_ON_SUSPEND; in omap_gpio_probe()
1410 irqc->parent_device = dev; in omap_gpio_probe()
1412 bank->irq = platform_get_irq(pdev, 0); in omap_gpio_probe()
1413 if (bank->irq <= 0) { in omap_gpio_probe()
1414 if (!bank->irq) in omap_gpio_probe()
1415 bank->irq = -ENXIO; in omap_gpio_probe()
1416 return dev_err_probe(dev, bank->irq, "can't get irq resource\n"); in omap_gpio_probe()
1419 bank->chip.parent = dev; in omap_gpio_probe()
1420 bank->chip.owner = THIS_MODULE; in omap_gpio_probe()
1421 bank->dbck_flag = pdata->dbck_flag; in omap_gpio_probe()
1422 bank->stride = pdata->bank_stride; in omap_gpio_probe()
1423 bank->width = pdata->bank_width; in omap_gpio_probe()
1424 bank->is_mpuio = pdata->is_mpuio; in omap_gpio_probe()
1425 bank->non_wakeup_gpios = pdata->non_wakeup_gpios; in omap_gpio_probe()
1426 bank->regs = pdata->regs; in omap_gpio_probe()
1428 bank->chip.of_node = of_node_get(node); in omap_gpio_probe()
1432 if (!of_property_read_bool(node, "ti,gpio-always-on")) in omap_gpio_probe()
1433 bank->loses_context = true; in omap_gpio_probe()
1435 bank->loses_context = pdata->loses_context; in omap_gpio_probe()
1437 if (bank->loses_context) in omap_gpio_probe()
1438 bank->get_context_loss_count = in omap_gpio_probe()
1439 pdata->get_context_loss_count; in omap_gpio_probe()
1442 if (bank->regs->set_dataout && bank->regs->clr_dataout) in omap_gpio_probe()
1443 bank->set_dataout = omap_set_gpio_dataout_reg; in omap_gpio_probe()
1445 bank->set_dataout = omap_set_gpio_dataout_mask; in omap_gpio_probe()
1447 raw_spin_lock_init(&bank->lock); in omap_gpio_probe()
1448 raw_spin_lock_init(&bank->wa_lock); in omap_gpio_probe()
1451 bank->base = devm_platform_ioremap_resource(pdev, 0); in omap_gpio_probe()
1452 if (IS_ERR(bank->base)) { in omap_gpio_probe()
1453 return PTR_ERR(bank->base); in omap_gpio_probe()
1456 if (bank->dbck_flag) { in omap_gpio_probe()
1457 bank->dbck = devm_clk_get(dev, "dbclk"); in omap_gpio_probe()
1458 if (IS_ERR(bank->dbck)) { in omap_gpio_probe()
1460 "Could not get gpio dbck. Disable debounce\n"); in omap_gpio_probe()
1461 bank->dbck_flag = false; in omap_gpio_probe()
1463 clk_prepare(bank->dbck); in omap_gpio_probe()
1472 if (bank->is_mpuio) in omap_gpio_probe()
1481 if (bank->dbck_flag) in omap_gpio_probe()
1482 clk_unprepare(bank->dbck); in omap_gpio_probe()
1488 bank->nb.notifier_call = gpio_omap_cpu_notifier; in omap_gpio_probe()
1489 cpu_pm_register_notifier(&bank->nb); in omap_gpio_probe()
1500 cpu_pm_unregister_notifier(&bank->nb); in omap_gpio_remove()
1501 gpiochip_remove(&bank->chip); in omap_gpio_remove()
1502 pm_runtime_disable(&pdev->dev); in omap_gpio_remove()
1503 if (bank->dbck_flag) in omap_gpio_remove()
1504 clk_unprepare(bank->dbck); in omap_gpio_remove()
1514 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_runtime_suspend()
1516 bank->is_suspended = true; in omap_gpio_runtime_suspend()
1517 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_runtime_suspend()
1527 raw_spin_lock_irqsave(&bank->lock, flags); in omap_gpio_runtime_resume()
1529 bank->is_suspended = false; in omap_gpio_runtime_resume()
1530 raw_spin_unlock_irqrestore(&bank->lock, flags); in omap_gpio_runtime_resume()
1539 if (bank->is_suspended) in omap_gpio_suspend()
1542 bank->needs_resume = 1; in omap_gpio_suspend()
1551 if (!bank->needs_resume) in omap_gpio_resume()
1554 bank->needs_resume = 0; in omap_gpio_resume()
1576 * gpio driver register needs to be done before
1577 * machine_init functions access gpio APIs.
1592 MODULE_DESCRIPTION("omap gpio driver");
1593 MODULE_ALIAS("platform:gpio-omap");