Lines Matching +full:4 +full:- +full:ring
50 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
53 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
61 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
64 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
458 switch (rdev->family) { in ni_init_golden_registers()
468 if ((rdev->pdev->device == 0x9900) || in ni_init_golden_registers()
469 (rdev->pdev->device == 0x9901) || in ni_init_golden_registers()
470 (rdev->pdev->device == 0x9903) || in ni_init_golden_registers()
471 (rdev->pdev->device == 0x9904) || in ni_init_golden_registers()
472 (rdev->pdev->device == 0x9905) || in ni_init_golden_registers()
473 (rdev->pdev->device == 0x9906) || in ni_init_golden_registers()
474 (rdev->pdev->device == 0x9907) || in ni_init_golden_registers()
475 (rdev->pdev->device == 0x9908) || in ni_init_golden_registers()
476 (rdev->pdev->device == 0x9909) || in ni_init_golden_registers()
477 (rdev->pdev->device == 0x990A) || in ni_init_golden_registers()
478 (rdev->pdev->device == 0x990B) || in ni_init_golden_registers()
479 (rdev->pdev->device == 0x990C) || in ni_init_golden_registers()
480 (rdev->pdev->device == 0x990D) || in ni_init_golden_registers()
481 (rdev->pdev->device == 0x990E) || in ni_init_golden_registers()
482 (rdev->pdev->device == 0x990F) || in ni_init_golden_registers()
483 (rdev->pdev->device == 0x9910) || in ni_init_golden_registers()
484 (rdev->pdev->device == 0x9913) || in ni_init_golden_registers()
485 (rdev->pdev->device == 0x9917) || in ni_init_golden_registers()
486 (rdev->pdev->device == 0x9918)) { in ni_init_golden_registers()
644 if (!rdev->mc_fw) in ni_mc_load_microcode()
645 return -EINVAL; in ni_mc_load_microcode()
647 switch (rdev->family) { in ni_mc_load_microcode()
690 fw_data = (const __be32 *)rdev->mc_fw->data; in ni_mc_load_microcode()
700 for (i = 0; i < rdev->usec_timeout; i++) { in ni_mc_load_microcode()
724 switch (rdev->family) { in ni_init_microcode()
728 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; in ni_init_microcode()
729 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; in ni_init_microcode()
730 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; in ni_init_microcode()
731 mc_req_size = BTC_MC_UCODE_SIZE * 4; in ni_init_microcode()
732 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4); in ni_init_microcode()
737 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; in ni_init_microcode()
738 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; in ni_init_microcode()
739 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; in ni_init_microcode()
740 mc_req_size = BTC_MC_UCODE_SIZE * 4; in ni_init_microcode()
741 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4); in ni_init_microcode()
746 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4; in ni_init_microcode()
747 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4; in ni_init_microcode()
748 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4; in ni_init_microcode()
749 mc_req_size = BTC_MC_UCODE_SIZE * 4; in ni_init_microcode()
750 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4); in ni_init_microcode()
755 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; in ni_init_microcode()
756 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; in ni_init_microcode()
757 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; in ni_init_microcode()
758 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; in ni_init_microcode()
759 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4); in ni_init_microcode()
765 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4; in ni_init_microcode()
766 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4; in ni_init_microcode()
767 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4; in ni_init_microcode()
776 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in ni_init_microcode()
779 if (rdev->pfp_fw->size != pfp_req_size) { in ni_init_microcode()
781 rdev->pfp_fw->size, fw_name); in ni_init_microcode()
782 err = -EINVAL; in ni_init_microcode()
787 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in ni_init_microcode()
790 if (rdev->me_fw->size != me_req_size) { in ni_init_microcode()
792 rdev->me_fw->size, fw_name); in ni_init_microcode()
793 err = -EINVAL; in ni_init_microcode()
797 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in ni_init_microcode()
800 if (rdev->rlc_fw->size != rlc_req_size) { in ni_init_microcode()
802 rdev->rlc_fw->size, fw_name); in ni_init_microcode()
803 err = -EINVAL; in ni_init_microcode()
807 if (!(rdev->flags & RADEON_IS_IGP)) { in ni_init_microcode()
809 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in ni_init_microcode()
812 if (rdev->mc_fw->size != mc_req_size) { in ni_init_microcode()
814 rdev->mc_fw->size, fw_name); in ni_init_microcode()
815 err = -EINVAL; in ni_init_microcode()
819 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { in ni_init_microcode()
821 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in ni_init_microcode()
824 release_firmware(rdev->smc_fw); in ni_init_microcode()
825 rdev->smc_fw = NULL; in ni_init_microcode()
827 } else if (rdev->smc_fw->size != smc_req_size) { in ni_init_microcode()
829 rdev->mc_fw->size, fw_name); in ni_init_microcode()
830 err = -EINVAL; in ni_init_microcode()
836 if (err != -EINVAL) in ni_init_microcode()
839 release_firmware(rdev->pfp_fw); in ni_init_microcode()
840 rdev->pfp_fw = NULL; in ni_init_microcode()
841 release_firmware(rdev->me_fw); in ni_init_microcode()
842 rdev->me_fw = NULL; in ni_init_microcode()
843 release_firmware(rdev->rlc_fw); in ni_init_microcode()
844 rdev->rlc_fw = NULL; in ni_init_microcode()
845 release_firmware(rdev->mc_fw); in ni_init_microcode()
846 rdev->mc_fw = NULL; in ni_init_microcode()
852 * cayman_get_allowed_info_register - fetch the register for the info ioctl
858 * Returns 0 for success or -EINVAL for an invalid register
876 return -EINVAL; in cayman_get_allowed_info_register()
883 int actual_temp = (temp / 8) - 49; in tn_get_temp()
904 switch (rdev->family) { in cayman_gpu_init()
906 rdev->config.cayman.max_shader_engines = 2; in cayman_gpu_init()
907 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
908 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()
909 rdev->config.cayman.max_simds_per_se = 12; in cayman_gpu_init()
910 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()
911 rdev->config.cayman.max_texture_channel_caches = 8; in cayman_gpu_init()
912 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
913 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
914 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
915 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
916 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
917 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
918 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
919 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
920 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
921 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
923 rdev->config.cayman.sc_prim_fifo_size = 0x100; in cayman_gpu_init()
924 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
925 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
930 rdev->config.cayman.max_shader_engines = 1; in cayman_gpu_init()
931 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
932 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
933 if ((rdev->pdev->device == 0x9900) || in cayman_gpu_init()
934 (rdev->pdev->device == 0x9901) || in cayman_gpu_init()
935 (rdev->pdev->device == 0x9905) || in cayman_gpu_init()
936 (rdev->pdev->device == 0x9906) || in cayman_gpu_init()
937 (rdev->pdev->device == 0x9907) || in cayman_gpu_init()
938 (rdev->pdev->device == 0x9908) || in cayman_gpu_init()
939 (rdev->pdev->device == 0x9909) || in cayman_gpu_init()
940 (rdev->pdev->device == 0x990B) || in cayman_gpu_init()
941 (rdev->pdev->device == 0x990C) || in cayman_gpu_init()
942 (rdev->pdev->device == 0x990F) || in cayman_gpu_init()
943 (rdev->pdev->device == 0x9910) || in cayman_gpu_init()
944 (rdev->pdev->device == 0x9917) || in cayman_gpu_init()
945 (rdev->pdev->device == 0x9999) || in cayman_gpu_init()
946 (rdev->pdev->device == 0x999C)) { in cayman_gpu_init()
947 rdev->config.cayman.max_simds_per_se = 6; in cayman_gpu_init()
948 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
949 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
950 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
951 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
952 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
953 } else if ((rdev->pdev->device == 0x9903) || in cayman_gpu_init()
954 (rdev->pdev->device == 0x9904) || in cayman_gpu_init()
955 (rdev->pdev->device == 0x990A) || in cayman_gpu_init()
956 (rdev->pdev->device == 0x990D) || in cayman_gpu_init()
957 (rdev->pdev->device == 0x990E) || in cayman_gpu_init()
958 (rdev->pdev->device == 0x9913) || in cayman_gpu_init()
959 (rdev->pdev->device == 0x9918) || in cayman_gpu_init()
960 (rdev->pdev->device == 0x999D)) { in cayman_gpu_init()
961 rdev->config.cayman.max_simds_per_se = 4; in cayman_gpu_init()
962 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
963 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
964 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
965 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
966 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
967 } else if ((rdev->pdev->device == 0x9919) || in cayman_gpu_init()
968 (rdev->pdev->device == 0x9990) || in cayman_gpu_init()
969 (rdev->pdev->device == 0x9991) || in cayman_gpu_init()
970 (rdev->pdev->device == 0x9994) || in cayman_gpu_init()
971 (rdev->pdev->device == 0x9995) || in cayman_gpu_init()
972 (rdev->pdev->device == 0x9996) || in cayman_gpu_init()
973 (rdev->pdev->device == 0x999A) || in cayman_gpu_init()
974 (rdev->pdev->device == 0x99A0)) { in cayman_gpu_init()
975 rdev->config.cayman.max_simds_per_se = 3; in cayman_gpu_init()
976 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
977 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
978 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
979 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
980 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
982 rdev->config.cayman.max_simds_per_se = 2; in cayman_gpu_init()
983 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
984 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
985 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
986 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
987 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
989 rdev->config.cayman.max_texture_channel_caches = 2; in cayman_gpu_init()
990 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
991 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
992 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
993 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
994 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
995 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
997 rdev->config.cayman.sc_prim_fifo_size = 0x40; in cayman_gpu_init()
998 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
999 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
1023 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in cayman_gpu_init()
1024 if (rdev->config.cayman.mem_row_size_in_kb > 4) in cayman_gpu_init()
1025 rdev->config.cayman.mem_row_size_in_kb = 4; in cayman_gpu_init()
1027 rdev->config.cayman.shader_engine_tile_size = 32; in cayman_gpu_init()
1028 rdev->config.cayman.num_gpus = 1; in cayman_gpu_init()
1029 rdev->config.cayman.multi_gpu_tile_size = 64; in cayman_gpu_init()
1032 rdev->config.cayman.num_tile_pipes = (1 << tmp); in cayman_gpu_init()
1034 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; in cayman_gpu_init()
1036 rdev->config.cayman.num_shader_engines = tmp + 1; in cayman_gpu_init()
1038 rdev->config.cayman.num_gpus = tmp + 1; in cayman_gpu_init()
1040 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; in cayman_gpu_init()
1042 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; in cayman_gpu_init()
1048 * bits 7:4 num_banks in cayman_gpu_init()
1052 rdev->config.cayman.tile_config = 0; in cayman_gpu_init()
1053 switch (rdev->config.cayman.num_tile_pipes) { in cayman_gpu_init()
1056 rdev->config.cayman.tile_config |= (0 << 0); in cayman_gpu_init()
1059 rdev->config.cayman.tile_config |= (1 << 0); in cayman_gpu_init()
1061 case 4: in cayman_gpu_init()
1062 rdev->config.cayman.tile_config |= (2 << 0); in cayman_gpu_init()
1065 rdev->config.cayman.tile_config |= (3 << 0); in cayman_gpu_init()
1069 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */ in cayman_gpu_init()
1070 if (rdev->flags & RADEON_IS_IGP) in cayman_gpu_init()
1071 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1075 rdev->config.cayman.tile_config |= 0 << 4; in cayman_gpu_init()
1078 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1082 rdev->config.cayman.tile_config |= 2 << 4; in cayman_gpu_init()
1086 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1088 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1092 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { in cayman_gpu_init()
1098 tmp <<= 4; in cayman_gpu_init()
1104 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1108 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1112 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { in cayman_gpu_init()
1118 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in cayman_gpu_init()
1122 rdev->config.cayman.active_simds = hweight32(~tmp); in cayman_gpu_init()
1138 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()
1139 (rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_init()
1150 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
1151 rdev->config.cayman.max_shader_engines, in cayman_gpu_init()
1154 rdev->config.cayman.backend_map = tmp; in cayman_gpu_init()
1158 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) in cayman_gpu_init()
1180 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); in cayman_gpu_init()
1183 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE); in cayman_gpu_init()
1185 /* need to be explicitly zero-ed */ in cayman_gpu_init()
1196 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1… in cayman_gpu_init()
1197 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | in cayman_gpu_init()
1198 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); in cayman_gpu_init()
1200 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | in cayman_gpu_init()
1201 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | in cayman_gpu_init()
1202 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); in cayman_gpu_init()
1209 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | in cayman_gpu_init()
1214 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4)); in cayman_gpu_init()
1252 if (rdev->family == CHIP_ARUBA) { in cayman_gpu_init()
1270 /* bits 0-7 are the VM contexts0-7 */ in cayman_pcie_gart_tlb_flush()
1278 if (rdev->gart.robj == NULL) { in cayman_pcie_gart_enable()
1279 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in cayman_pcie_gart_enable()
1280 return -EINVAL; in cayman_pcie_gart_enable()
1305 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cayman_pcie_gart_enable()
1306 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cayman_pcie_gart_enable()
1307 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1309 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1318 /* empty context1-7 */ in cayman_pcie_gart_enable()
1326 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1328 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1331 /* enable context1-7 */ in cayman_pcie_gart_enable()
1333 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1334 WREG32(VM_CONTEXT1_CNTL2, 4); in cayman_pcie_gart_enable()
1336 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) | in cayman_pcie_gart_enable()
1352 (unsigned)(rdev->mc.gtt_size >> 20), in cayman_pcie_gart_enable()
1353 (unsigned long long)rdev->gart.table_addr); in cayman_pcie_gart_enable()
1354 rdev->gart.ready = true; in cayman_pcie_gart_enable()
1363 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
1393 int ring, u32 cp_int_cntl) in cayman_cp_int_cntl_setup() argument
1395 WREG32(SRBM_GFX_CNTL, RINGID(ring)); in cayman_cp_int_cntl_setup()
1405 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cayman_fence_ring_emit() local
1406 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
1411 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_fence_ring_emit()
1412 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); in cayman_fence_ring_emit()
1413 radeon_ring_write(ring, 0xFFFFFFFF); in cayman_fence_ring_emit()
1414 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1415 radeon_ring_write(ring, 10); /* poll interval */ in cayman_fence_ring_emit()
1416 /* EVENT_WRITE_EOP - flush caches, send int */ in cayman_fence_ring_emit()
1417 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cayman_fence_ring_emit()
1418 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); in cayman_fence_ring_emit()
1419 radeon_ring_write(ring, lower_32_bits(addr)); in cayman_fence_ring_emit()
1420 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
1421 radeon_ring_write(ring, fence->seq); in cayman_fence_ring_emit()
1422 radeon_ring_write(ring, 0); in cayman_fence_ring_emit()
1427 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cayman_ring_ib_execute() local
1428 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; in cayman_ring_ib_execute()
1433 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); in cayman_ring_ib_execute()
1434 radeon_ring_write(ring, 1); in cayman_ring_ib_execute()
1436 if (ring->rptr_save_reg) { in cayman_ring_ib_execute()
1437 uint32_t next_rptr = ring->wptr + 3 + 4 + 8; in cayman_ring_ib_execute()
1438 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); in cayman_ring_ib_execute()
1439 radeon_ring_write(ring, ((ring->rptr_save_reg - in cayman_ring_ib_execute()
1441 radeon_ring_write(ring, next_rptr); in cayman_ring_ib_execute()
1444 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); in cayman_ring_ib_execute()
1445 radeon_ring_write(ring, in cayman_ring_ib_execute()
1449 (ib->gpu_addr & 0xFFFFFFFC)); in cayman_ring_ib_execute()
1450 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF); in cayman_ring_ib_execute()
1451 radeon_ring_write(ring, ib->length_dw | (vm_id << 24)); in cayman_ring_ib_execute()
1454 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); in cayman_ring_ib_execute()
1455 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); in cayman_ring_ib_execute()
1456 radeon_ring_write(ring, 0xFFFFFFFF); in cayman_ring_ib_execute()
1457 radeon_ring_write(ring, 0); in cayman_ring_ib_execute()
1458 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */ in cayman_ring_ib_execute()
1466 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_enable()
1467 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in cayman_cp_enable()
1470 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_enable()
1475 struct radeon_ring *ring) in cayman_gfx_get_rptr() argument
1479 if (rdev->wb.enabled) in cayman_gfx_get_rptr()
1480 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_gfx_get_rptr()
1482 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) in cayman_gfx_get_rptr()
1484 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) in cayman_gfx_get_rptr()
1494 struct radeon_ring *ring) in cayman_gfx_get_wptr() argument
1498 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) in cayman_gfx_get_wptr()
1500 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) in cayman_gfx_get_wptr()
1509 struct radeon_ring *ring) in cayman_gfx_set_wptr() argument
1511 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) { in cayman_gfx_set_wptr()
1512 WREG32(CP_RB0_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1514 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) { in cayman_gfx_set_wptr()
1515 WREG32(CP_RB1_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1518 WREG32(CP_RB2_WPTR, ring->wptr); in cayman_gfx_set_wptr()
1528 if (!rdev->me_fw || !rdev->pfp_fw) in cayman_cp_load_microcode()
1529 return -EINVAL; in cayman_cp_load_microcode()
1533 fw_data = (const __be32 *)rdev->pfp_fw->data; in cayman_cp_load_microcode()
1539 fw_data = (const __be32 *)rdev->me_fw->data; in cayman_cp_load_microcode()
1552 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_start() local
1555 r = radeon_ring_lock(rdev, ring, 7); in cayman_cp_start()
1557 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); in cayman_cp_start()
1560 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5)); in cayman_cp_start()
1561 radeon_ring_write(ring, 0x1); in cayman_cp_start()
1562 radeon_ring_write(ring, 0x0); in cayman_cp_start()
1563 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); in cayman_cp_start()
1564 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); in cayman_cp_start()
1565 radeon_ring_write(ring, 0); in cayman_cp_start()
1566 radeon_ring_write(ring, 0); in cayman_cp_start()
1567 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1571 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); in cayman_cp_start()
1573 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); in cayman_cp_start()
1578 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1579 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cayman_cp_start()
1582 radeon_ring_write(ring, cayman_default_state[i]); in cayman_cp_start()
1584 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cayman_cp_start()
1585 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cayman_cp_start()
1588 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cayman_cp_start()
1589 radeon_ring_write(ring, 0); in cayman_cp_start()
1592 radeon_ring_write(ring, 0xc0026f00); in cayman_cp_start()
1593 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1594 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1595 radeon_ring_write(ring, 0x00000000); in cayman_cp_start()
1598 radeon_ring_write(ring, 0xc0036f00); in cayman_cp_start()
1599 radeon_ring_write(ring, 0x00000bc4); in cayman_cp_start()
1600 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1601 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1602 radeon_ring_write(ring, 0xffffffff); in cayman_cp_start()
1604 radeon_ring_write(ring, 0xc0026900); in cayman_cp_start()
1605 radeon_ring_write(ring, 0x00000316); in cayman_cp_start()
1606 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in cayman_cp_start()
1607 radeon_ring_write(ring, 0x00000010); /* */ in cayman_cp_start()
1609 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1618 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_fini() local
1620 radeon_ring_fini(rdev, ring); in cayman_cp_fini()
1621 radeon_scratch_free(rdev, ring->rptr_save_reg); in cayman_cp_fini()
1661 struct radeon_ring *ring; in cayman_cp_resume() local
1685 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cayman_cp_resume()
1692 /* Set ring buffer size */ in cayman_cp_resume()
1693 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1694 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1702 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; in cayman_cp_resume()
1709 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1710 WREG32(cp_rb_base[i], ring->gpu_addr >> 8); in cayman_cp_resume()
1714 /* Initialize the ring buffer's read and write pointers */ in cayman_cp_resume()
1715 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1718 ring->wptr = 0; in cayman_cp_resume()
1720 WREG32(cp_rb_wptr[i], ring->wptr); in cayman_cp_resume()
1728 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cayman_cp_resume()
1729 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1730 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1732 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cayman_cp_resume()
1734 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_resume()
1735 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1736 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1740 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_resume()
1741 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in cayman_cp_resume()
1833 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in cayman_gpu_soft_reset()
1836 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1838 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1840 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1842 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1866 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in cayman_gpu_soft_reset()
1914 if (!(rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_soft_reset()
1922 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1936 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1983 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1986 * @ring: radeon_ring structure holding ring information
1991 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in cayman_gfx_is_lockup() argument
1998 radeon_ring_lockup_update(rdev, ring); in cayman_gfx_is_lockup()
2001 return radeon_ring_test_lockup(rdev, ring); in cayman_gfx_is_lockup()
2008 if (!rdev->has_uvd) in cayman_uvd_init()
2013 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in cayman_uvd_init()
2015 * At this point rdev->uvd.vcpu_bo is NULL which trickles down in cayman_uvd_init()
2020 rdev->has_uvd = false; in cayman_uvd_init()
2023 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in cayman_uvd_init()
2024 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in cayman_uvd_init()
2031 if (!rdev->has_uvd) in cayman_uvd_start()
2036 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in cayman_uvd_start()
2041 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in cayman_uvd_start()
2047 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cayman_uvd_start()
2052 struct radeon_ring *ring; in cayman_uvd_resume() local
2055 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in cayman_uvd_resume()
2058 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_uvd_resume()
2059 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in cayman_uvd_resume()
2061 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in cayman_uvd_resume()
2066 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in cayman_uvd_resume()
2076 if (!rdev->has_vce) in cayman_vce_init()
2081 dev_err(rdev->dev, "failed VCE (%d) init.\n", r); in cayman_vce_init()
2083 * At this point rdev->vce.vcpu_bo is NULL which trickles down in cayman_vce_init()
2088 rdev->has_vce = false; in cayman_vce_init()
2091 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL; in cayman_vce_init()
2092 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096); in cayman_vce_init()
2093 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL; in cayman_vce_init()
2094 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096); in cayman_vce_init()
2101 if (!rdev->has_vce) in cayman_vce_start()
2106 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in cayman_vce_start()
2111 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in cayman_vce_start()
2116 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r); in cayman_vce_start()
2121 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r); in cayman_vce_start()
2127 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in cayman_vce_start()
2128 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in cayman_vce_start()
2133 struct radeon_ring *ring; in cayman_vce_resume() local
2136 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size) in cayman_vce_resume()
2139 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cayman_vce_resume()
2140 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2142 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in cayman_vce_resume()
2145 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cayman_vce_resume()
2146 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2148 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in cayman_vce_resume()
2153 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r); in cayman_vce_resume()
2160 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_startup() local
2175 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { in cayman_startup()
2189 if (rdev->flags & RADEON_IS_IGP) { in cayman_startup()
2190 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; in cayman_startup()
2191 rdev->rlc.reg_list_size = in cayman_startup()
2193 rdev->rlc.cs_data = cayman_cs_data; in cayman_startup()
2208 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2217 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2223 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2229 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2235 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2240 if (!rdev->irq.installed) { in cayman_startup()
2254 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cayman_startup()
2259 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_startup()
2260 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in cayman_startup()
2265 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_startup()
2266 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in cayman_startup()
2287 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in cayman_startup()
2293 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); in cayman_startup()
2313 atom_asic_init(rdev->mode_info.atom_context); in cayman_resume()
2318 if (rdev->pm.pm_method == PM_METHOD_DPM) in cayman_resume()
2321 rdev->accel_working = true; in cayman_resume()
2325 rdev->accel_working = false; in cayman_resume()
2338 if (rdev->has_uvd) { in cayman_suspend()
2356 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_init() local
2362 return -EINVAL; in cayman_init()
2365 if (!rdev->is_atom_bios) { in cayman_init()
2366 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); in cayman_init()
2367 return -EINVAL; in cayman_init()
2375 if (!rdev->bios) { in cayman_init()
2376 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in cayman_init()
2377 return -EINVAL; in cayman_init()
2380 atom_asic_init(rdev->mode_info.atom_context); in cayman_init()
2389 radeon_get_clock_info(rdev->ddev); in cayman_init()
2403 if (rdev->flags & RADEON_IS_IGP) { in cayman_init()
2404 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in cayman_init()
2412 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in cayman_init()
2424 ring->ring_obj = NULL; in cayman_init()
2425 r600_ring_init(rdev, ring, 1024 * 1024); in cayman_init()
2427 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_init()
2428 ring->ring_obj = NULL; in cayman_init()
2429 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2431 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_init()
2432 ring->ring_obj = NULL; in cayman_init()
2433 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2438 rdev->ih.ring_obj = NULL; in cayman_init()
2445 rdev->accel_working = true; in cayman_init()
2448 dev_err(rdev->dev, "disabling GPU acceleration\n"); in cayman_init()
2452 if (rdev->flags & RADEON_IS_IGP) in cayman_init()
2459 rdev->accel_working = false; in cayman_init()
2469 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { in cayman_init()
2471 return -EINVAL; in cayman_init()
2483 if (rdev->flags & RADEON_IS_IGP) in cayman_fini()
2491 if (rdev->has_vce) in cayman_fini()
2499 kfree(rdev->bios); in cayman_fini()
2500 rdev->bios = NULL; in cayman_fini()
2509 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2511 if (rdev->flags & RADEON_IS_IGP) { in cayman_vm_init()
2514 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2516 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()
2525 * cayman_vm_decode_fault - print human readable fault info
2686 * cayman_vm_flush - vm flush using the CP
2691 * using the CP (cayman-si).
2693 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in cayman_vm_flush() argument
2696 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0)); in cayman_vm_flush()
2697 radeon_ring_write(ring, pd_addr >> 12); in cayman_vm_flush()
2700 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0)); in cayman_vm_flush()
2701 radeon_ring_write(ring, 0x1); in cayman_vm_flush()
2703 /* bits 0-7 are the VM contexts0-7 */ in cayman_vm_flush()
2704 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0)); in cayman_vm_flush()
2705 radeon_ring_write(ring, 1 << vm_id); in cayman_vm_flush()
2708 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cayman_vm_flush()
2709 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */ in cayman_vm_flush()
2711 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cayman_vm_flush()
2712 radeon_ring_write(ring, 0); in cayman_vm_flush()
2713 radeon_ring_write(ring, 0); /* ref */ in cayman_vm_flush()
2714 radeon_ring_write(ring, 0); /* mask */ in cayman_vm_flush()
2715 radeon_ring_write(ring, 0x20); /* poll interval */ in cayman_vm_flush()
2718 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cayman_vm_flush()
2719 radeon_ring_write(ring, 0x0); in cayman_vm_flush()
2738 return -ETIMEDOUT; in tn_set_vce_clocks()
2748 return -ETIMEDOUT; in tn_set_vce_clocks()