Lines Matching +full:tegra194 +full:- +full:display
1 // SPDX-License-Identifier: GPL-2.0-only
36 stats->frames = 0; in tegra_dc_stats_reset()
37 stats->vblank = 0; in tegra_dc_stats_reset()
38 stats->underflow = 0; in tegra_dc_stats_reset()
39 stats->overflow = 0; in tegra_dc_stats_reset()
58 offset = 0x000 + (offset - 0x500); in tegra_plane_offset()
59 return plane->offset + offset; in tegra_plane_offset()
63 offset = 0x180 + (offset - 0x700); in tegra_plane_offset()
64 return plane->offset + offset; in tegra_plane_offset()
68 offset = 0x1c0 + (offset - 0x800); in tegra_plane_offset()
69 return plane->offset + offset; in tegra_plane_offset()
72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); in tegra_plane_offset()
74 return plane->offset + offset; in tegra_plane_offset()
80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); in tegra_plane_readl()
86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); in tegra_plane_writel()
91 struct device_node *np = dc->dev->of_node; in tegra_dc_has_output()
96 if (it.node == dev->of_node) in tegra_dc_has_output()
103 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the
105 * Latching happens mmediately if the display controller is in STOP mode or
108 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The
111 * into the ACTIVE copy, either immediately if the display controller is in
145 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); in compute_dda_inc()
146 inf.full -= dfixed_const(1); in compute_dda_inc()
174 /* disable blending for non-overlapping case */ in tegra_plane_setup_blending_legacy()
178 state = to_tegra_plane_state(plane->base.state); in tegra_plane_setup_blending_legacy()
180 if (state->opaque) { in tegra_plane_setup_blending_legacy()
182 * Since custom fix-weight blending isn't utilized and weight in tegra_plane_setup_blending_legacy()
199 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
201 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
202 state->blending[1].alpha) in tegra_plane_setup_blending_legacy()
224 if (state->blending[i].alpha && in tegra_plane_setup_blending_legacy()
225 state->blending[i].top) in tegra_plane_setup_blending_legacy()
229 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
231 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
232 state->blending[1].alpha) in tegra_plane_setup_blending_legacy()
242 if (state->blending[0].alpha && in tegra_plane_setup_blending_legacy()
243 state->blending[0].top) in tegra_plane_setup_blending_legacy()
246 if (state->blending[1].alpha && in tegra_plane_setup_blending_legacy()
247 state->blending[1].top) in tegra_plane_setup_blending_legacy()
253 switch (state->base.normalized_zpos) { in tegra_plane_setup_blending_legacy()
266 if (!state->blending[0].top && state->blending[1].top) { in tegra_plane_setup_blending_legacy()
302 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); in tegra_plane_setup_blending()
310 struct tegra_dc *dc = plane->dc; in tegra_plane_use_horizontal_filtering()
312 if (window->src.w == window->dst.w) in tegra_plane_use_horizontal_filtering()
315 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_horizontal_filtering()
325 struct tegra_dc *dc = plane->dc; in tegra_plane_use_vertical_filtering()
327 if (window->src.h == window->dst.h) in tegra_plane_use_vertical_filtering()
330 if (plane->index == 0 && dc->soc->has_win_a_without_filters) in tegra_plane_use_vertical_filtering()
333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) in tegra_plane_use_vertical_filtering()
343 struct tegra_dc *dc = plane->dc; in tegra_dc_setup_window()
351 yuv = tegra_plane_format_is_yuv(window->format, &planar); in tegra_dc_setup_window()
353 bpp = window->bits_per_pixel / 8; in tegra_dc_setup_window()
357 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); in tegra_dc_setup_window()
358 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); in tegra_dc_setup_window()
360 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); in tegra_dc_setup_window()
363 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); in tegra_dc_setup_window()
366 h_offset = window->src.x * bpp; in tegra_dc_setup_window()
367 v_offset = window->src.y; in tegra_dc_setup_window()
368 h_size = window->src.w * bpp; in tegra_dc_setup_window()
369 v_size = window->src.h; in tegra_dc_setup_window()
371 if (window->reflect_x) in tegra_dc_setup_window()
372 h_offset += (window->src.w - 1) * bpp; in tegra_dc_setup_window()
374 if (window->reflect_y) in tegra_dc_setup_window()
375 v_offset += window->src.h - 1; in tegra_dc_setup_window()
387 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); in tegra_dc_setup_window()
388 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); in tegra_dc_setup_window()
393 h_dda = compute_initial_dda(window->src.x); in tegra_dc_setup_window()
394 v_dda = compute_initial_dda(window->src.y); in tegra_dc_setup_window()
402 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); in tegra_dc_setup_window()
405 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); in tegra_dc_setup_window()
406 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); in tegra_dc_setup_window()
407 value = window->stride[1] << 16 | window->stride[0]; in tegra_dc_setup_window()
410 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); in tegra_dc_setup_window()
416 if (dc->soc->supports_block_linear) { in tegra_dc_setup_window()
417 unsigned long height = window->tiling.value; in tegra_dc_setup_window()
419 switch (window->tiling.mode) { in tegra_dc_setup_window()
436 switch (window->tiling.mode) { in tegra_dc_setup_window()
449 * No need to handle this here because ->atomic_check in tegra_dc_setup_window()
472 } else if (window->bits_per_pixel < 24) { in tegra_dc_setup_window()
476 if (window->reflect_x) in tegra_dc_setup_window()
479 if (window->reflect_y) in tegra_dc_setup_window()
484 * Enable horizontal 6-tap filter and set filtering in tegra_dc_setup_window()
511 * Enable vertical 2-tap filter and set filtering in tegra_dc_setup_window()
514 for (i = 0, k = 128; i < 16; i++, k -= 8) in tegra_dc_setup_window()
522 if (dc->soc->has_legacy_blending) in tegra_dc_setup_window()
535 /* non-native formats */
613 unsigned int rotation = state->rotation; in tegra_plane_atomic_check()
614 struct tegra_bo_tiling *tiling = &plane_state->tiling; in tegra_plane_atomic_check()
616 struct tegra_dc *dc = to_tegra_dc(state->crtc); in tegra_plane_atomic_check()
620 if (!state->crtc) in tegra_plane_atomic_check()
623 err = tegra_plane_format(state->fb->format->format, in tegra_plane_atomic_check()
624 &plane_state->format, in tegra_plane_atomic_check()
625 &plane_state->swap); in tegra_plane_atomic_check()
635 if (dc->soc->has_legacy_blending) { in tegra_plane_atomic_check()
641 err = tegra_fb_get_tiling(state->fb, tiling); in tegra_plane_atomic_check()
645 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && in tegra_plane_atomic_check()
646 !dc->soc->supports_block_linear) { in tegra_plane_atomic_check()
648 return -EINVAL; in tegra_plane_atomic_check()
657 if (tegra_fb_is_bottom_up(state->fb)) in tegra_plane_atomic_check()
663 plane_state->reflect_x = true; in tegra_plane_atomic_check()
665 plane_state->reflect_x = false; in tegra_plane_atomic_check()
668 plane_state->reflect_y = true; in tegra_plane_atomic_check()
670 plane_state->reflect_y = false; in tegra_plane_atomic_check()
674 * error out if the user tries to display a framebuffer with such a in tegra_plane_atomic_check()
677 if (state->fb->format->num_planes > 2) { in tegra_plane_atomic_check()
678 if (state->fb->pitches[2] != state->fb->pitches[1]) { in tegra_plane_atomic_check()
679 DRM_ERROR("unsupported UV-plane configuration\n"); in tegra_plane_atomic_check()
680 return -EINVAL; in tegra_plane_atomic_check()
698 if (!old_state || !old_state->crtc) in tegra_plane_atomic_disable()
709 struct tegra_plane_state *state = to_tegra_plane_state(plane->state); in tegra_plane_atomic_update()
710 struct drm_framebuffer *fb = plane->state->fb; in tegra_plane_atomic_update()
716 if (!plane->state->crtc || !plane->state->fb) in tegra_plane_atomic_update()
719 if (!plane->state->visible) in tegra_plane_atomic_update()
723 window.src.x = plane->state->src.x1 >> 16; in tegra_plane_atomic_update()
724 window.src.y = plane->state->src.y1 >> 16; in tegra_plane_atomic_update()
725 window.src.w = drm_rect_width(&plane->state->src) >> 16; in tegra_plane_atomic_update()
726 window.src.h = drm_rect_height(&plane->state->src) >> 16; in tegra_plane_atomic_update()
727 window.dst.x = plane->state->dst.x1; in tegra_plane_atomic_update()
728 window.dst.y = plane->state->dst.y1; in tegra_plane_atomic_update()
729 window.dst.w = drm_rect_width(&plane->state->dst); in tegra_plane_atomic_update()
730 window.dst.h = drm_rect_height(&plane->state->dst); in tegra_plane_atomic_update()
731 window.bits_per_pixel = fb->format->cpp[0] * 8; in tegra_plane_atomic_update()
732 window.reflect_x = state->reflect_x; in tegra_plane_atomic_update()
733 window.reflect_y = state->reflect_y; in tegra_plane_atomic_update()
736 window.zpos = plane->state->normalized_zpos; in tegra_plane_atomic_update()
737 window.tiling = state->tiling; in tegra_plane_atomic_update()
738 window.format = state->format; in tegra_plane_atomic_update()
739 window.swap = state->swap; in tegra_plane_atomic_update()
741 for (i = 0; i < fb->format->num_planes; i++) { in tegra_plane_atomic_update()
742 window.base[i] = state->iova[i] + fb->offsets[i]; in tegra_plane_atomic_update()
747 * function, so it's safe to ignore the V-plane pitch here. in tegra_plane_atomic_update()
750 window.stride[i] = fb->pitches[i]; in tegra_plane_atomic_update()
778 return 1 << drm->mode_config.num_crtc; in tegra_plane_get_possible_crtcs()
794 return ERR_PTR(-ENOMEM); in tegra_primary_plane_create()
797 plane->offset = 0xa00; in tegra_primary_plane_create()
798 plane->index = 0; in tegra_primary_plane_create()
799 plane->dc = dc; in tegra_primary_plane_create()
801 num_formats = dc->soc->num_primary_formats; in tegra_primary_plane_create()
802 formats = dc->soc->primary_formats; in tegra_primary_plane_create()
803 modifiers = dc->soc->modifiers; in tegra_primary_plane_create()
805 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_primary_plane_create()
813 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); in tegra_primary_plane_create()
814 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); in tegra_primary_plane_create()
816 err = drm_plane_create_rotation_property(&plane->base, in tegra_primary_plane_create()
823 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_primary_plane_create()
826 return &plane->base; in tegra_primary_plane_create()
840 if (!state->crtc) in tegra_cursor_atomic_check()
844 if ((state->src_w >> 16 != state->crtc_w) || in tegra_cursor_atomic_check()
845 (state->src_h >> 16 != state->crtc_h)) in tegra_cursor_atomic_check()
846 return -EINVAL; in tegra_cursor_atomic_check()
849 if (state->src_w != state->src_h) in tegra_cursor_atomic_check()
850 return -EINVAL; in tegra_cursor_atomic_check()
852 if (state->crtc_w != 32 && state->crtc_w != 64 && in tegra_cursor_atomic_check()
853 state->crtc_w != 128 && state->crtc_w != 256) in tegra_cursor_atomic_check()
854 return -EINVAL; in tegra_cursor_atomic_check()
866 struct tegra_plane_state *state = to_tegra_plane_state(plane->state); in tegra_cursor_atomic_update()
867 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); in tegra_cursor_atomic_update()
871 if (!plane->state->crtc || !plane->state->fb) in tegra_cursor_atomic_update()
874 switch (plane->state->crtc_w) { in tegra_cursor_atomic_update()
893 plane->state->crtc_w, plane->state->crtc_h); in tegra_cursor_atomic_update()
897 value |= (state->iova[0] >> 10) & 0x3fffff; in tegra_cursor_atomic_update()
901 value = (state->iova[0] >> 32) & 0x3; in tegra_cursor_atomic_update()
920 value = (plane->state->crtc_y & 0x3fff) << 16 | in tegra_cursor_atomic_update()
921 (plane->state->crtc_x & 0x3fff); in tegra_cursor_atomic_update()
932 if (!old_state || !old_state->crtc) in tegra_cursor_atomic_disable()
935 dc = to_tegra_dc(old_state->crtc); in tegra_cursor_atomic_disable()
966 return ERR_PTR(-ENOMEM); in tegra_dc_cursor_plane_create()
973 * need to special-casing the cursor plane. in tegra_dc_cursor_plane_create()
975 plane->index = 6; in tegra_dc_cursor_plane_create()
976 plane->dc = dc; in tegra_dc_cursor_plane_create()
981 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_dc_cursor_plane_create()
990 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); in tegra_dc_cursor_plane_create()
991 drm_plane_create_zpos_immutable_property(&plane->base, 255); in tegra_dc_cursor_plane_create()
993 return &plane->base; in tegra_dc_cursor_plane_create()
1003 /* non-native formats */
1086 return ERR_PTR(-ENOMEM); in tegra_dc_overlay_plane_create()
1088 plane->offset = 0xa00 + 0x200 * index; in tegra_dc_overlay_plane_create()
1089 plane->index = index; in tegra_dc_overlay_plane_create()
1090 plane->dc = dc; in tegra_dc_overlay_plane_create()
1092 num_formats = dc->soc->num_overlay_formats; in tegra_dc_overlay_plane_create()
1093 formats = dc->soc->overlay_formats; in tegra_dc_overlay_plane_create()
1100 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, in tegra_dc_overlay_plane_create()
1109 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); in tegra_dc_overlay_plane_create()
1110 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); in tegra_dc_overlay_plane_create()
1112 err = drm_plane_create_rotation_property(&plane->base, in tegra_dc_overlay_plane_create()
1119 dev_err(dc->dev, "failed to create rotation property: %d\n", in tegra_dc_overlay_plane_create()
1122 return &plane->base; in tegra_dc_overlay_plane_create()
1131 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_add_shared_planes()
1132 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_add_shared_planes()
1134 if (wgrp->dc == dc->pipe) { in tegra_dc_add_shared_planes()
1135 for (j = 0; j < wgrp->num_windows; j++) { in tegra_dc_add_shared_planes()
1136 unsigned int index = wgrp->windows[j]; in tegra_dc_add_shared_planes()
1139 wgrp->index, in tegra_dc_add_shared_planes()
1149 plane->type = DRM_PLANE_TYPE_PRIMARY; in tegra_dc_add_shared_planes()
1171 if (dc->soc->supports_cursor) in tegra_dc_add_planes()
1182 while (i--) in tegra_dc_add_planes()
1202 if (crtc->state) in tegra_crtc_reset()
1203 tegra_crtc_atomic_destroy_state(crtc, crtc->state); in tegra_crtc_reset()
1205 __drm_atomic_helper_crtc_reset(crtc, &state->base); in tegra_crtc_reset()
1211 struct tegra_dc_state *state = to_dc_state(crtc->state); in tegra_crtc_atomic_duplicate_state()
1218 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); in tegra_crtc_atomic_duplicate_state()
1219 copy->clk = state->clk; in tegra_crtc_atomic_duplicate_state()
1220 copy->pclk = state->pclk; in tegra_crtc_atomic_duplicate_state()
1221 copy->div = state->div; in tegra_crtc_atomic_duplicate_state()
1222 copy->planes = state->planes; in tegra_crtc_atomic_duplicate_state()
1224 return ©->base; in tegra_crtc_atomic_duplicate_state()
1453 struct drm_info_node *node = s->private; in tegra_dc_show_regs()
1454 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_regs()
1458 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_regs()
1460 if (!dc->base.state->active) { in tegra_dc_show_regs()
1461 err = -EBUSY; in tegra_dc_show_regs()
1468 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, in tegra_dc_show_regs()
1473 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_regs()
1479 struct drm_info_node *node = s->private; in tegra_dc_show_crc()
1480 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_crc()
1484 drm_modeset_lock(&dc->base.mutex, NULL); in tegra_dc_show_crc()
1486 if (!dc->base.state->active) { in tegra_dc_show_crc()
1487 err = -EBUSY; in tegra_dc_show_crc()
1495 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1496 drm_crtc_wait_one_vblank(&dc->base); in tegra_dc_show_crc()
1504 drm_modeset_unlock(&dc->base.mutex); in tegra_dc_show_crc()
1510 struct drm_info_node *node = s->private; in tegra_dc_show_stats()
1511 struct tegra_dc *dc = node->info_ent->data; in tegra_dc_show_stats()
1513 seq_printf(s, "frames: %lu\n", dc->stats.frames); in tegra_dc_show_stats()
1514 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); in tegra_dc_show_stats()
1515 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); in tegra_dc_show_stats()
1516 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); in tegra_dc_show_stats()
1530 struct drm_minor *minor = crtc->dev->primary; in tegra_dc_late_register()
1535 root = crtc->debugfs_entry; in tegra_dc_late_register()
1540 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_dc_late_register()
1542 if (!dc->debugfs_files) in tegra_dc_late_register()
1543 return -ENOMEM; in tegra_dc_late_register()
1546 dc->debugfs_files[i].data = dc; in tegra_dc_late_register()
1548 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); in tegra_dc_late_register()
1556 struct drm_minor *minor = crtc->dev->primary; in tegra_dc_early_unregister()
1559 drm_debugfs_remove_files(dc->debugfs_files, count, minor); in tegra_dc_early_unregister()
1560 kfree(dc->debugfs_files); in tegra_dc_early_unregister()
1561 dc->debugfs_files = NULL; in tegra_dc_early_unregister()
1569 if (dc->syncpt && !dc->soc->has_nvdisplay) in tegra_dc_get_vblank_counter()
1570 return host1x_syncpt_read(dc->syncpt); in tegra_dc_get_vblank_counter()
1573 return (u32)drm_crtc_vblank_count(&dc->base); in tegra_dc_get_vblank_counter()
1619 if (!dc->soc->has_nvdisplay) { in tegra_dc_set_timings()
1626 value = ((mode->vsync_end - mode->vsync_start) << 16) | in tegra_dc_set_timings()
1627 ((mode->hsync_end - mode->hsync_start) << 0); in tegra_dc_set_timings()
1630 value = ((mode->vtotal - mode->vsync_end) << 16) | in tegra_dc_set_timings()
1631 ((mode->htotal - mode->hsync_end) << 0); in tegra_dc_set_timings()
1634 value = ((mode->vsync_start - mode->vdisplay) << 16) | in tegra_dc_set_timings()
1635 ((mode->hsync_start - mode->hdisplay) << 0); in tegra_dc_set_timings()
1638 value = (mode->vdisplay << 16) | mode->hdisplay; in tegra_dc_set_timings()
1645 * tegra_dc_state_setup_clock - check clock settings and store them in atomic
1647 * @dc: display controller
1649 * @clk: parent clock for display controller
1654 * 0 on success or a negative error-code on failure.
1663 if (!clk_has_parent(dc->clk, clk)) in tegra_dc_state_setup_clock()
1664 return -EINVAL; in tegra_dc_state_setup_clock()
1666 state->clk = clk; in tegra_dc_state_setup_clock()
1667 state->pclk = pclk; in tegra_dc_state_setup_clock()
1668 state->div = div; in tegra_dc_state_setup_clock()
1679 err = clk_set_parent(dc->clk, state->clk); in tegra_dc_commit_state()
1681 dev_err(dc->dev, "failed to set parent clock: %d\n", err); in tegra_dc_commit_state()
1685 * relevant to Tegra20 where only a single display PLL is available. in tegra_dc_commit_state()
1691 if (state->pclk > 0) { in tegra_dc_commit_state()
1692 err = clk_set_rate(state->clk, state->pclk); in tegra_dc_commit_state()
1694 dev_err(dc->dev, in tegra_dc_commit_state()
1696 state->pclk); in tegra_dc_commit_state()
1698 err = clk_set_rate(dc->clk, state->pclk); in tegra_dc_commit_state()
1700 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", in tegra_dc_commit_state()
1701 dc->clk, state->pclk, err); in tegra_dc_commit_state()
1704 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), in tegra_dc_commit_state()
1705 state->div); in tegra_dc_commit_state()
1706 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); in tegra_dc_commit_state()
1708 if (!dc->soc->has_nvdisplay) { in tegra_dc_commit_state()
1709 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; in tegra_dc_commit_state()
1718 /* stop the display controller */ in tegra_dc_stop()
1746 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); in tegra_dc_wait_idle()
1747 return -ETIMEDOUT; in tegra_dc_wait_idle()
1769 * these bits has the side-effect of stopping the display controller. in tegra_crtc_atomic_disable()
1771 * time the encoder is disabled before the display controller, so the in tegra_crtc_atomic_disable()
1775 * Given the close coupling between the RGB encoder and the display in tegra_crtc_atomic_disable()
1779 * XXX: Perhaps given that the display controller is switched off at in tegra_crtc_atomic_disable()
1783 if (dc->rgb) { in tegra_crtc_atomic_disable()
1790 tegra_dc_stats_reset(&dc->stats); in tegra_crtc_atomic_disable()
1793 spin_lock_irq(&crtc->dev->event_lock); in tegra_crtc_atomic_disable()
1795 if (crtc->state->event) { in tegra_crtc_atomic_disable()
1796 drm_crtc_send_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_disable()
1797 crtc->state->event = NULL; in tegra_crtc_atomic_disable()
1800 spin_unlock_irq(&crtc->dev->event_lock); in tegra_crtc_atomic_disable()
1802 err = host1x_client_suspend(&dc->client); in tegra_crtc_atomic_disable()
1804 dev_err(dc->dev, "failed to suspend: %d\n", err); in tegra_crtc_atomic_disable()
1810 struct drm_display_mode *mode = &crtc->state->adjusted_mode; in tegra_crtc_atomic_enable()
1811 struct tegra_dc_state *state = to_dc_state(crtc->state); in tegra_crtc_atomic_enable()
1816 err = host1x_client_resume(&dc->client); in tegra_crtc_atomic_enable()
1818 dev_err(dc->dev, "failed to resume: %d\n", err); in tegra_crtc_atomic_enable()
1822 /* initialize display controller */ in tegra_crtc_atomic_enable()
1823 if (dc->syncpt) { in tegra_crtc_atomic_enable()
1824 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; in tegra_crtc_atomic_enable()
1826 if (dc->soc->has_nvdisplay) in tegra_crtc_atomic_enable()
1838 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1885 if (dc->soc->supports_background_color) in tegra_crtc_atomic_enable()
1893 /* program display mode */ in tegra_crtc_atomic_enable()
1897 if (dc->soc->supports_interlacing) { in tegra_crtc_atomic_enable()
1908 if (!dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1915 /* enable underflow reporting and display red for missing pixels */ in tegra_crtc_atomic_enable()
1916 if (dc->soc->has_nvdisplay) { in tegra_crtc_atomic_enable()
1931 if (crtc->state->event) { in tegra_crtc_atomic_begin()
1932 spin_lock_irqsave(&crtc->dev->event_lock, flags); in tegra_crtc_atomic_begin()
1935 drm_crtc_send_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_begin()
1937 drm_crtc_arm_vblank_event(crtc, crtc->state->event); in tegra_crtc_atomic_begin()
1939 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); in tegra_crtc_atomic_begin()
1941 crtc->state->event = NULL; in tegra_crtc_atomic_begin()
1948 struct tegra_dc_state *state = to_dc_state(crtc->state); in tegra_crtc_atomic_flush()
1952 value = state->planes << 8 | GENERAL_UPDATE; in tegra_crtc_atomic_flush()
1956 value = state->planes | GENERAL_ACT_REQ; in tegra_crtc_atomic_flush()
1978 dev_dbg(dc->dev, "%s(): frame end\n", __func__); in tegra_dc_irq()
1980 dc->stats.frames++; in tegra_dc_irq()
1985 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); in tegra_dc_irq()
1987 drm_crtc_handle_vblank(&dc->base); in tegra_dc_irq()
1988 dc->stats.vblank++; in tegra_dc_irq()
1993 dev_dbg(dc->dev, "%s(): underflow\n", __func__); in tegra_dc_irq()
1995 dc->stats.underflow++; in tegra_dc_irq()
2000 dev_dbg(dc->dev, "%s(): overflow\n", __func__); in tegra_dc_irq()
2002 dc->stats.overflow++; in tegra_dc_irq()
2006 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); in tegra_dc_irq()
2007 dc->stats.underflow++; in tegra_dc_irq()
2017 if (!dc->soc->wgrps) in tegra_dc_has_window_groups()
2020 for (i = 0; i < dc->soc->num_wgrps; i++) { in tegra_dc_has_window_groups()
2021 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; in tegra_dc_has_window_groups()
2023 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) in tegra_dc_has_window_groups()
2032 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_dc_init()
2035 struct tegra_drm *tegra = drm->dev_private; in tegra_dc_init()
2049 * Set the display hub as the host1x client parent for the display in tegra_dc_init()
2051 * ensures the display hub is always powered when any of the display in tegra_dc_init()
2054 if (dc->soc->has_nvdisplay) in tegra_dc_init()
2055 client->parent = &tegra->hub->client; in tegra_dc_init()
2057 dc->syncpt = host1x_syncpt_request(client, flags); in tegra_dc_init()
2058 if (!dc->syncpt) in tegra_dc_init()
2059 dev_warn(dc->dev, "failed to allocate syncpoint\n"); in tegra_dc_init()
2062 if (err < 0 && err != -ENODEV) { in tegra_dc_init()
2063 dev_err(client->dev, "failed to attach to domain: %d\n", err); in tegra_dc_init()
2067 if (dc->soc->wgrps) in tegra_dc_init()
2077 if (dc->soc->supports_cursor) { in tegra_dc_init()
2092 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, in tegra_dc_init()
2097 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); in tegra_dc_init()
2100 * Keep track of the minimum pitch alignment across all display in tegra_dc_init()
2103 if (dc->soc->pitch_align > tegra->pitch_align) in tegra_dc_init()
2104 tegra->pitch_align = dc->soc->pitch_align; in tegra_dc_init()
2107 if (err < 0 && err != -ENODEV) { in tegra_dc_init()
2108 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); in tegra_dc_init()
2112 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, in tegra_dc_init()
2113 dev_name(dc->dev), dc); in tegra_dc_init()
2115 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, in tegra_dc_init()
2124 client->dev->dma_parms = client->host->dma_parms; in tegra_dc_init()
2136 host1x_syncpt_free(dc->syncpt); in tegra_dc_init()
2150 client->dev->dma_parms = NULL; in tegra_dc_exit()
2152 devm_free_irq(dc->dev, dc->irq, dc); in tegra_dc_exit()
2156 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); in tegra_dc_exit()
2161 host1x_syncpt_free(dc->syncpt); in tegra_dc_exit()
2169 struct device *dev = client->dev; in tegra_dc_runtime_suspend()
2172 err = reset_control_assert(dc->rst); in tegra_dc_runtime_suspend()
2178 if (dc->soc->has_powergate) in tegra_dc_runtime_suspend()
2179 tegra_powergate_power_off(dc->powergate); in tegra_dc_runtime_suspend()
2181 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_suspend()
2190 struct device *dev = client->dev; in tegra_dc_runtime_resume()
2199 if (dc->soc->has_powergate) { in tegra_dc_runtime_resume()
2200 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, in tegra_dc_runtime_resume()
2201 dc->rst); in tegra_dc_runtime_resume()
2207 err = clk_prepare_enable(dc->clk); in tegra_dc_runtime_resume()
2213 err = reset_control_deassert(dc->rst); in tegra_dc_runtime_resume()
2223 clk_disable_unprepare(dc->clk); in tegra_dc_runtime_resume()
2429 .compatible = "nvidia,tegra194-dc",
2432 .compatible = "nvidia,tegra186-dc",
2435 .compatible = "nvidia,tegra210-dc",
2438 .compatible = "nvidia,tegra124-dc",
2441 .compatible = "nvidia,tegra114-dc",
2444 .compatible = "nvidia,tegra30-dc",
2447 .compatible = "nvidia,tegra20-dc",
2461 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); in tegra_dc_parse_dt()
2463 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); in tegra_dc_parse_dt()
2468 * display controller's node within the device tree. Assuming in tegra_dc_parse_dt()
2475 * cases where only a single display controller is used. in tegra_dc_parse_dt()
2478 if (np == dc->dev->of_node) { in tegra_dc_parse_dt()
2487 dc->pipe = value; in tegra_dc_parse_dt()
2497 return dc->pipe == pipe; in tegra_dc_match_by_pipe()
2507 if (dc->soc->coupled_pm && dc->pipe == 1) { in tegra_dc_couple()
2511 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, in tegra_dc_couple()
2514 return -EPROBE_DEFER; in tegra_dc_couple()
2517 dc->client.parent = &parent->client; in tegra_dc_couple()
2519 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); in tegra_dc_couple()
2530 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); in tegra_dc_probe()
2532 return -ENOMEM; in tegra_dc_probe()
2534 dc->soc = of_device_get_match_data(&pdev->dev); in tegra_dc_probe()
2536 INIT_LIST_HEAD(&dc->list); in tegra_dc_probe()
2537 dc->dev = &pdev->dev; in tegra_dc_probe()
2547 dc->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dc_probe()
2548 if (IS_ERR(dc->clk)) { in tegra_dc_probe()
2549 dev_err(&pdev->dev, "failed to get clock\n"); in tegra_dc_probe()
2550 return PTR_ERR(dc->clk); in tegra_dc_probe()
2553 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); in tegra_dc_probe()
2554 if (IS_ERR(dc->rst)) { in tegra_dc_probe()
2555 dev_err(&pdev->dev, "failed to get reset\n"); in tegra_dc_probe()
2556 return PTR_ERR(dc->rst); in tegra_dc_probe()
2560 err = clk_prepare_enable(dc->clk); in tegra_dc_probe()
2566 err = reset_control_assert(dc->rst); in tegra_dc_probe()
2568 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
2574 clk_disable_unprepare(dc->clk); in tegra_dc_probe()
2576 if (dc->soc->has_powergate) { in tegra_dc_probe()
2577 if (dc->pipe == 0) in tegra_dc_probe()
2578 dc->powergate = TEGRA_POWERGATE_DIS; in tegra_dc_probe()
2580 dc->powergate = TEGRA_POWERGATE_DISB; in tegra_dc_probe()
2582 tegra_powergate_power_off(dc->powergate); in tegra_dc_probe()
2585 dc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_dc_probe()
2586 if (IS_ERR(dc->regs)) in tegra_dc_probe()
2587 return PTR_ERR(dc->regs); in tegra_dc_probe()
2589 dc->irq = platform_get_irq(pdev, 0); in tegra_dc_probe()
2590 if (dc->irq < 0) in tegra_dc_probe()
2591 return -ENXIO; in tegra_dc_probe()
2594 if (err < 0 && err != -ENODEV) { in tegra_dc_probe()
2597 if (err == -EPROBE_DEFER) in tegra_dc_probe()
2600 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n", in tegra_dc_probe()
2606 pm_runtime_enable(&pdev->dev); in tegra_dc_probe()
2608 INIT_LIST_HEAD(&dc->client.list); in tegra_dc_probe()
2609 dc->client.ops = &dc_client_ops; in tegra_dc_probe()
2610 dc->client.dev = &pdev->dev; in tegra_dc_probe()
2612 err = host1x_client_register(&dc->client); in tegra_dc_probe()
2614 dev_err(&pdev->dev, "failed to register host1x client: %d\n", in tegra_dc_probe()
2622 pm_runtime_disable(&pdev->dev); in tegra_dc_probe()
2633 err = host1x_client_unregister(&dc->client); in tegra_dc_remove()
2635 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", in tegra_dc_remove()
2642 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); in tegra_dc_remove()
2646 pm_runtime_disable(&pdev->dev); in tegra_dc_remove()
2653 .name = "tegra-dc",