Lines Matching +full:dpaux +full:- +full:io
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/io.h>
12 #include <linux/pinctrl/pinconf-generic.h>
25 #include "dpaux.h"
75 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, in tegra_dpaux_readl() argument
78 u32 value = readl(dpaux->regs + (offset << 2)); in tegra_dpaux_readl()
80 trace_dpaux_readl(dpaux->dev, offset, value); in tegra_dpaux_readl()
85 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, in tegra_dpaux_writel() argument
88 trace_dpaux_writel(dpaux->dev, offset, value); in tegra_dpaux_writel()
89 writel(value, dpaux->regs + (offset << 2)); in tegra_dpaux_writel()
92 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer, in tegra_dpaux_write_fifo() argument
98 size_t num = min_t(size_t, size - i * 4, 4); in tegra_dpaux_write_fifo()
104 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i)); in tegra_dpaux_write_fifo()
108 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer, in tegra_dpaux_read_fifo() argument
114 size_t num = min_t(size_t, size - i * 4, 4); in tegra_dpaux_read_fifo()
117 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i)); in tegra_dpaux_read_fifo()
128 struct tegra_dpaux *dpaux = to_dpaux(aux); in tegra_dpaux_transfer() local
135 if (msg->size > 16) in tegra_dpaux_transfer()
136 return -EINVAL; in tegra_dpaux_transfer()
139 * Allow zero-sized messages only for I2C, in which case they specify in tegra_dpaux_transfer()
140 * address-only transactions. in tegra_dpaux_transfer()
142 if (msg->size < 1) { in tegra_dpaux_transfer()
143 switch (msg->request & ~DP_AUX_I2C_MOT) { in tegra_dpaux_transfer()
151 return -EINVAL; in tegra_dpaux_transfer()
154 /* For non-zero-sized messages, set the CMDLEN field. */ in tegra_dpaux_transfer()
155 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1); in tegra_dpaux_transfer()
158 switch (msg->request & ~DP_AUX_I2C_MOT) { in tegra_dpaux_transfer()
160 if (msg->request & DP_AUX_I2C_MOT) in tegra_dpaux_transfer()
168 if (msg->request & DP_AUX_I2C_MOT) in tegra_dpaux_transfer()
176 if (msg->request & DP_AUX_I2C_MOT) in tegra_dpaux_transfer()
192 return -EINVAL; in tegra_dpaux_transfer()
195 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR); in tegra_dpaux_transfer()
196 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); in tegra_dpaux_transfer()
198 if ((msg->request & DP_AUX_I2C_READ) == 0) { in tegra_dpaux_transfer()
199 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size); in tegra_dpaux_transfer()
200 ret = msg->size; in tegra_dpaux_transfer()
204 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL); in tegra_dpaux_transfer()
206 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); in tegra_dpaux_transfer()
208 status = wait_for_completion_timeout(&dpaux->complete, timeout); in tegra_dpaux_transfer()
210 return -ETIMEDOUT; in tegra_dpaux_transfer()
213 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); in tegra_dpaux_transfer()
214 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT); in tegra_dpaux_transfer()
217 return -ETIMEDOUT; in tegra_dpaux_transfer()
222 return -EIO; in tegra_dpaux_transfer()
246 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) { in tegra_dpaux_transfer()
247 if (msg->request & DP_AUX_I2C_READ) { in tegra_dpaux_transfer()
253 * an -EBUSY return value, simply reuse that instead. in tegra_dpaux_transfer()
255 if (count != msg->size) { in tegra_dpaux_transfer()
256 ret = -EBUSY; in tegra_dpaux_transfer()
260 tegra_dpaux_read_fifo(dpaux, msg->buffer, count); in tegra_dpaux_transfer()
265 msg->reply = reply; in tegra_dpaux_transfer()
273 struct tegra_dpaux *dpaux = work_to_dpaux(work); in tegra_dpaux_hotplug() local
275 if (dpaux->output) in tegra_dpaux_hotplug()
276 drm_helper_hpd_irq_event(dpaux->output->connector.dev); in tegra_dpaux_hotplug()
281 struct tegra_dpaux *dpaux = data; in tegra_dpaux_irq() local
286 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX); in tegra_dpaux_irq()
287 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); in tegra_dpaux_irq()
290 schedule_work(&dpaux->work); in tegra_dpaux_irq()
297 complete(&dpaux->complete); in tegra_dpaux_irq()
308 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux) in tegra_dpaux_pad_power_down() argument
310 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); in tegra_dpaux_pad_power_down()
314 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); in tegra_dpaux_pad_power_down()
317 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux) in tegra_dpaux_pad_power_up() argument
319 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); in tegra_dpaux_pad_power_up()
323 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); in tegra_dpaux_pad_power_up()
326 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function) in tegra_dpaux_pad_config() argument
332 value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) | in tegra_dpaux_pad_config()
333 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) | in tegra_dpaux_pad_config()
334 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) | in tegra_dpaux_pad_config()
342 DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) | in tegra_dpaux_pad_config()
343 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) | in tegra_dpaux_pad_config()
344 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) | in tegra_dpaux_pad_config()
349 tegra_dpaux_pad_power_down(dpaux); in tegra_dpaux_pad_config()
353 return -ENOTSUPP; in tegra_dpaux_pad_config()
356 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL); in tegra_dpaux_pad_config()
357 tegra_dpaux_pad_power_up(dpaux); in tegra_dpaux_pad_config()
371 "dpaux-io",
434 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl); in tegra_dpaux_set_mux() local
436 return tegra_dpaux_pad_config(dpaux, function); in tegra_dpaux_set_mux()
449 struct tegra_dpaux *dpaux; in tegra_dpaux_probe() local
454 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL); in tegra_dpaux_probe()
455 if (!dpaux) in tegra_dpaux_probe()
456 return -ENOMEM; in tegra_dpaux_probe()
458 dpaux->soc = of_device_get_match_data(&pdev->dev); in tegra_dpaux_probe()
459 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug); in tegra_dpaux_probe()
460 init_completion(&dpaux->complete); in tegra_dpaux_probe()
461 INIT_LIST_HEAD(&dpaux->list); in tegra_dpaux_probe()
462 dpaux->dev = &pdev->dev; in tegra_dpaux_probe()
465 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_dpaux_probe()
466 if (IS_ERR(dpaux->regs)) in tegra_dpaux_probe()
467 return PTR_ERR(dpaux->regs); in tegra_dpaux_probe()
469 dpaux->irq = platform_get_irq(pdev, 0); in tegra_dpaux_probe()
470 if (dpaux->irq < 0) in tegra_dpaux_probe()
471 return dpaux->irq; in tegra_dpaux_probe()
473 if (!pdev->dev.pm_domain) { in tegra_dpaux_probe()
474 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); in tegra_dpaux_probe()
475 if (IS_ERR(dpaux->rst)) { in tegra_dpaux_probe()
476 dev_err(&pdev->dev, in tegra_dpaux_probe()
478 PTR_ERR(dpaux->rst)); in tegra_dpaux_probe()
479 return PTR_ERR(dpaux->rst); in tegra_dpaux_probe()
483 dpaux->clk = devm_clk_get(&pdev->dev, NULL); in tegra_dpaux_probe()
484 if (IS_ERR(dpaux->clk)) { in tegra_dpaux_probe()
485 dev_err(&pdev->dev, "failed to get module clock: %ld\n", in tegra_dpaux_probe()
486 PTR_ERR(dpaux->clk)); in tegra_dpaux_probe()
487 return PTR_ERR(dpaux->clk); in tegra_dpaux_probe()
490 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_dpaux_probe()
491 if (IS_ERR(dpaux->clk_parent)) { in tegra_dpaux_probe()
492 dev_err(&pdev->dev, "failed to get parent clock: %ld\n", in tegra_dpaux_probe()
493 PTR_ERR(dpaux->clk_parent)); in tegra_dpaux_probe()
494 return PTR_ERR(dpaux->clk_parent); in tegra_dpaux_probe()
497 err = clk_set_rate(dpaux->clk_parent, 270000000); in tegra_dpaux_probe()
499 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n", in tegra_dpaux_probe()
504 dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd"); in tegra_dpaux_probe()
505 if (IS_ERR(dpaux->vdd)) { in tegra_dpaux_probe()
506 if (PTR_ERR(dpaux->vdd) != -ENODEV) { in tegra_dpaux_probe()
507 if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER) in tegra_dpaux_probe()
508 dev_err(&pdev->dev, in tegra_dpaux_probe()
510 PTR_ERR(dpaux->vdd)); in tegra_dpaux_probe()
512 return PTR_ERR(dpaux->vdd); in tegra_dpaux_probe()
515 dpaux->vdd = NULL; in tegra_dpaux_probe()
518 platform_set_drvdata(pdev, dpaux); in tegra_dpaux_probe()
519 pm_runtime_enable(&pdev->dev); in tegra_dpaux_probe()
520 pm_runtime_get_sync(&pdev->dev); in tegra_dpaux_probe()
522 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, in tegra_dpaux_probe()
523 dev_name(dpaux->dev), dpaux); in tegra_dpaux_probe()
525 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n", in tegra_dpaux_probe()
526 dpaux->irq, err); in tegra_dpaux_probe()
530 disable_irq(dpaux->irq); in tegra_dpaux_probe()
532 dpaux->aux.transfer = tegra_dpaux_transfer; in tegra_dpaux_probe()
533 dpaux->aux.dev = &pdev->dev; in tegra_dpaux_probe()
535 err = drm_dp_aux_register(&dpaux->aux); in tegra_dpaux_probe()
540 * Assume that by default the DPAUX/I2C pads will be used for HDMI, in tegra_dpaux_probe()
543 * The DPAUX code paths reconfigure the pads in AUX mode, but there in tegra_dpaux_probe()
547 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C); in tegra_dpaux_probe()
552 dpaux->desc.name = dev_name(&pdev->dev); in tegra_dpaux_probe()
553 dpaux->desc.pins = tegra_dpaux_pins; in tegra_dpaux_probe()
554 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins); in tegra_dpaux_probe()
555 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops; in tegra_dpaux_probe()
556 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops; in tegra_dpaux_probe()
557 dpaux->desc.owner = THIS_MODULE; in tegra_dpaux_probe()
559 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux); in tegra_dpaux_probe()
560 if (IS_ERR(dpaux->pinctrl)) { in tegra_dpaux_probe()
561 dev_err(&pdev->dev, "failed to register pincontrol\n"); in tegra_dpaux_probe()
562 return PTR_ERR(dpaux->pinctrl); in tegra_dpaux_probe()
568 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX); in tegra_dpaux_probe()
569 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); in tegra_dpaux_probe()
572 list_add_tail(&dpaux->list, &dpaux_list); in tegra_dpaux_probe()
580 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev); in tegra_dpaux_remove() local
582 cancel_work_sync(&dpaux->work); in tegra_dpaux_remove()
585 tegra_dpaux_pad_power_down(dpaux); in tegra_dpaux_remove()
587 pm_runtime_put_sync(&pdev->dev); in tegra_dpaux_remove()
588 pm_runtime_disable(&pdev->dev); in tegra_dpaux_remove()
590 drm_dp_aux_unregister(&dpaux->aux); in tegra_dpaux_remove()
593 list_del(&dpaux->list); in tegra_dpaux_remove()
602 struct tegra_dpaux *dpaux = dev_get_drvdata(dev); in tegra_dpaux_suspend() local
605 if (dpaux->rst) { in tegra_dpaux_suspend()
606 err = reset_control_assert(dpaux->rst); in tegra_dpaux_suspend()
615 clk_disable_unprepare(dpaux->clk_parent); in tegra_dpaux_suspend()
616 clk_disable_unprepare(dpaux->clk); in tegra_dpaux_suspend()
623 struct tegra_dpaux *dpaux = dev_get_drvdata(dev); in tegra_dpaux_resume() local
626 err = clk_prepare_enable(dpaux->clk); in tegra_dpaux_resume()
632 err = clk_prepare_enable(dpaux->clk_parent); in tegra_dpaux_resume()
640 if (dpaux->rst) { in tegra_dpaux_resume()
641 err = reset_control_deassert(dpaux->rst); in tegra_dpaux_resume()
653 clk_disable_unprepare(dpaux->clk_parent); in tegra_dpaux_resume()
655 clk_disable_unprepare(dpaux->clk); in tegra_dpaux_resume()
683 { .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc },
684 { .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc },
685 { .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc },
686 { .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc },
693 .name = "tegra-dpaux",
703 struct tegra_dpaux *dpaux; in drm_dp_aux_find_by_of_node() local
707 list_for_each_entry(dpaux, &dpaux_list, list) in drm_dp_aux_find_by_of_node()
708 if (np == dpaux->dev->of_node) { in drm_dp_aux_find_by_of_node()
710 return &dpaux->aux; in drm_dp_aux_find_by_of_node()
720 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_attach() local
724 output->connector.polled = DRM_CONNECTOR_POLL_HPD; in drm_dp_aux_attach()
725 dpaux->output = output; in drm_dp_aux_attach()
727 if (output->panel) { in drm_dp_aux_attach()
730 if (dpaux->vdd) { in drm_dp_aux_attach()
731 err = regulator_enable(dpaux->vdd); in drm_dp_aux_attach()
748 return -ETIMEDOUT; in drm_dp_aux_attach()
751 enable_irq(dpaux->irq); in drm_dp_aux_attach()
757 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_detach() local
761 disable_irq(dpaux->irq); in drm_dp_aux_detach()
763 if (dpaux->output->panel) { in drm_dp_aux_detach()
766 if (dpaux->vdd) { in drm_dp_aux_detach()
767 err = regulator_disable(dpaux->vdd); in drm_dp_aux_detach()
784 return -ETIMEDOUT; in drm_dp_aux_detach()
786 dpaux->output = NULL; in drm_dp_aux_detach()
794 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_detect() local
797 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); in drm_dp_aux_detect()
807 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_enable() local
809 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX); in drm_dp_aux_enable()
814 struct tegra_dpaux *dpaux = to_dpaux(aux); in drm_dp_aux_disable() local
816 tegra_dpaux_pad_power_down(dpaux); in drm_dp_aux_disable()