Lines Matching +full:tegra194 +full:- +full:display
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved.
64 struct drm_device *drm = old_state->dev; in tegra_atomic_commit_tail()
65 struct tegra_drm *tegra = drm->dev_private; in tegra_atomic_commit_tail()
67 if (tegra->hub) { in tegra_atomic_commit_tail()
91 return -ENOMEM; in tegra_drm_open()
93 idr_init_base(&fpriv->contexts, 1); in tegra_drm_open()
94 mutex_init(&fpriv->lock); in tegra_drm_open()
95 filp->driver_priv = fpriv; in tegra_drm_open()
102 context->client->ops->close_channel(context); in tegra_drm_context_free()
117 return &bo->base; in host1x_bo_lookup()
128 err = get_user(cmdbuf, &src->cmdbuf.handle); in host1x_reloc_copy_from_user()
132 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); in host1x_reloc_copy_from_user()
136 err = get_user(target, &src->target.handle); in host1x_reloc_copy_from_user()
140 err = get_user(dest->target.offset, &src->target.offset); in host1x_reloc_copy_from_user()
144 err = get_user(dest->shift, &src->shift); in host1x_reloc_copy_from_user()
148 dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE; in host1x_reloc_copy_from_user()
150 dest->cmdbuf.bo = host1x_bo_lookup(file, cmdbuf); in host1x_reloc_copy_from_user()
151 if (!dest->cmdbuf.bo) in host1x_reloc_copy_from_user()
152 return -ENOENT; in host1x_reloc_copy_from_user()
154 dest->target.bo = host1x_bo_lookup(file, target); in host1x_reloc_copy_from_user()
155 if (!dest->target.bo) in host1x_reloc_copy_from_user()
156 return -ENOENT; in host1x_reloc_copy_from_user()
165 struct host1x_client *client = &context->client->base; in tegra_drm_submit()
166 unsigned int num_cmdbufs = args->num_cmdbufs; in tegra_drm_submit()
167 unsigned int num_relocs = args->num_relocs; in tegra_drm_submit()
172 struct host1x *host1x = dev_get_drvdata(drm->dev->parent); in tegra_drm_submit()
179 user_cmdbufs = u64_to_user_ptr(args->cmdbufs); in tegra_drm_submit()
180 user_relocs = u64_to_user_ptr(args->relocs); in tegra_drm_submit()
181 user_syncpt = u64_to_user_ptr(args->syncpts); in tegra_drm_submit()
184 if (args->num_syncpts != 1) in tegra_drm_submit()
185 return -EINVAL; in tegra_drm_submit()
188 if (args->num_waitchks != 0) in tegra_drm_submit()
189 return -EINVAL; in tegra_drm_submit()
191 job = host1x_job_alloc(context->channel, args->num_cmdbufs, in tegra_drm_submit()
192 args->num_relocs); in tegra_drm_submit()
194 return -ENOMEM; in tegra_drm_submit()
196 job->num_relocs = args->num_relocs; in tegra_drm_submit()
197 job->client = client; in tegra_drm_submit()
198 job->class = client->class; in tegra_drm_submit()
199 job->serialize = true; in tegra_drm_submit()
209 err = -ENOMEM; in tegra_drm_submit()
223 err = -EFAULT; in tegra_drm_submit()
232 err = -EINVAL; in tegra_drm_submit()
238 err = -ENOENT; in tegra_drm_submit()
244 refs[num_refs++] = &obj->gem; in tegra_drm_submit()
247 * Gather buffer base address must be 4-bytes aligned, in tegra_drm_submit()
251 if (offset & 3 || offset > obj->gem.size) { in tegra_drm_submit()
252 err = -EINVAL; in tegra_drm_submit()
257 num_cmdbufs--; in tegra_drm_submit()
262 while (num_relocs--) { in tegra_drm_submit()
266 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs], in tegra_drm_submit()
272 reloc = &job->relocs[num_relocs]; in tegra_drm_submit()
273 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); in tegra_drm_submit()
274 refs[num_refs++] = &obj->gem; in tegra_drm_submit()
281 if (reloc->cmdbuf.offset & 3 || in tegra_drm_submit()
282 reloc->cmdbuf.offset >= obj->gem.size) { in tegra_drm_submit()
283 err = -EINVAL; in tegra_drm_submit()
287 obj = host1x_to_tegra_bo(reloc->target.bo); in tegra_drm_submit()
288 refs[num_refs++] = &obj->gem; in tegra_drm_submit()
290 if (reloc->target.offset >= obj->gem.size) { in tegra_drm_submit()
291 err = -EINVAL; in tegra_drm_submit()
297 err = -EFAULT; in tegra_drm_submit()
304 err = -ENOENT; in tegra_drm_submit()
308 job->is_addr_reg = context->client->ops->is_addr_reg; in tegra_drm_submit()
309 job->is_valid_class = context->client->ops->is_valid_class; in tegra_drm_submit()
310 job->syncpt_incrs = syncpt.incrs; in tegra_drm_submit()
311 job->syncpt_id = syncpt.id; in tegra_drm_submit()
312 job->timeout = 10000; in tegra_drm_submit()
314 if (args->timeout && args->timeout < 10000) in tegra_drm_submit()
315 job->timeout = args->timeout; in tegra_drm_submit()
317 err = host1x_job_pin(job, context->client->base.dev); in tegra_drm_submit()
327 args->fence = job->syncpt_end; in tegra_drm_submit()
330 while (num_refs--) in tegra_drm_submit()
348 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, in tegra_gem_create()
349 &args->handle); in tegra_gem_create()
363 gem = drm_gem_object_lookup(file, args->handle); in tegra_gem_mmap()
365 return -EINVAL; in tegra_gem_mmap()
369 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); in tegra_gem_mmap()
379 struct host1x *host = dev_get_drvdata(drm->dev->parent); in tegra_syncpt_read()
383 sp = host1x_syncpt_get(host, args->id); in tegra_syncpt_read()
385 return -EINVAL; in tegra_syncpt_read()
387 args->value = host1x_syncpt_read_min(sp); in tegra_syncpt_read()
394 struct host1x *host1x = dev_get_drvdata(drm->dev->parent); in tegra_syncpt_incr()
398 sp = host1x_syncpt_get(host1x, args->id); in tegra_syncpt_incr()
400 return -EINVAL; in tegra_syncpt_incr()
408 struct host1x *host1x = dev_get_drvdata(drm->dev->parent); in tegra_syncpt_wait()
412 sp = host1x_syncpt_get(host1x, args->id); in tegra_syncpt_wait()
414 return -EINVAL; in tegra_syncpt_wait()
416 return host1x_syncpt_wait(sp, args->thresh, in tegra_syncpt_wait()
417 msecs_to_jiffies(args->timeout), in tegra_syncpt_wait()
418 &args->value); in tegra_syncpt_wait()
427 err = client->ops->open_channel(client, context); in tegra_client_open()
431 err = idr_alloc(&fpriv->contexts, context, 1, 0, GFP_KERNEL); in tegra_client_open()
433 client->ops->close_channel(context); in tegra_client_open()
437 context->client = client; in tegra_client_open()
438 context->id = err; in tegra_client_open()
446 struct tegra_drm_file *fpriv = file->driver_priv; in tegra_open_channel()
447 struct tegra_drm *tegra = drm->dev_private; in tegra_open_channel()
451 int err = -ENODEV; in tegra_open_channel()
455 return -ENOMEM; in tegra_open_channel()
457 mutex_lock(&fpriv->lock); in tegra_open_channel()
459 list_for_each_entry(client, &tegra->clients, list) in tegra_open_channel()
460 if (client->base.class == args->client) { in tegra_open_channel()
465 args->context = context->id; in tegra_open_channel()
472 mutex_unlock(&fpriv->lock); in tegra_open_channel()
479 struct tegra_drm_file *fpriv = file->driver_priv; in tegra_close_channel()
484 mutex_lock(&fpriv->lock); in tegra_close_channel()
486 context = idr_find(&fpriv->contexts, args->context); in tegra_close_channel()
488 err = -EINVAL; in tegra_close_channel()
492 idr_remove(&fpriv->contexts, context->id); in tegra_close_channel()
496 mutex_unlock(&fpriv->lock); in tegra_close_channel()
503 struct tegra_drm_file *fpriv = file->driver_priv; in tegra_get_syncpt()
509 mutex_lock(&fpriv->lock); in tegra_get_syncpt()
511 context = idr_find(&fpriv->contexts, args->context); in tegra_get_syncpt()
513 err = -ENODEV; in tegra_get_syncpt()
517 if (args->index >= context->client->base.num_syncpts) { in tegra_get_syncpt()
518 err = -EINVAL; in tegra_get_syncpt()
522 syncpt = context->client->base.syncpts[args->index]; in tegra_get_syncpt()
523 args->id = host1x_syncpt_id(syncpt); in tegra_get_syncpt()
526 mutex_unlock(&fpriv->lock); in tegra_get_syncpt()
533 struct tegra_drm_file *fpriv = file->driver_priv; in tegra_submit()
538 mutex_lock(&fpriv->lock); in tegra_submit()
540 context = idr_find(&fpriv->contexts, args->context); in tegra_submit()
542 err = -ENODEV; in tegra_submit()
546 err = context->client->ops->submit(context, args, drm, file); in tegra_submit()
549 mutex_unlock(&fpriv->lock); in tegra_submit()
556 struct tegra_drm_file *fpriv = file->driver_priv; in tegra_get_syncpt_base()
563 mutex_lock(&fpriv->lock); in tegra_get_syncpt_base()
565 context = idr_find(&fpriv->contexts, args->context); in tegra_get_syncpt_base()
567 err = -ENODEV; in tegra_get_syncpt_base()
571 if (args->syncpt >= context->client->base.num_syncpts) { in tegra_get_syncpt_base()
572 err = -EINVAL; in tegra_get_syncpt_base()
576 syncpt = context->client->base.syncpts[args->syncpt]; in tegra_get_syncpt_base()
580 err = -ENXIO; in tegra_get_syncpt_base()
584 args->id = host1x_syncpt_base_id(base); in tegra_get_syncpt_base()
587 mutex_unlock(&fpriv->lock); in tegra_get_syncpt_base()
600 switch (args->mode) { in tegra_gem_set_tiling()
604 if (args->value != 0) in tegra_gem_set_tiling()
605 return -EINVAL; in tegra_gem_set_tiling()
612 if (args->value != 0) in tegra_gem_set_tiling()
613 return -EINVAL; in tegra_gem_set_tiling()
620 if (args->value > 5) in tegra_gem_set_tiling()
621 return -EINVAL; in tegra_gem_set_tiling()
623 value = args->value; in tegra_gem_set_tiling()
627 return -EINVAL; in tegra_gem_set_tiling()
630 gem = drm_gem_object_lookup(file, args->handle); in tegra_gem_set_tiling()
632 return -ENOENT; in tegra_gem_set_tiling()
636 bo->tiling.mode = mode; in tegra_gem_set_tiling()
637 bo->tiling.value = value; in tegra_gem_set_tiling()
652 gem = drm_gem_object_lookup(file, args->handle); in tegra_gem_get_tiling()
654 return -ENOENT; in tegra_gem_get_tiling()
658 switch (bo->tiling.mode) { in tegra_gem_get_tiling()
660 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; in tegra_gem_get_tiling()
661 args->value = 0; in tegra_gem_get_tiling()
665 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; in tegra_gem_get_tiling()
666 args->value = 0; in tegra_gem_get_tiling()
670 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; in tegra_gem_get_tiling()
671 args->value = bo->tiling.value; in tegra_gem_get_tiling()
675 err = -EINVAL; in tegra_gem_get_tiling()
691 if (args->flags & ~DRM_TEGRA_GEM_FLAGS) in tegra_gem_set_flags()
692 return -EINVAL; in tegra_gem_set_flags()
694 gem = drm_gem_object_lookup(file, args->handle); in tegra_gem_set_flags()
696 return -ENOENT; in tegra_gem_set_flags()
699 bo->flags = 0; in tegra_gem_set_flags()
701 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) in tegra_gem_set_flags()
702 bo->flags |= TEGRA_BO_BOTTOM_UP; in tegra_gem_set_flags()
716 gem = drm_gem_object_lookup(file, args->handle); in tegra_gem_get_flags()
718 return -ENOENT; in tegra_gem_get_flags()
721 args->flags = 0; in tegra_gem_get_flags()
723 if (bo->flags & TEGRA_BO_BOTTOM_UP) in tegra_gem_get_flags()
724 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; in tegra_gem_get_flags()
788 struct tegra_drm_file *fpriv = file->driver_priv; in tegra_drm_postclose()
790 mutex_lock(&fpriv->lock); in tegra_drm_postclose()
791 idr_for_each(&fpriv->contexts, tegra_drm_context_cleanup, NULL); in tegra_drm_postclose()
792 mutex_unlock(&fpriv->lock); in tegra_drm_postclose()
794 idr_destroy(&fpriv->contexts); in tegra_drm_postclose()
795 mutex_destroy(&fpriv->lock); in tegra_drm_postclose()
802 struct drm_info_node *node = (struct drm_info_node *)s->private; in tegra_debugfs_framebuffers()
803 struct drm_device *drm = node->minor->dev; in tegra_debugfs_framebuffers()
806 mutex_lock(&drm->mode_config.fb_lock); in tegra_debugfs_framebuffers()
808 list_for_each_entry(fb, &drm->mode_config.fb_list, head) { in tegra_debugfs_framebuffers()
810 fb->base.id, fb->width, fb->height, in tegra_debugfs_framebuffers()
811 fb->format->depth, in tegra_debugfs_framebuffers()
812 fb->format->cpp[0] * 8, in tegra_debugfs_framebuffers()
816 mutex_unlock(&drm->mode_config.fb_lock); in tegra_debugfs_framebuffers()
823 struct drm_info_node *node = (struct drm_info_node *)s->private; in tegra_debugfs_iova()
824 struct drm_device *drm = node->minor->dev; in tegra_debugfs_iova()
825 struct tegra_drm *tegra = drm->dev_private; in tegra_debugfs_iova()
828 if (tegra->domain) { in tegra_debugfs_iova()
829 mutex_lock(&tegra->mm_lock); in tegra_debugfs_iova()
830 drm_mm_print(&tegra->mm, &p); in tegra_debugfs_iova()
831 mutex_unlock(&tegra->mm_lock); in tegra_debugfs_iova()
846 minor->debugfs_root, minor); in tegra_debugfs_init()
886 mutex_lock(&tegra->clients_lock); in tegra_drm_register_client()
887 list_add_tail(&client->list, &tegra->clients); in tegra_drm_register_client()
888 client->drm = tegra; in tegra_drm_register_client()
889 mutex_unlock(&tegra->clients_lock); in tegra_drm_register_client()
897 mutex_lock(&tegra->clients_lock); in tegra_drm_unregister_client()
898 list_del_init(&client->list); in tegra_drm_unregister_client()
899 client->drm = NULL; in tegra_drm_unregister_client()
900 mutex_unlock(&tegra->clients_lock); in tegra_drm_unregister_client()
907 struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev); in host1x_client_iommu_attach()
908 struct drm_device *drm = dev_get_drvdata(client->host); in host1x_client_iommu_attach()
909 struct tegra_drm *tegra = drm->dev_private; in host1x_client_iommu_attach()
916 * domain. This allows using the IOMMU-backed DMA API. in host1x_client_iommu_attach()
918 if (domain && domain != tegra->domain) in host1x_client_iommu_attach()
921 if (tegra->domain) { in host1x_client_iommu_attach()
922 group = iommu_group_get(client->dev); in host1x_client_iommu_attach()
924 return -ENODEV; in host1x_client_iommu_attach()
926 if (domain != tegra->domain) { in host1x_client_iommu_attach()
927 err = iommu_attach_group(tegra->domain, group); in host1x_client_iommu_attach()
934 tegra->use_explicit_iommu = true; in host1x_client_iommu_attach()
937 client->group = group; in host1x_client_iommu_attach()
944 struct drm_device *drm = dev_get_drvdata(client->host); in host1x_client_iommu_detach()
945 struct tegra_drm *tegra = drm->dev_private; in host1x_client_iommu_detach()
948 if (client->group) { in host1x_client_iommu_detach()
954 domain = iommu_get_domain_for_dev(client->dev); in host1x_client_iommu_detach()
956 iommu_detach_group(tegra->domain, client->group); in host1x_client_iommu_detach()
958 iommu_group_put(client->group); in host1x_client_iommu_detach()
959 client->group = NULL; in host1x_client_iommu_detach()
970 if (tegra->domain) in tegra_drm_alloc()
971 size = iova_align(&tegra->carveout.domain, size); in tegra_drm_alloc()
976 if (!tegra->domain) { in tegra_drm_alloc()
978 * Many units only support 32-bit addresses, even on 64-bit in tegra_drm_alloc()
979 * SoCs. If there is no IOMMU to translate into a 32-bit IO in tegra_drm_alloc()
981 * lower 32-bit range. in tegra_drm_alloc()
988 return ERR_PTR(-ENOMEM); in tegra_drm_alloc()
990 if (!tegra->domain) { in tegra_drm_alloc()
999 alloc = alloc_iova(&tegra->carveout.domain, in tegra_drm_alloc()
1000 size >> tegra->carveout.shift, in tegra_drm_alloc()
1001 tegra->carveout.limit, true); in tegra_drm_alloc()
1003 err = -EBUSY; in tegra_drm_alloc()
1007 *dma = iova_dma_addr(&tegra->carveout.domain, alloc); in tegra_drm_alloc()
1008 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt), in tegra_drm_alloc()
1016 __free_iova(&tegra->carveout.domain, alloc); in tegra_drm_alloc()
1026 if (tegra->domain) in tegra_drm_free()
1027 size = iova_align(&tegra->carveout.domain, size); in tegra_drm_free()
1031 if (tegra->domain) { in tegra_drm_free()
1032 iommu_unmap(tegra->domain, dma, size); in tegra_drm_free()
1033 free_iova(&tegra->carveout.domain, in tegra_drm_free()
1034 iova_pfn(&tegra->carveout.domain, dma)); in tegra_drm_free()
1042 struct host1x *host1x = dev_get_drvdata(dev->dev.parent); in host1x_drm_wants_iommu()
1051 * likely to be allocated beyond the 32-bit boundary if sufficient in host1x_drm_wants_iommu()
1056 * 32-bit boundary. in host1x_drm_wants_iommu()
1076 domain = iommu_get_domain_for_dev(dev->dev.parent); in host1x_drm_wants_iommu()
1080 * 32-bit boundary, so the regular GATHER opcodes will always be in host1x_drm_wants_iommu()
1097 drm = drm_dev_alloc(driver, &dev->dev); in host1x_drm_probe()
1103 err = -ENOMEM; in host1x_drm_probe()
1108 tegra->domain = iommu_domain_alloc(&platform_bus_type); in host1x_drm_probe()
1109 if (!tegra->domain) { in host1x_drm_probe()
1110 err = -ENOMEM; in host1x_drm_probe()
1119 mutex_init(&tegra->clients_lock); in host1x_drm_probe()
1120 INIT_LIST_HEAD(&tegra->clients); in host1x_drm_probe()
1122 dev_set_drvdata(&dev->dev, drm); in host1x_drm_probe()
1123 drm->dev_private = tegra; in host1x_drm_probe()
1124 tegra->drm = drm; in host1x_drm_probe()
1128 drm->mode_config.min_width = 0; in host1x_drm_probe()
1129 drm->mode_config.min_height = 0; in host1x_drm_probe()
1131 drm->mode_config.max_width = 4096; in host1x_drm_probe()
1132 drm->mode_config.max_height = 4096; in host1x_drm_probe()
1134 drm->mode_config.normalize_zpos = true; in host1x_drm_probe()
1136 drm->mode_config.funcs = &tegra_drm_mode_config_funcs; in host1x_drm_probe()
1137 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers; in host1x_drm_probe()
1149 if (tegra->use_explicit_iommu) { in host1x_drm_probe()
1151 u64 dma_mask = dma_get_mask(&dev->dev); in host1x_drm_probe()
1155 start = tegra->domain->geometry.aperture_start & dma_mask; in host1x_drm_probe()
1156 end = tegra->domain->geometry.aperture_end & dma_mask; in host1x_drm_probe()
1159 gem_end = end - CARVEOUT_SZ; in host1x_drm_probe()
1163 order = __ffs(tegra->domain->pgsize_bitmap); in host1x_drm_probe()
1164 init_iova_domain(&tegra->carveout.domain, 1UL << order, in host1x_drm_probe()
1167 tegra->carveout.shift = iova_shift(&tegra->carveout.domain); in host1x_drm_probe()
1168 tegra->carveout.limit = carveout_end >> tegra->carveout.shift; in host1x_drm_probe()
1170 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1); in host1x_drm_probe()
1171 mutex_init(&tegra->mm_lock); in host1x_drm_probe()
1174 DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end); in host1x_drm_probe()
1175 DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start, in host1x_drm_probe()
1177 } else if (tegra->domain) { in host1x_drm_probe()
1178 iommu_domain_free(tegra->domain); in host1x_drm_probe()
1179 tegra->domain = NULL; in host1x_drm_probe()
1183 if (tegra->hub) { in host1x_drm_probe()
1184 err = tegra_display_hub_prepare(tegra->hub); in host1x_drm_probe()
1194 drm->irq_enabled = true; in host1x_drm_probe()
1196 /* syncpoints are used for full 32-bit hardware VBLANK counters */ in host1x_drm_probe()
1197 drm->max_vblank_count = 0xffffffff; in host1x_drm_probe()
1199 err = drm_vblank_init(drm, drm->mode_config.num_crtc); in host1x_drm_probe()
1223 if (tegra->hub) in host1x_drm_probe()
1224 tegra_display_hub_cleanup(tegra->hub); in host1x_drm_probe()
1226 if (tegra->domain) { in host1x_drm_probe()
1227 mutex_destroy(&tegra->mm_lock); in host1x_drm_probe()
1228 drm_mm_takedown(&tegra->mm); in host1x_drm_probe()
1229 put_iova_domain(&tegra->carveout.domain); in host1x_drm_probe()
1240 if (tegra->domain) in host1x_drm_probe()
1241 iommu_domain_free(tegra->domain); in host1x_drm_probe()
1251 struct drm_device *drm = dev_get_drvdata(&dev->dev); in host1x_drm_remove()
1252 struct tegra_drm *tegra = drm->dev_private; in host1x_drm_remove()
1262 if (tegra->hub) in host1x_drm_remove()
1263 tegra_display_hub_cleanup(tegra->hub); in host1x_drm_remove()
1267 dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err); in host1x_drm_remove()
1269 if (tegra->domain) { in host1x_drm_remove()
1270 mutex_destroy(&tegra->mm_lock); in host1x_drm_remove()
1271 drm_mm_takedown(&tegra->mm); in host1x_drm_remove()
1272 put_iova_domain(&tegra->carveout.domain); in host1x_drm_remove()
1274 iommu_domain_free(tegra->domain); in host1x_drm_remove()
1303 { .compatible = "nvidia,tegra20-dc", },
1304 { .compatible = "nvidia,tegra20-hdmi", },
1305 { .compatible = "nvidia,tegra20-gr2d", },
1306 { .compatible = "nvidia,tegra20-gr3d", },
1307 { .compatible = "nvidia,tegra30-dc", },
1308 { .compatible = "nvidia,tegra30-hdmi", },
1309 { .compatible = "nvidia,tegra30-gr2d", },
1310 { .compatible = "nvidia,tegra30-gr3d", },
1311 { .compatible = "nvidia,tegra114-dsi", },
1312 { .compatible = "nvidia,tegra114-hdmi", },
1313 { .compatible = "nvidia,tegra114-gr3d", },
1314 { .compatible = "nvidia,tegra124-dc", },
1315 { .compatible = "nvidia,tegra124-sor", },
1316 { .compatible = "nvidia,tegra124-hdmi", },
1317 { .compatible = "nvidia,tegra124-dsi", },
1318 { .compatible = "nvidia,tegra124-vic", },
1319 { .compatible = "nvidia,tegra132-dsi", },
1320 { .compatible = "nvidia,tegra210-dc", },
1321 { .compatible = "nvidia,tegra210-dsi", },
1322 { .compatible = "nvidia,tegra210-sor", },
1323 { .compatible = "nvidia,tegra210-sor1", },
1324 { .compatible = "nvidia,tegra210-vic", },
1325 { .compatible = "nvidia,tegra186-display", },
1326 { .compatible = "nvidia,tegra186-dc", },
1327 { .compatible = "nvidia,tegra186-sor", },
1328 { .compatible = "nvidia,tegra186-sor1", },
1329 { .compatible = "nvidia,tegra186-vic", },
1330 { .compatible = "nvidia,tegra194-display", },
1331 { .compatible = "nvidia,tegra194-dc", },
1332 { .compatible = "nvidia,tegra194-sor", },
1333 { .compatible = "nvidia,tegra194-vic", },
1386 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");