Lines Matching +full:30 +full:bpp
308 # define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30
309 # define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)
312 # define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30
313 # define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)
332 # define SCALER_DISPCTRLX_RESET BIT(30)
341 /* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */
369 # define SCALER_DISPBKGND_INTERLACE BIT(30)
380 # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
381 # define SCALER_DISPSTATX_MODE_SHIFT 30
432 # define SCALER_GAMADDR_SRAMENB BIT(30)
486 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
597 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
631 # define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)
728 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
759 /* 8bpp */
761 /* 16bpp */
766 /* 24bpp */
769 /* 32bpp */
803 #define SCALER_CTL0_VALID BIT(30)
882 #define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
883 #define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
915 #define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
916 #define SCALER_POS2_ALPHA_MODE_SHIFT 30
1000 #define SCALER_PPF_AGC BIT(30)