Lines Matching +full:8 +full:bit
26 ('3' << 8) | \
37 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
38 # define V3D_IDENT1_QUPS_SHIFT 8
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
56 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
57 # define V3D_SLCACTL_UCC_SHIFT 8
64 # define V3D_INT_SPILLUSE BIT(3)
65 # define V3D_INT_OUTOMEM BIT(2)
66 # define V3D_INT_FLDONE BIT(1)
67 # define V3D_INT_FRDONE BIT(0)
72 # define V3D_CTRSTA BIT(15)
73 # define V3D_CTSEMA BIT(12)
74 # define V3D_CTRTSD BIT(8)
75 # define V3D_CTRUN BIT(5)
76 # define V3D_CTSUBS BIT(4)
77 # define V3D_CTERR BIT(3)
78 # define V3D_CTMODE BIT(0)
97 # define V3D_BMOOM BIT(8)
98 # define V3D_RMBUSY BIT(3)
99 # define V3D_RMACTIVE BIT(2)
100 # define V3D_BMBUSY BIT(1)
101 # define V3D_BMACTIVE BIT(0)
121 # define V3D_PCTRE_EN BIT(31)
122 #define V3D_PCTR(x) (0x00680 + ((x) * 8))
123 #define V3D_PCTRS(x) (0x00684 + ((x) * 8))
144 # define PV_CONTROL_CLR_AT_START BIT(14)
145 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
146 # define PV_CONTROL_WAIT_HSTART BIT(12)
154 # define PV_CONTROL_FIFO_CLR BIT(1)
155 # define PV_CONTROL_EN BIT(0)
160 # define PV_VCONTROL_ODD_FIRST BIT(5)
161 # define PV_VCONTROL_INTERLACE BIT(4)
162 # define PV_VCONTROL_DSI BIT(3)
163 # define PV_VCONTROL_COMMAND BIT(2)
164 # define PV_VCONTROL_CONTINUOUS BIT(1)
165 # define PV_VCONTROL_VIDEN BIT(0)
198 # define PV_INT_VID_IDLE BIT(9)
199 # define PV_INT_VFP_END BIT(8)
200 # define PV_INT_VFP_START BIT(7)
201 # define PV_INT_VACT_START BIT(6)
202 # define PV_INT_VBP_START BIT(5)
203 # define PV_INT_VSYNC_START BIT(4)
204 # define PV_INT_HFP_START BIT(3)
205 # define PV_INT_HACT_START BIT(2)
206 # define PV_INT_HBP_START BIT(1)
207 # define PV_INT_HSYNC_START BIT(0)
216 # define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP 8
222 # define SCALER_DISPCTRL_ENABLE BIT(31)
236 # define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x))
240 # define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))
242 # define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))
244 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
245 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
246 # define SCALER_DISPCTRL_DMAEIRQ BIT(4)
250 # define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x))
252 # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
262 # define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8))
264 # define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8))
268 # define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8))
272 # define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8))
276 # define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8))
278 # define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8))
280 # define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \
281 8 + ((x) * 8))
284 # define SCALER_DISPSTAT_DMA_ERROR BIT(7)
286 # define SCALER_DISPSTAT_IRQSLVRD BIT(6)
288 # define SCALER_DISPSTAT_IRQSLVWR BIT(5)
292 # define SCALER_DISPSTAT_IRQDMA BIT(4)
294 * corresponding interrupt bit is enabled in DISPCTRL.
296 # define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x))
298 # define SCALER_DISPSTAT_IRQSCL BIT(0)
331 # define SCALER_DISPCTRLX_ENABLE BIT(31)
332 # define SCALER_DISPCTRLX_RESET BIT(30)
336 # define SCALER_DISPCTRLX_ONESHOT BIT(29)
340 # define SCALER_DISPCTRLX_ONECTX BIT(28)
342 # define SCALER_DISPCTRLX_FIFO32 BIT(27)
346 # define SCALER_DISPCTRLX_FIFOREG BIT(26)
358 # define SCALER5_DISPCTRLX_ONESHOT BIT(15)
368 # define SCALER_DISPBKGND_AUTOHS BIT(31)
369 # define SCALER_DISPBKGND_INTERLACE BIT(30)
370 # define SCALER_DISPBKGND_GAMMA BIT(29)
377 # define SCALER_DISPBKGND_FILL BIT(24)
386 # define SCALER_DISPSTATX_FULL BIT(29)
387 # define SCALER_DISPSTATX_EMPTY BIT(28)
428 # define SCALER_GAMADDR_AUTOINC BIT(31)
432 # define SCALER_GAMADDR_SRAMENB BIT(30)
436 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
446 /* Offsets are 8-bit 2s-complement. */
449 # define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8)
450 # define SCALER_OLEDOFFS_GREEN_SHIFT 8
485 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
486 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
488 # define SCALER_DISPSLAVE_EOL BIT(26)
490 # define SCALER_DISPSLAVE_EMPTY BIT(25)
492 # define SCALER_DISPSLAVE_VALID BIT(24)
502 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
503 # define VC4_HDMI_SW_RESET_HDMI BIT(0)
505 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
507 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
508 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
512 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
513 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
514 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
515 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
519 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
521 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
525 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
530 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
532 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
536 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
540 # define VC4_HDMI_HORZA_VPOS BIT(14)
541 # define VC4_HDMI_HORZA_HPOS BIT(13)
556 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
557 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
558 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
559 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
560 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
561 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
562 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
563 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
564 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
565 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
568 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
569 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
570 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
571 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
572 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
588 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
592 # define VC4_HDMI_CEC_TX_EOM BIT(31)
597 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
598 # define VC4_HDMI_CEC_RX_EOM BIT(29)
599 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
603 /* Sets continuous receive mode. Generates interrupt after each 8
610 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
611 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
613 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
617 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
623 /* Divides off of HSM clock to generate CEC bit clock. */
624 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
628 /* Set these fields to how many bit clock cycles get to that many
646 # define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)
647 # define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
655 # define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)
656 # define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8
660 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
661 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
662 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
663 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
664 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
667 # define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)
668 # define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8
672 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
674 # define VC4_HDMI_CPU_CEC BIT(6)
675 # define VC4_HDMI_CPU_HOTPLUG BIT(0)
678 # define VC4_HD_CECRXD BIT(9)
680 # define VC4_HD_CECOVR BIT(8)
683 # define VC4_HD_M_SW_RST BIT(2)
684 # define VC4_HD_M_ENABLE BIT(0)
689 # define VC4_HD_MAI_CTL_DLATE BIT(15)
690 # define VC4_HD_MAI_CTL_BUSY BIT(14)
691 # define VC4_HD_MAI_CTL_CHALIGN BIT(13)
692 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
693 # define VC4_HD_MAI_CTL_FULL BIT(11)
694 # define VC4_HD_MAI_CTL_EMPTY BIT(10)
695 # define VC4_HD_MAI_CTL_FLUSH BIT(9)
696 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
699 # define VC4_HD_MAI_CTL_PAREN BIT(8)
702 # define VC4_HD_MAI_CTL_ENABLE BIT(3)
703 /* Underflow error status bit, write 1 to clear. */
704 # define VC4_HD_MAI_CTL_ERRORE BIT(2)
705 /* Overflow error status bit, write 1 to clear. */
706 # define VC4_HD_MAI_CTL_ERRORF BIT(1)
707 /* Single-shot reset bit. Read value is undefined. */
708 # define VC4_HD_MAI_CTL_RESET BIT(0)
714 # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)
715 # define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8
722 # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)
723 # define VC4_HD_MAI_SMP_N_SHIFT 8
727 # define VC4_HD_VID_CTL_ENABLE BIT(31)
728 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
729 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
730 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
731 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
732 # define VC4_HD_VID_CTL_CLRSYNC BIT(24)
733 # define VC4_HD_VID_CTL_CLRRGB BIT(23)
734 # define VC4_HD_VID_CTL_BLANKPIX BIT(18)
744 # define VC4_HD_CSC_CTL_PADMSB BIT(4)
750 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
751 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
753 # define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)
759 /* 8bpp */
772 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
802 #define SCALER_CTL0_END BIT(31)
803 #define SCALER_CTL0_VALID BIT(30)
815 #define SCALER_CTL0_ALPHA_MASK BIT(19)
816 #define SCALER_CTL0_HFLIP BIT(16)
817 #define SCALER_CTL0_VFLIP BIT(15)
836 #define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
838 #define SCALER5_CTL0_RGB_EXPAND BIT(11)
840 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
841 #define SCALER_CTL0_SCL1_SHIFT 8
856 #define SCALER_CTL0_UNITY BIT(4)
857 #define SCALER5_CTL0_UNITY BIT(15)
879 #define SCALER5_POS0_VFLIP BIT(31)
880 #define SCALER5_POS0_HFLIP BIT(15)
889 #define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
891 #define SCALER5_CTL2_ALPHA_MIX BIT(28)
893 #define SCALER5_CTL2_ALPHA_LOC BIT(25)
898 #define SCALER5_CTL2_GAMMA BIT(16)
921 #define SCALER_POS2_ALPHA_PREMULT BIT(29)
922 #define SCALER_POS2_ALPHA_MIX BIT(28)
936 /* Color Space Conversion words. Some values are S2.8 signed
940 /* bottom 8 bits of S2.8 contribution of Cr to Blue */
947 #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
948 #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
956 /* S2.8 contribution of Cb to Green */
959 /* S2.8 contribution of Cr to Green */
962 /* S2.8 contribution of Y to all of RGB */
965 /* top 2 bits of S2.8 contribution of Cr to Blue */
972 /* S2.8 contribution of Cb to Red */
975 /* S2.8 contribution of Cr to Red */
978 /* S2.8 contribution of Cb to Blue */
985 #define SCALER_TPZ0_VERT_RECALC BIT(31)
986 #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
987 #define SCALER_TPZ0_SCALE_SHIFT 8
993 /* Skips interpolating coefficients to 64 phases, so just 8 are used.
996 #define SCALER_PPF_NOINTERP BIT(31)
1000 #define SCALER_PPF_AGC BIT(30)
1001 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
1002 #define SCALER_PPF_SCALE_SHIFT 8
1008 #define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1027 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1028 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
1030 #define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
1031 #define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8