49 #define CMDBUF_ALIGNMENT_SIZE   (0x100)
50 #define CMDBUF_ALIGNMENT_MASK   (0x0ff)
53 #define VIA_REG_STATUS          0x400
54 #define VIA_REG_TRANSET         0x43C
55 #define VIA_REG_TRANSPACE       0x440
57 /* VIA_REG_STATUS(0x400): Engine Status */
58 #define VIA_CMD_RGTR_BUSY       0x00000080	/* Command Regulator is busy */
59 #define VIA_2D_ENG_BUSY         0x00000001	/* 2D Engine is busy */
60 #define VIA_3D_ENG_BUSY         0x00000002	/* 3D Engine is busy */
61 #define VIA_VR_QUEUE_BUSY       0x00020000	/* Virtual Queue is busy */
76 } while (0)
130 		if (count-- == 0) {  in via_cmdbuf_wait()
139 	return 0;  in via_cmdbuf_wait()
156 	if (via_cmdbuf_wait(dev_priv, size) != 0)  in via_check_dma()
177 	return 0;  in via_dma_cleanup()
206 	dev_priv->ring.map.type = 0;  in via_initialize()
207 	dev_priv->ring.map.flags = 0;  in via_initialize()
208 	dev_priv->ring.map.mtrr = 0;  in via_initialize()
222 	dev_priv->dma_low = 0;  in via_initialize()
233 	return 0;  in via_initialize()
240 	int retcode = 0;  in via_dma_init()
257 			0 : -EFAULT;  in via_dma_init()
298 	vb = via_check_dma(dev_priv, (cmd->size < 0x100) ? 0x102 : cmd->size);  in via_dispatch_cmdbuffer()
311 	if (cmd->size < 0x100)  in via_dispatch_cmdbuffer()
312 		via_pad_cache(dev_priv, (0x100 - cmd->size) >> 3);  in via_dispatch_cmdbuffer()
315 	return 0;  in via_dispatch_cmdbuffer()
324 	return 0;  in via_driver_dma_quiescent()
361 				       cmd->size, dev, 0))) {  in via_dispatch_pci_cmdbuffer()
387 	for (; qw_count > 0; --qw_count)  in via_align_buffer()
416 	paused = 0;  in via_hook_segment()
439 	while (diff == 0 && count--) {  in via_hook_segment()
440 		paused = (via_read(dev_priv, 0x41c) & 0x80000000);  in via_hook_segment()
447 	paused = via_read(dev_priv, 0x41c) & 0x80000000;  in via_hook_segment()
453 		if (diff != 0 && diff < (dev_priv->dma_high >> 1)) {  in via_hook_segment()
455 				  "0x%08x, 0x%08x 0x%08x\n",  in via_hook_segment()
457 		} else if (diff == 0) {  in via_hook_segment()
528 	dev_priv->dma_low = 0;  in via_cmdbuf_start()
534 	start_addr_lo = ((HC_SubA_HAGPBstL << 24) | (start_addr & 0xFFFFFF));  in via_cmdbuf_start()
535 	end_addr_lo = ((HC_SubA_HAGPBendL << 24) | (end_addr & 0xFFFFFF));  in via_cmdbuf_start()
537 		   ((end_addr & 0xff000000) >> 16));  in via_cmdbuf_start()
540 	    via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0,  in via_cmdbuf_start()
557 	dev_priv->dma_diff = 0;  in via_cmdbuf_start()
560 	while (!(via_read(dev_priv, 0x41c) & 0x80000000) && count--);  in via_cmdbuf_start()
589 	SetReg2DAGP(0x0C, (0 | (0 << 16)));  in via_dummy_bitblt()
590 	SetReg2DAGP(0x10, 0 | (0 << 16));  in via_dummy_bitblt()
591 	SetReg2DAGP(0x0, 0x1 | 0x2000 | 0xAA000000);  in via_dummy_bitblt()
603 	via_align_cmd(dev_priv, HC_HAGPBpID_JUMP, 0, &jump_addr_hi,  in via_cmdbuf_jump()
604 		      &jump_addr_lo, 0);  in via_cmdbuf_jump()
612 	dev_priv->dma_low = 0;  in via_cmdbuf_jump()
613 	if (via_cmdbuf_wait(dev_priv, CMDBUF_ALIGNMENT_SIZE) != 0)  in via_cmdbuf_jump()
620 	    via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,  in via_cmdbuf_jump()
621 			  &pause_addr_lo, 0) - 1;  in via_cmdbuf_jump()
622 	via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,  in via_cmdbuf_jump()
623 		      &pause_addr_lo, 0);  in via_cmdbuf_jump()
638 		via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,  in via_cmdbuf_jump()
639 			      &pause_addr_lo, 0) - 1;  in via_cmdbuf_jump()
640 	via_align_cmd(dev_priv, HC_HAGPBpID_PAUSE, 0, &pause_addr_hi,  in via_cmdbuf_jump()
641 		      &pause_addr_lo, 0);  in via_cmdbuf_jump()
646 	via_hook_segment(dev_priv, jump_addr_hi, jump_addr_lo, 0);  in via_cmdbuf_jump()
648 	via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);  in via_cmdbuf_jump()
661 	via_align_cmd(dev_priv, cmd_type, 0, &pause_addr_hi, &pause_addr_lo, 0);  in via_cmdbuf_flush()
662 	via_hook_segment(dev_priv, pause_addr_hi, pause_addr_lo, 0);  in via_cmdbuf_flush()
683 	int ret = 0;  in via_cmdbuf_size()