1 // SPDX-License-Identifier: GPL-2.0-only
3  * Tegra host1x driver
5  * Copyright (c) 2010-2013, NVIDIA Corporation.
9 #include <linux/dma-mapping.h>
18 #include <trace/events/host1x.h>
22 #include <asm/dma-iommu.h>
38 void host1x_hypervisor_writel(struct host1x *host1x, u32 v, u32 r)  in host1x_hypervisor_writel()  argument
40 	writel(v, host1x->hv_regs + r);  in host1x_hypervisor_writel()
43 u32 host1x_hypervisor_readl(struct host1x *host1x, u32 r)  in host1x_hypervisor_readl()  argument
45 	return readl(host1x->hv_regs + r);  in host1x_hypervisor_readl()
48 void host1x_sync_writel(struct host1x *host1x, u32 v, u32 r)  in host1x_sync_writel()  argument
50 	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;  in host1x_sync_writel()
55 u32 host1x_sync_readl(struct host1x *host1x, u32 r)  in host1x_sync_readl()  argument
57 	void __iomem *sync_regs = host1x->regs + host1x->info->sync_offset;  in host1x_sync_readl()
64 	writel(v, ch->regs + r);  in host1x_ch_writel()
69 	return readl(ch->regs + r);  in host1x_ch_readl()
175 	{ .compatible = "nvidia,tegra194-host1x", .data = &host1x07_info, },
176 	{ .compatible = "nvidia,tegra186-host1x", .data = &host1x06_info, },
177 	{ .compatible = "nvidia,tegra210-host1x", .data = &host1x05_info, },
178 	{ .compatible = "nvidia,tegra124-host1x", .data = &host1x04_info, },
179 	{ .compatible = "nvidia,tegra114-host1x", .data = &host1x02_info, },
180 	{ .compatible = "nvidia,tegra30-host1x", .data = &host1x01_info, },
181 	{ .compatible = "nvidia,tegra20-host1x", .data = &host1x01_info, },
186 static void host1x_setup_sid_table(struct host1x *host)  in host1x_setup_sid_table()
188 	const struct host1x_info *info = host->info;  in host1x_setup_sid_table()
191 	for (i = 0; i < info->num_sid_entries; i++) {  in host1x_setup_sid_table()
192 		const struct host1x_sid_entry *entry = &info->sid_table[i];  in host1x_setup_sid_table()
194 		host1x_hypervisor_writel(host, entry->offset, entry->base);  in host1x_setup_sid_table()
195 		host1x_hypervisor_writel(host, entry->limit, entry->base + 4);  in host1x_setup_sid_table()
199 static bool host1x_wants_iommu(struct host1x *host1x)  in host1x_wants_iommu()  argument
207 	 * and if the host1x firewall is enabled, there's no need to enable  in host1x_wants_iommu()
214 	 * SoCs before Tegra186 (i.e. Tegra124 and Tegra210), the host1x can  in host1x_wants_iommu()
222 	 * buffers will be mapped into a 32-bit IOVA space that host1x can  in host1x_wants_iommu()
224 	 * within the limitations of the host1x on these SoCs.  in host1x_wants_iommu()
228 	 * the host1x firewall is disabled.  in host1x_wants_iommu()
230 	if (host1x->info->dma_mask <= DMA_BIT_MASK(32)) {  in host1x_wants_iommu()
238 static struct iommu_domain *host1x_iommu_attach(struct host1x *host)  in host1x_iommu_attach()
240 	struct iommu_domain *domain = iommu_get_domain_for_dev(host->dev);  in host1x_iommu_attach()
244 	if (host->dev->archdata.mapping) {  in host1x_iommu_attach()
246 				to_dma_iommu_mapping(host->dev);  in host1x_iommu_attach()
247 		arm_iommu_detach_device(host->dev);  in host1x_iommu_attach()
250 		domain = iommu_get_domain_for_dev(host->dev);  in host1x_iommu_attach()
256 	 * host1x firewall is already enabled and we don't support addressing  in host1x_iommu_attach()
259 	 * Similarly, if host1x is already attached to an IOMMU (via the DMA  in host1x_iommu_attach()
265 	host->group = iommu_group_get(host->dev);  in host1x_iommu_attach()
266 	if (host->group) {  in host1x_iommu_attach()
275 		host->domain = iommu_domain_alloc(&platform_bus_type);  in host1x_iommu_attach()
276 		if (!host->domain) {  in host1x_iommu_attach()
277 			err = -ENOMEM;  in host1x_iommu_attach()
281 		err = iommu_attach_group(host->domain, host->group);  in host1x_iommu_attach()
283 			if (err == -ENODEV)  in host1x_iommu_attach()
289 		geometry = &host->domain->geometry;  in host1x_iommu_attach()
290 		start = geometry->aperture_start & host->info->dma_mask;  in host1x_iommu_attach()
291 		end = geometry->aperture_end & host->info->dma_mask;  in host1x_iommu_attach()
293 		order = __ffs(host->domain->pgsize_bitmap);  in host1x_iommu_attach()
294 		init_iova_domain(&host->iova, 1UL << order, start >> order);  in host1x_iommu_attach()
295 		host->iova_end = end;  in host1x_iommu_attach()
297 		domain = host->domain;  in host1x_iommu_attach()
303 	iommu_domain_free(host->domain);  in host1x_iommu_attach()
304 	host->domain = NULL;  in host1x_iommu_attach()
308 	iommu_group_put(host->group);  in host1x_iommu_attach()
309 	host->group = NULL;  in host1x_iommu_attach()
314 static int host1x_iommu_init(struct host1x *host)  in host1x_iommu_init()
316 	u64 mask = host->info->dma_mask;  in host1x_iommu_init()
323 		dev_err(host->dev, "failed to attach to IOMMU: %d\n", err);  in host1x_iommu_init()
335 	if (!domain && !host->info->has_wide_gather)  in host1x_iommu_init()
338 	err = dma_coerce_mask_and_coherent(host->dev, mask);  in host1x_iommu_init()
340 		dev_err(host->dev, "failed to set DMA mask: %d\n", err);  in host1x_iommu_init()
347 static void host1x_iommu_exit(struct host1x *host)  in host1x_iommu_exit()
349 	if (host->domain) {  in host1x_iommu_exit()
350 		put_iova_domain(&host->iova);  in host1x_iommu_exit()
351 		iommu_detach_group(host->domain, host->group);  in host1x_iommu_exit()
353 		iommu_domain_free(host->domain);  in host1x_iommu_exit()
354 		host->domain = NULL;  in host1x_iommu_exit()
358 		iommu_group_put(host->group);  in host1x_iommu_exit()
359 		host->group = NULL;  in host1x_iommu_exit()
365 	struct host1x *host;  in host1x_probe()
370 	host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);  in host1x_probe()
372 		return -ENOMEM;  in host1x_probe()
374 	host->info = of_device_get_match_data(&pdev->dev);  in host1x_probe()
376 	if (host->info->has_hypervisor) {  in host1x_probe()
379 			dev_err(&pdev->dev, "failed to get vm registers\n");  in host1x_probe()
380 			return -ENXIO;  in host1x_probe()
386 			dev_err(&pdev->dev,  in host1x_probe()
388 			return -ENXIO;  in host1x_probe()
393 			dev_err(&pdev->dev, "failed to get registers\n");  in host1x_probe()
394 			return -ENXIO;  in host1x_probe()
402 	mutex_init(&host->devices_lock);  in host1x_probe()
403 	INIT_LIST_HEAD(&host->devices);  in host1x_probe()
404 	INIT_LIST_HEAD(&host->list);  in host1x_probe()
405 	host->dev = &pdev->dev;  in host1x_probe()
407 	/* set common host1x device data */  in host1x_probe()
410 	host->regs = devm_ioremap_resource(&pdev->dev, regs);  in host1x_probe()
411 	if (IS_ERR(host->regs))  in host1x_probe()
412 		return PTR_ERR(host->regs);  in host1x_probe()
414 	if (host->info->has_hypervisor) {  in host1x_probe()
415 		host->hv_regs = devm_ioremap_resource(&pdev->dev, hv_regs);  in host1x_probe()
416 		if (IS_ERR(host->hv_regs))  in host1x_probe()
417 			return PTR_ERR(host->hv_regs);  in host1x_probe()
420 	host->dev->dma_parms = &host->dma_parms;  in host1x_probe()
421 	dma_set_max_seg_size(host->dev, UINT_MAX);  in host1x_probe()
423 	if (host->info->init) {  in host1x_probe()
424 		err = host->info->init(host);  in host1x_probe()
429 	host->clk = devm_clk_get(&pdev->dev, NULL);  in host1x_probe()
430 	if (IS_ERR(host->clk)) {  in host1x_probe()
431 		err = PTR_ERR(host->clk);  in host1x_probe()
433 		if (err != -EPROBE_DEFER)  in host1x_probe()
434 			dev_err(&pdev->dev, "failed to get clock: %d\n", err);  in host1x_probe()
439 	host->rst = devm_reset_control_get(&pdev->dev, "host1x");  in host1x_probe()
440 	if (IS_ERR(host->rst)) {  in host1x_probe()
441 		err = PTR_ERR(host->rst);  in host1x_probe()
442 		dev_err(&pdev->dev, "failed to get reset: %d\n", err);  in host1x_probe()
448 		dev_err(&pdev->dev, "failed to setup IOMMU: %d\n", err);  in host1x_probe()
452 	err = host1x_channel_list_init(&host->channel_list,  in host1x_probe()
453 				       host->info->nb_channels);  in host1x_probe()
455 		dev_err(&pdev->dev, "failed to initialize channel list\n");  in host1x_probe()
459 	err = clk_prepare_enable(host->clk);  in host1x_probe()
461 		dev_err(&pdev->dev, "failed to enable clock\n");  in host1x_probe()
465 	err = reset_control_deassert(host->rst);  in host1x_probe()
467 		dev_err(&pdev->dev, "failed to deassert reset: %d\n", err);  in host1x_probe()
473 		dev_err(&pdev->dev, "failed to initialize syncpts\n");  in host1x_probe()
479 		dev_err(&pdev->dev, "failed to initialize interrupts\n");  in host1x_probe()
485 	if (host->info->has_hypervisor)  in host1x_probe()
492 	err = devm_of_platform_populate(&pdev->dev);  in host1x_probe()
506 	reset_control_assert(host->rst);  in host1x_probe()
508 	clk_disable_unprepare(host->clk);  in host1x_probe()
510 	host1x_channel_list_free(&host->channel_list);  in host1x_probe()
519 	struct host1x *host = platform_get_drvdata(pdev);  in host1x_remove()
525 	reset_control_assert(host->rst);  in host1x_remove()
526 	clk_disable_unprepare(host->clk);  in host1x_remove()
527 	host1x_channel_list_free(&host->channel_list);  in host1x_remove()
535 		.name = "tegra-host1x",
571  * host1x_get_dma_mask() - query the supported DMA mask for host1x
572  * @host1x: host1x instance
574  * Note that this returns the supported DMA mask for host1x, which can be
577 u64 host1x_get_dma_mask(struct host1x *host1x)  in host1x_get_dma_mask()  argument
579 	return host1x->info->dma_mask;  in host1x_get_dma_mask()
583 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
585 MODULE_DESCRIPTION("Host1x driver for Tegra products");