Lines Matching +full:i2c +full:- +full:fast +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Synopsys DesignWare I2C adapter driver (master only).
5 * Based on the TI DAVINCI I2C adapter driver.
16 #include <linux/i2c.h>
24 #include "i2c-designware-core.h"
29 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2); in i2c_dw_configure_fifo_master()
30 regmap_write(dev->map, DW_IC_RX_TL, 0); in i2c_dw_configure_fifo_master()
32 /* Configure the I2C master */ in i2c_dw_configure_fifo_master()
33 regmap_write(dev->map, DW_IC_CON, dev->master_cfg); in i2c_dw_configure_fifo_master()
41 struct i2c_timings *t = &dev->timings; in i2c_dw_set_timings_master()
49 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1); in i2c_dw_set_timings_master()
54 /* Set standard and fast speed dividers for high/low periods */ in i2c_dw_set_timings_master()
55 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
56 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */ in i2c_dw_set_timings_master()
58 /* Calculate SCL timing parameters for standard mode if not set */ in i2c_dw_set_timings_master()
59 if (!dev->ss_hcnt || !dev->ss_lcnt) { in i2c_dw_set_timings_master()
61 dev->ss_hcnt = in i2c_dw_set_timings_master()
67 dev->ss_lcnt = in i2c_dw_set_timings_master()
73 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
74 dev->ss_hcnt, dev->ss_lcnt); in i2c_dw_set_timings_master()
77 * Set SCL timing parameters for fast mode or fast mode plus. Only in i2c_dw_set_timings_master()
81 if (t->bus_freq_hz == 1000000) { in i2c_dw_set_timings_master()
83 * Check are Fast Mode Plus parameters available. Calculate in i2c_dw_set_timings_master()
84 * SCL timing parameters for Fast Mode Plus if not set. in i2c_dw_set_timings_master()
86 if (dev->fp_hcnt && dev->fp_lcnt) { in i2c_dw_set_timings_master()
87 dev->fs_hcnt = dev->fp_hcnt; in i2c_dw_set_timings_master()
88 dev->fs_lcnt = dev->fp_lcnt; in i2c_dw_set_timings_master()
91 dev->fs_hcnt = in i2c_dw_set_timings_master()
97 dev->fs_lcnt = in i2c_dw_set_timings_master()
106 * Calculate SCL timing parameters for fast mode if not set. They are in i2c_dw_set_timings_master()
107 * needed also in high speed mode. in i2c_dw_set_timings_master()
109 if (!dev->fs_hcnt || !dev->fs_lcnt) { in i2c_dw_set_timings_master()
111 dev->fs_hcnt = in i2c_dw_set_timings_master()
117 dev->fs_lcnt = in i2c_dw_set_timings_master()
123 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
124 fp_str, dev->fs_hcnt, dev->fs_lcnt); in i2c_dw_set_timings_master()
126 /* Check is high speed possible and fall back to fast mode if not */ in i2c_dw_set_timings_master()
127 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) == in i2c_dw_set_timings_master()
131 dev_err(dev->dev, "High Speed not supported!\n"); in i2c_dw_set_timings_master()
132 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ; in i2c_dw_set_timings_master()
133 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK; in i2c_dw_set_timings_master()
134 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_set_timings_master()
135 dev->hs_hcnt = 0; in i2c_dw_set_timings_master()
136 dev->hs_lcnt = 0; in i2c_dw_set_timings_master()
137 } else if (!dev->hs_hcnt || !dev->hs_lcnt) { in i2c_dw_set_timings_master()
139 dev->hs_hcnt = in i2c_dw_set_timings_master()
145 dev->hs_lcnt = in i2c_dw_set_timings_master()
151 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n", in i2c_dw_set_timings_master()
152 dev->hs_hcnt, dev->hs_lcnt); in i2c_dw_set_timings_master()
159 switch (dev->master_cfg & DW_IC_CON_SPEED_MASK) { in i2c_dw_set_timings_master()
161 mode_str = "Standard Mode"; in i2c_dw_set_timings_master()
164 mode_str = "High Speed Mode"; in i2c_dw_set_timings_master()
167 mode_str = "Fast Mode"; in i2c_dw_set_timings_master()
169 dev_dbg(dev->dev, "Bus speed: %s%s\n", mode_str, fp_str); in i2c_dw_set_timings_master()
176 * i2c_dw_init() - Initialize the designware I2C master hardware
179 * This functions configures and enables the I2C master.
180 * This function is called during I2C init function, and in case of timeout at
195 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt); in i2c_dw_init_master()
196 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt); in i2c_dw_init_master()
198 /* Write fast mode/fast mode plus timing parameters */ in i2c_dw_init_master()
199 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt); in i2c_dw_init_master()
200 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt); in i2c_dw_init_master()
203 if (dev->hs_hcnt && dev->hs_lcnt) { in i2c_dw_init_master()
204 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt); in i2c_dw_init_master()
205 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt); in i2c_dw_init_master()
209 if (dev->sda_hold_time) in i2c_dw_init_master()
210 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time); in i2c_dw_init_master()
220 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_init()
228 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) { in i2c_dw_xfer_init()
231 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing in i2c_dw_xfer_init()
232 * mode has to be enabled via bit 12 of IC_TAR register. in i2c_dw_xfer_init()
239 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER, in i2c_dw_xfer_init()
243 * Set the slave (target) address and enable 10-bit addressing mode in i2c_dw_xfer_init()
246 regmap_write(dev->map, DW_IC_TAR, in i2c_dw_xfer_init()
247 msgs[dev->msg_write_idx].addr | ic_tar); in i2c_dw_xfer_init()
256 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy); in i2c_dw_xfer_init()
259 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy); in i2c_dw_xfer_init()
260 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK); in i2c_dw_xfer_init()
272 struct i2c_msg *msgs = dev->msgs; in i2c_dw_xfer_msg()
275 u32 addr = msgs[dev->msg_write_idx].addr; in i2c_dw_xfer_msg()
276 u32 buf_len = dev->tx_buf_len; in i2c_dw_xfer_msg()
277 u8 *buf = dev->tx_buf; in i2c_dw_xfer_msg()
283 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) { in i2c_dw_xfer_msg()
284 u32 flags = msgs[dev->msg_write_idx].flags; in i2c_dw_xfer_msg()
288 * reprogram the target address in the I2C in i2c_dw_xfer_msg()
291 if (msgs[dev->msg_write_idx].addr != addr) { in i2c_dw_xfer_msg()
292 dev_err(dev->dev, in i2c_dw_xfer_msg()
294 dev->msg_err = -EINVAL; in i2c_dw_xfer_msg()
298 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) { in i2c_dw_xfer_msg()
300 buf = msgs[dev->msg_write_idx].buf; in i2c_dw_xfer_msg()
301 buf_len = msgs[dev->msg_write_idx].len; in i2c_dw_xfer_msg()
307 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) && in i2c_dw_xfer_msg()
308 (dev->msg_write_idx > 0)) in i2c_dw_xfer_msg()
312 regmap_read(dev->map, DW_IC_TXFLR, &flr); in i2c_dw_xfer_msg()
313 tx_limit = dev->tx_fifo_depth - flr; in i2c_dw_xfer_msg()
315 regmap_read(dev->map, DW_IC_RXFLR, &flr); in i2c_dw_xfer_msg()
316 rx_limit = dev->rx_fifo_depth - flr; in i2c_dw_xfer_msg()
329 * i2c-core always sets the buffer length of in i2c_dw_xfer_msg()
334 if (dev->msg_write_idx == dev->msgs_num - 1 && in i2c_dw_xfer_msg()
343 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) { in i2c_dw_xfer_msg()
346 if (dev->rx_outstanding >= dev->rx_fifo_depth) in i2c_dw_xfer_msg()
349 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
351 rx_limit--; in i2c_dw_xfer_msg()
352 dev->rx_outstanding++; in i2c_dw_xfer_msg()
354 regmap_write(dev->map, DW_IC_DATA_CMD, in i2c_dw_xfer_msg()
357 tx_limit--; buf_len--; in i2c_dw_xfer_msg()
360 dev->tx_buf = buf; in i2c_dw_xfer_msg()
361 dev->tx_buf_len = buf_len; in i2c_dw_xfer_msg()
371 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
376 dev->status |= STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
379 dev->status &= ~STATUS_WRITE_IN_PROGRESS; in i2c_dw_xfer_msg()
386 if (dev->msg_write_idx == dev->msgs_num) in i2c_dw_xfer_msg()
389 if (dev->msg_err) in i2c_dw_xfer_msg()
392 regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask); in i2c_dw_xfer_msg()
398 struct i2c_msg *msgs = dev->msgs; in i2c_dw_recv_len()
399 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_recv_len()
406 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding); in i2c_dw_recv_len()
407 msgs[dev->msg_read_idx].len = len; in i2c_dw_recv_len()
408 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN; in i2c_dw_recv_len()
411 * Received buffer length, re-enable TX_EMPTY interrupt in i2c_dw_recv_len()
414 regmap_update_bits(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_TX_EMPTY, in i2c_dw_recv_len()
423 struct i2c_msg *msgs = dev->msgs; in i2c_dw_read()
426 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) { in i2c_dw_read()
430 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD)) in i2c_dw_read()
433 if (!(dev->status & STATUS_READ_IN_PROGRESS)) { in i2c_dw_read()
434 len = msgs[dev->msg_read_idx].len; in i2c_dw_read()
435 buf = msgs[dev->msg_read_idx].buf; in i2c_dw_read()
437 len = dev->rx_buf_len; in i2c_dw_read()
438 buf = dev->rx_buf; in i2c_dw_read()
441 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid); in i2c_dw_read()
443 for (; len > 0 && rx_valid > 0; len--, rx_valid--) { in i2c_dw_read()
444 u32 flags = msgs[dev->msg_read_idx].flags; in i2c_dw_read()
446 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp); in i2c_dw_read()
464 dev->rx_outstanding--; in i2c_dw_read()
468 dev->status |= STATUS_READ_IN_PROGRESS; in i2c_dw_read()
469 dev->rx_buf_len = len; in i2c_dw_read()
470 dev->rx_buf = buf; in i2c_dw_read()
473 dev->status &= ~STATUS_READ_IN_PROGRESS; in i2c_dw_read()
486 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num); in i2c_dw_xfer()
488 pm_runtime_get_sync(dev->dev); in i2c_dw_xfer()
490 if (dev_WARN_ONCE(dev->dev, dev->suspended, "Transfer while suspended\n")) { in i2c_dw_xfer()
491 ret = -ESHUTDOWN; in i2c_dw_xfer()
495 reinit_completion(&dev->cmd_complete); in i2c_dw_xfer()
496 dev->msgs = msgs; in i2c_dw_xfer()
497 dev->msgs_num = num; in i2c_dw_xfer()
498 dev->cmd_err = 0; in i2c_dw_xfer()
499 dev->msg_write_idx = 0; in i2c_dw_xfer()
500 dev->msg_read_idx = 0; in i2c_dw_xfer()
501 dev->msg_err = 0; in i2c_dw_xfer()
502 dev->status = STATUS_IDLE; in i2c_dw_xfer()
503 dev->abort_source = 0; in i2c_dw_xfer()
504 dev->rx_outstanding = 0; in i2c_dw_xfer()
518 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) { in i2c_dw_xfer()
519 dev_err(dev->dev, "controller timed out\n"); in i2c_dw_xfer()
521 i2c_recover_bus(&dev->adapter); in i2c_dw_xfer()
523 ret = -ETIMEDOUT; in i2c_dw_xfer()
537 if (dev->msg_err) { in i2c_dw_xfer()
538 ret = dev->msg_err; in i2c_dw_xfer()
543 if (likely(!dev->cmd_err && !dev->status)) { in i2c_dw_xfer()
549 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) { in i2c_dw_xfer()
554 if (dev->status) in i2c_dw_xfer()
555 dev_err(dev->dev, in i2c_dw_xfer()
556 "transfer terminated early - interrupt latency too high?\n"); in i2c_dw_xfer()
558 ret = -EIO; in i2c_dw_xfer()
564 pm_runtime_mark_last_busy(dev->dev); in i2c_dw_xfer()
565 pm_runtime_put_autosuspend(dev->dev); in i2c_dw_xfer()
595 regmap_read(dev->map, DW_IC_INTR_STAT, &stat); in i2c_dw_read_clear_intrbits()
602 * Instead, use the separately-prepared IC_CLR_* registers. in i2c_dw_read_clear_intrbits()
605 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy); in i2c_dw_read_clear_intrbits()
607 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
609 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy); in i2c_dw_read_clear_intrbits()
611 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy); in i2c_dw_read_clear_intrbits()
617 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source); in i2c_dw_read_clear_intrbits()
618 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy); in i2c_dw_read_clear_intrbits()
621 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy); in i2c_dw_read_clear_intrbits()
623 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy); in i2c_dw_read_clear_intrbits()
625 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy); in i2c_dw_read_clear_intrbits()
627 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy); in i2c_dw_read_clear_intrbits()
629 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy); in i2c_dw_read_clear_intrbits()
635 * Interrupt service routine. This gets called whenever an I2C master interrupt
644 dev->cmd_err |= DW_IC_ERR_TX_ABRT; in i2c_dw_irq_handler_master()
645 dev->status = STATUS_IDLE; in i2c_dw_irq_handler_master()
651 regmap_write(dev->map, DW_IC_INTR_MASK, 0); in i2c_dw_irq_handler_master()
668 if ((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) in i2c_dw_irq_handler_master()
669 complete(&dev->cmd_complete); in i2c_dw_irq_handler_master()
670 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) { in i2c_dw_irq_handler_master()
672 regmap_read(dev->map, DW_IC_INTR_MASK, &stat); in i2c_dw_irq_handler_master()
674 regmap_write(dev->map, DW_IC_INTR_MASK, stat); in i2c_dw_irq_handler_master()
685 regmap_read(dev->map, DW_IC_ENABLE, &enabled); in i2c_dw_isr()
686 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat); in i2c_dw_isr()
687 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat); in i2c_dw_isr()
698 struct i2c_timings *t = &dev->timings; in i2c_dw_configure_master()
700 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY; in i2c_dw_configure_master()
702 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE | in i2c_dw_configure_master()
705 dev->mode = DW_IC_MASTER; in i2c_dw_configure_master()
707 switch (t->bus_freq_hz) { in i2c_dw_configure_master()
709 dev->master_cfg |= DW_IC_CON_SPEED_STD; in i2c_dw_configure_master()
712 dev->master_cfg |= DW_IC_CON_SPEED_HIGH; in i2c_dw_configure_master()
715 dev->master_cfg |= DW_IC_CON_SPEED_FAST; in i2c_dw_configure_master()
725 reset_control_assert(dev->rst); in i2c_dw_prepare_recovery()
734 reset_control_deassert(dev->rst); in i2c_dw_unprepare_recovery()
740 struct i2c_bus_recovery_info *rinfo = &dev->rinfo; in i2c_dw_init_recovery_info()
741 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_init_recovery_info()
744 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH); in i2c_dw_init_recovery_info()
748 rinfo->scl_gpiod = gpio; in i2c_dw_init_recovery_info()
750 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN); in i2c_dw_init_recovery_info()
753 rinfo->sda_gpiod = gpio; in i2c_dw_init_recovery_info()
755 rinfo->recover_bus = i2c_generic_scl_recovery; in i2c_dw_init_recovery_info()
756 rinfo->prepare_recovery = i2c_dw_prepare_recovery; in i2c_dw_init_recovery_info()
757 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery; in i2c_dw_init_recovery_info()
758 adap->bus_recovery_info = rinfo; in i2c_dw_init_recovery_info()
760 dev_info(dev->dev, "running with gpio recovery mode! scl%s", in i2c_dw_init_recovery_info()
761 rinfo->sda_gpiod ? ",sda" : ""); in i2c_dw_init_recovery_info()
768 struct i2c_adapter *adap = &dev->adapter; in i2c_dw_probe_master()
772 init_completion(&dev->cmd_complete); in i2c_dw_probe_master()
774 dev->init = i2c_dw_init_master; in i2c_dw_probe_master()
775 dev->disable = i2c_dw_disable; in i2c_dw_probe_master()
776 dev->disable_int = i2c_dw_disable_int; in i2c_dw_probe_master()
790 ret = dev->init(dev); in i2c_dw_probe_master()
794 snprintf(adap->name, sizeof(adap->name), in i2c_dw_probe_master()
795 "Synopsys DesignWare I2C adapter"); in i2c_dw_probe_master()
796 adap->retries = 3; in i2c_dw_probe_master()
797 adap->algo = &i2c_dw_algo; in i2c_dw_probe_master()
798 adap->quirks = &i2c_dw_quirks; in i2c_dw_probe_master()
799 adap->dev.parent = dev->dev; in i2c_dw_probe_master()
802 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) { in i2c_dw_probe_master()
809 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr, irq_flags, in i2c_dw_probe_master()
810 dev_name(dev->dev), dev); in i2c_dw_probe_master()
812 dev_err(dev->dev, "failure requesting irq %i: %d\n", in i2c_dw_probe_master()
813 dev->irq, ret); in i2c_dw_probe_master()
825 * registered I2C slaves that do I2C transfers in their probe. in i2c_dw_probe_master()
827 pm_runtime_get_noresume(dev->dev); in i2c_dw_probe_master()
830 dev_err(dev->dev, "failure adding adapter: %d\n", ret); in i2c_dw_probe_master()
831 pm_runtime_put_noidle(dev->dev); in i2c_dw_probe_master()
837 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");