Lines Matching +full:idle +full:- +full:wait +full:- +full:delay
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
17 #include <linux/delay.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
80 /* Max time to wait for bus to become idle after a xfer (in us) */
96 wait_queue_head_t wait; member
127 .name = "s3c2410-i2c",
130 .name = "s3c2440-i2c",
133 .name = "s3c2440-hdmiphy-i2c",
143 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
144 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
145 { .compatible = "samsung,s3c2440-hdmiphy-i2c",
147 { .compatible = "samsung,exynos5-sata-phy-i2c",
159 if (pdev->dev.of_node) { in s3c24xx_get_device_quirks()
162 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node); in s3c24xx_get_device_quirks()
163 return (kernel_ulong_t)match->data; in s3c24xx_get_device_quirks()
166 return platform_get_device_id(pdev)->driver_data; in s3c24xx_get_device_quirks()
175 dev_dbg(i2c->dev, "master_complete %d\n", ret); in s3c24xx_i2c_master_complete()
177 i2c->msg_ptr = 0; in s3c24xx_i2c_master_complete()
178 i2c->msg = NULL; in s3c24xx_i2c_master_complete()
179 i2c->msg_idx++; in s3c24xx_i2c_master_complete()
180 i2c->msg_num = 0; in s3c24xx_i2c_master_complete()
182 i2c->msg_idx = ret; in s3c24xx_i2c_master_complete()
184 if (!(i2c->quirks & QUIRK_POLL)) in s3c24xx_i2c_master_complete()
185 wake_up(&i2c->wait); in s3c24xx_i2c_master_complete()
192 tmp = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_disable_ack()
193 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_disable_ack()
200 tmp = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_enable_ack()
201 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_enable_ack()
209 tmp = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_disable_irq()
210 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_disable_irq()
217 tmp = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_enable_irq()
218 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_enable_irq()
225 for (tries = 50; tries; --tries) { in is_ack()
226 unsigned long tmp = readl(i2c->regs + S3C2410_IICCON); in is_ack()
230 * Wait a bit for the bus to stabilize, in is_ack()
231 * delay estimated experimentally. in is_ack()
237 if (!(readl(i2c->regs + S3C2410_IICSTAT) in is_ack()
243 dev_err(i2c->dev, "ack was not received\n"); in is_ack()
253 unsigned int addr = (msg->addr & 0x7f) << 1; in s3c24xx_i2c_message_start()
260 if (msg->flags & I2C_M_RD) { in s3c24xx_i2c_message_start()
266 if (msg->flags & I2C_M_REV_DIR_ADDR) in s3c24xx_i2c_message_start()
269 /* todo - check for whether ack wanted or not */ in s3c24xx_i2c_message_start()
272 iiccon = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_message_start()
273 writel(stat, i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_message_start()
275 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr); in s3c24xx_i2c_message_start()
276 writeb(addr, i2c->regs + S3C2410_IICDS); in s3c24xx_i2c_message_start()
279 * delay here to ensure the data byte has gotten onto the bus in s3c24xx_i2c_message_start()
282 ndelay(i2c->tx_setup); in s3c24xx_i2c_message_start()
284 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon); in s3c24xx_i2c_message_start()
285 writel(iiccon, i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_message_start()
288 writel(stat, i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_message_start()
293 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_stop()
295 dev_dbg(i2c->dev, "STOP\n"); in s3c24xx_i2c_stop()
299 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP') in s3c24xx_i2c_stop()
300 * 2) I2CCON.4 = 0 - Clear IRQPEND in s3c24xx_i2c_stop()
301 * 3) Wait until the stop condition takes effect. in s3c24xx_i2c_stop()
302 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN in s3c24xx_i2c_stop()
308 * Master->Slave when they complete generating a STOP condition. in s3c24xx_i2c_stop()
321 * To avoid these extra post-STOP transactions on HDMI phy devices, we in s3c24xx_i2c_stop()
331 if (i2c->quirks & QUIRK_HDMIPHY) { in s3c24xx_i2c_stop()
338 writel(iicstat, i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_stop()
340 i2c->state = STATE_STOP; in s3c24xx_i2c_stop()
356 return i2c->msg_idx >= (i2c->msg_num - 1); in is_lastmsg()
365 * msg->len is always 1 for the first byte of smbus block read. in is_msglast()
369 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) in is_msglast()
372 return i2c->msg_ptr == i2c->msg->len-1; in is_msglast()
380 return i2c->msg_ptr >= i2c->msg->len; in is_msgend()
392 switch (i2c->state) { in i2c_s3c_irq_nextbyte()
395 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__); in i2c_s3c_irq_nextbyte()
399 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__); in i2c_s3c_irq_nextbyte()
409 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) { in i2c_s3c_irq_nextbyte()
411 dev_dbg(i2c->dev, "ack was not received\n"); in i2c_s3c_irq_nextbyte()
412 s3c24xx_i2c_stop(i2c, -ENXIO); in i2c_s3c_irq_nextbyte()
416 if (i2c->msg->flags & I2C_M_RD) in i2c_s3c_irq_nextbyte()
417 i2c->state = STATE_READ; in i2c_s3c_irq_nextbyte()
419 i2c->state = STATE_WRITE; in i2c_s3c_irq_nextbyte()
425 if (is_lastmsg(i2c) && i2c->msg->len == 0) { in i2c_s3c_irq_nextbyte()
430 if (i2c->state == STATE_READ) in i2c_s3c_irq_nextbyte()
443 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) { in i2c_s3c_irq_nextbyte()
445 dev_dbg(i2c->dev, "WRITE: No Ack\n"); in i2c_s3c_irq_nextbyte()
447 s3c24xx_i2c_stop(i2c, -ECONNREFUSED); in i2c_s3c_irq_nextbyte()
455 byte = i2c->msg->buf[i2c->msg_ptr++]; in i2c_s3c_irq_nextbyte()
456 writeb(byte, i2c->regs + S3C2410_IICDS); in i2c_s3c_irq_nextbyte()
459 * delay after writing the byte to allow the in i2c_s3c_irq_nextbyte()
465 ndelay(i2c->tx_setup); in i2c_s3c_irq_nextbyte()
470 dev_dbg(i2c->dev, "WRITE: Next Message\n"); in i2c_s3c_irq_nextbyte()
472 i2c->msg_ptr = 0; in i2c_s3c_irq_nextbyte()
473 i2c->msg_idx++; in i2c_s3c_irq_nextbyte()
474 i2c->msg++; in i2c_s3c_irq_nextbyte()
477 if (i2c->msg->flags & I2C_M_NOSTART) { in i2c_s3c_irq_nextbyte()
479 if (i2c->msg->flags & I2C_M_RD) { in i2c_s3c_irq_nextbyte()
485 dev_dbg(i2c->dev, in i2c_s3c_irq_nextbyte()
486 "missing START before write->read\n"); in i2c_s3c_irq_nextbyte()
487 s3c24xx_i2c_stop(i2c, -EINVAL); in i2c_s3c_irq_nextbyte()
494 s3c24xx_i2c_message_start(i2c, i2c->msg); in i2c_s3c_irq_nextbyte()
495 i2c->state = STATE_START; in i2c_s3c_irq_nextbyte()
510 byte = readb(i2c->regs + S3C2410_IICDS); in i2c_s3c_irq_nextbyte()
511 i2c->msg->buf[i2c->msg_ptr++] = byte; in i2c_s3c_irq_nextbyte()
514 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1) in i2c_s3c_irq_nextbyte()
515 i2c->msg->len += byte; in i2c_s3c_irq_nextbyte()
530 dev_dbg(i2c->dev, "READ: Send Stop\n"); in i2c_s3c_irq_nextbyte()
535 dev_dbg(i2c->dev, "READ: Next Transfer\n"); in i2c_s3c_irq_nextbyte()
537 i2c->msg_ptr = 0; in i2c_s3c_irq_nextbyte()
538 i2c->msg_idx++; in i2c_s3c_irq_nextbyte()
539 i2c->msg++; in i2c_s3c_irq_nextbyte()
549 tmp = readl(i2c->regs + S3C2410_IICCON); in i2c_s3c_irq_nextbyte()
551 writel(tmp, i2c->regs + S3C2410_IICCON); in i2c_s3c_irq_nextbyte()
565 status = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_irq()
569 dev_err(i2c->dev, "deal with arbitration loss\n"); in s3c24xx_i2c_irq()
572 if (i2c->state == STATE_IDLE) { in s3c24xx_i2c_irq()
573 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n"); in s3c24xx_i2c_irq()
575 tmp = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_irq()
577 writel(tmp, i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_irq()
596 * If there is an event on the bus, or we have a pre-existing event at
605 tmp = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_disable_bus()
607 writel(tmp, i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_disable_bus()
610 tmp = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_disable_bus()
613 writel(tmp, i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_disable_bus()
625 while (timeout-- > 0) { in s3c24xx_i2c_set_master()
626 iicstat = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_set_master()
634 return -ETIMEDOUT; in s3c24xx_i2c_set_master()
638 * wait for the i2c bus to become idle.
644 unsigned long delay; in s3c24xx_i2c_wait_idle() local
649 dev_dbg(i2c->dev, "waiting for bus idle\n"); in s3c24xx_i2c_wait_idle()
654 * Most of the time, the bus is already idle within a few usec of the in s3c24xx_i2c_wait_idle()
659 * instructions so busy wait briefly to avoid scheduling overhead. in s3c24xx_i2c_wait_idle()
662 iicstat = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_wait_idle()
663 while ((iicstat & S3C2410_IICSTAT_START) && --spins) { in s3c24xx_i2c_wait_idle()
665 iicstat = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_wait_idle()
669 * If we do get an appreciable delay as a compromise between idle in s3c24xx_i2c_wait_idle()
675 delay = 1; in s3c24xx_i2c_wait_idle()
678 usleep_range(delay, 2 * delay); in s3c24xx_i2c_wait_idle()
679 if (delay < S3C2410_IDLE_TIMEOUT / 10) in s3c24xx_i2c_wait_idle()
680 delay <<= 1; in s3c24xx_i2c_wait_idle()
682 iicstat = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_wait_idle()
686 dev_warn(i2c->dev, "timeout waiting for bus idle\n"); in s3c24xx_i2c_wait_idle()
700 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret); in s3c24xx_i2c_doxfer()
701 ret = -EAGAIN; in s3c24xx_i2c_doxfer()
705 i2c->msg = msgs; in s3c24xx_i2c_doxfer()
706 i2c->msg_num = num; in s3c24xx_i2c_doxfer()
707 i2c->msg_ptr = 0; in s3c24xx_i2c_doxfer()
708 i2c->msg_idx = 0; in s3c24xx_i2c_doxfer()
709 i2c->state = STATE_START; in s3c24xx_i2c_doxfer()
714 if (i2c->quirks & QUIRK_POLL) { in s3c24xx_i2c_doxfer()
715 while ((i2c->msg_num != 0) && is_ack(i2c)) { in s3c24xx_i2c_doxfer()
716 unsigned long stat = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_doxfer()
720 stat = readl(i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_doxfer()
722 dev_err(i2c->dev, "deal with arbitration loss\n"); in s3c24xx_i2c_doxfer()
725 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); in s3c24xx_i2c_doxfer()
728 ret = i2c->msg_idx; in s3c24xx_i2c_doxfer()
735 dev_dbg(i2c->dev, "timeout\n"); in s3c24xx_i2c_doxfer()
737 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); in s3c24xx_i2c_doxfer()
740 if (i2c->quirks & QUIRK_HDMIPHY) in s3c24xx_i2c_doxfer()
748 i2c->state = STATE_IDLE; in s3c24xx_i2c_doxfer()
760 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data; in s3c24xx_i2c_xfer()
764 ret = clk_enable(i2c->clk); in s3c24xx_i2c_xfer()
768 for (retry = 0; retry < adap->retries; retry++) { in s3c24xx_i2c_xfer()
772 if (ret != -EAGAIN) { in s3c24xx_i2c_xfer()
773 clk_disable(i2c->clk); in s3c24xx_i2c_xfer()
777 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry); in s3c24xx_i2c_xfer()
782 clk_disable(i2c->clk); in s3c24xx_i2c_xfer()
783 return -EREMOTEIO; in s3c24xx_i2c_xfer()
813 calc_divs += calc_div1-1; in s3c24xx_i2c_calcdivisor()
834 struct s3c2410_platform_i2c *pdata = i2c->pdata; in s3c24xx_i2c_clockrate()
835 unsigned long clkin = clk_get_rate(i2c->clk); in s3c24xx_i2c_clockrate()
841 i2c->clkrate = clkin; in s3c24xx_i2c_clockrate()
844 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency); in s3c24xx_i2c_clockrate()
846 target_frequency = pdata->frequency ?: I2C_MAX_STANDARD_MODE_FREQ; in s3c24xx_i2c_clockrate()
853 dev_err(i2c->dev, in s3c24xx_i2c_clockrate()
856 return -EINVAL; in s3c24xx_i2c_clockrate()
861 iiccon = readl(i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_clockrate()
863 iiccon |= (divs-1); in s3c24xx_i2c_clockrate()
868 if (i2c->quirks & QUIRK_POLL) in s3c24xx_i2c_clockrate()
871 writel(iiccon, i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_clockrate()
873 if (i2c->quirks & QUIRK_S3C2440) { in s3c24xx_i2c_clockrate()
876 if (pdata->sda_delay) { in s3c24xx_i2c_clockrate()
877 sda_delay = clkin * pdata->sda_delay; in s3c24xx_i2c_clockrate()
886 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay); in s3c24xx_i2c_clockrate()
887 writel(sda_delay, i2c->regs + S3C2440_IICLC); in s3c24xx_i2c_clockrate()
905 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate; in s3c24xx_i2c_cpufreq_transition()
907 /* if we're post-change and the input clock has slowed down in s3c24xx_i2c_cpufreq_transition()
908 * or at pre-change and the clock is about to speed up, then in s3c24xx_i2c_cpufreq_transition()
914 i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER); in s3c24xx_i2c_cpufreq_transition()
916 i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER); in s3c24xx_i2c_cpufreq_transition()
919 dev_err(i2c->dev, "cannot find frequency (%d)\n", ret); in s3c24xx_i2c_cpufreq_transition()
921 dev_info(i2c->dev, "setting freq %d\n", got); in s3c24xx_i2c_cpufreq_transition()
929 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition; in s3c24xx_i2c_register_cpufreq()
931 return cpufreq_register_notifier(&i2c->freq_transition, in s3c24xx_i2c_register_cpufreq()
937 cpufreq_unregister_notifier(&i2c->freq_transition, in s3c24xx_i2c_deregister_cpufreq()
957 if (i2c->quirks & QUIRK_NO_GPIO) in s3c24xx_i2c_parse_dt_gpio()
961 i2c->gpios[i] = devm_gpiod_get_index(i2c->dev, NULL, in s3c24xx_i2c_parse_dt_gpio()
963 if (IS_ERR(i2c->gpios[i])) { in s3c24xx_i2c_parse_dt_gpio()
964 dev_err(i2c->dev, "i2c gpio invalid at index %d\n", i); in s3c24xx_i2c_parse_dt_gpio()
965 return -EINVAL; in s3c24xx_i2c_parse_dt_gpio()
988 pdata = i2c->pdata; in s3c24xx_i2c_init()
992 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); in s3c24xx_i2c_init()
994 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr); in s3c24xx_i2c_init()
996 writel(0, i2c->regs + S3C2410_IICCON); in s3c24xx_i2c_init()
997 writel(0, i2c->regs + S3C2410_IICSTAT); in s3c24xx_i2c_init()
1002 dev_err(i2c->dev, "cannot meet bus frequency required\n"); in s3c24xx_i2c_init()
1003 return -EINVAL; in s3c24xx_i2c_init()
1006 /* todo - check that the i2c lines aren't being dragged anywhere */ in s3c24xx_i2c_init()
1008 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq); in s3c24xx_i2c_init()
1009 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n", in s3c24xx_i2c_init()
1010 readl(i2c->regs + S3C2410_IICCON)); in s3c24xx_i2c_init()
1022 struct s3c2410_platform_i2c *pdata = i2c->pdata; in s3c24xx_i2c_parse_dt()
1028 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */ in s3c24xx_i2c_parse_dt()
1029 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay); in s3c24xx_i2c_parse_dt()
1030 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); in s3c24xx_i2c_parse_dt()
1031 of_property_read_u32(np, "samsung,i2c-max-bus-freq", in s3c24xx_i2c_parse_dt()
1032 (u32 *)&pdata->frequency); in s3c24xx_i2c_parse_dt()
1036 * interrupts for 4-channel HS-I2C controller are enabled. in s3c24xx_i2c_parse_dt()
1038 * are available then re-configure the interrupts via the in s3c24xx_i2c_parse_dt()
1042 i2c->sysreg = syscon_regmap_lookup_by_phandle(np, in s3c24xx_i2c_parse_dt()
1043 "samsung,sysreg-phandle"); in s3c24xx_i2c_parse_dt()
1044 if (IS_ERR(i2c->sysreg)) in s3c24xx_i2c_parse_dt()
1047 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0); in s3c24xx_i2c_parse_dt()
1061 if (!pdev->dev.of_node) { in s3c24xx_i2c_probe()
1062 pdata = dev_get_platdata(&pdev->dev); in s3c24xx_i2c_probe()
1064 dev_err(&pdev->dev, "no platform data\n"); in s3c24xx_i2c_probe()
1065 return -EINVAL; in s3c24xx_i2c_probe()
1069 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL); in s3c24xx_i2c_probe()
1071 return -ENOMEM; in s3c24xx_i2c_probe()
1073 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); in s3c24xx_i2c_probe()
1074 if (!i2c->pdata) in s3c24xx_i2c_probe()
1075 return -ENOMEM; in s3c24xx_i2c_probe()
1077 i2c->quirks = s3c24xx_get_device_quirks(pdev); in s3c24xx_i2c_probe()
1078 i2c->sysreg = ERR_PTR(-ENOENT); in s3c24xx_i2c_probe()
1080 memcpy(i2c->pdata, pdata, sizeof(*pdata)); in s3c24xx_i2c_probe()
1082 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c); in s3c24xx_i2c_probe()
1084 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name)); in s3c24xx_i2c_probe()
1085 i2c->adap.owner = THIS_MODULE; in s3c24xx_i2c_probe()
1086 i2c->adap.algo = &s3c24xx_i2c_algorithm; in s3c24xx_i2c_probe()
1087 i2c->adap.retries = 2; in s3c24xx_i2c_probe()
1088 i2c->adap.class = I2C_CLASS_DEPRECATED; in s3c24xx_i2c_probe()
1089 i2c->tx_setup = 50; in s3c24xx_i2c_probe()
1091 init_waitqueue_head(&i2c->wait); in s3c24xx_i2c_probe()
1094 i2c->dev = &pdev->dev; in s3c24xx_i2c_probe()
1095 i2c->clk = devm_clk_get(&pdev->dev, "i2c"); in s3c24xx_i2c_probe()
1096 if (IS_ERR(i2c->clk)) { in s3c24xx_i2c_probe()
1097 dev_err(&pdev->dev, "cannot get clock\n"); in s3c24xx_i2c_probe()
1098 return -ENOENT; in s3c24xx_i2c_probe()
1101 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk); in s3c24xx_i2c_probe()
1105 i2c->regs = devm_ioremap_resource(&pdev->dev, res); in s3c24xx_i2c_probe()
1107 if (IS_ERR(i2c->regs)) in s3c24xx_i2c_probe()
1108 return PTR_ERR(i2c->regs); in s3c24xx_i2c_probe()
1110 dev_dbg(&pdev->dev, "registers %p (%p)\n", in s3c24xx_i2c_probe()
1111 i2c->regs, res); in s3c24xx_i2c_probe()
1114 i2c->adap.algo_data = i2c; in s3c24xx_i2c_probe()
1115 i2c->adap.dev.parent = &pdev->dev; in s3c24xx_i2c_probe()
1116 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev); in s3c24xx_i2c_probe()
1119 if (i2c->pdata->cfg_gpio) in s3c24xx_i2c_probe()
1120 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev)); in s3c24xx_i2c_probe()
1121 else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) in s3c24xx_i2c_probe()
1122 return -EINVAL; in s3c24xx_i2c_probe()
1125 ret = clk_prepare_enable(i2c->clk); in s3c24xx_i2c_probe()
1127 dev_err(&pdev->dev, "I2C clock enable failed\n"); in s3c24xx_i2c_probe()
1132 clk_disable(i2c->clk); in s3c24xx_i2c_probe()
1134 dev_err(&pdev->dev, "I2C controller init failed\n"); in s3c24xx_i2c_probe()
1135 clk_unprepare(i2c->clk); in s3c24xx_i2c_probe()
1143 if (!(i2c->quirks & QUIRK_POLL)) { in s3c24xx_i2c_probe()
1144 i2c->irq = ret = platform_get_irq(pdev, 0); in s3c24xx_i2c_probe()
1146 dev_err(&pdev->dev, "cannot find IRQ\n"); in s3c24xx_i2c_probe()
1147 clk_unprepare(i2c->clk); in s3c24xx_i2c_probe()
1151 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, in s3c24xx_i2c_probe()
1152 0, dev_name(&pdev->dev), i2c); in s3c24xx_i2c_probe()
1154 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); in s3c24xx_i2c_probe()
1155 clk_unprepare(i2c->clk); in s3c24xx_i2c_probe()
1162 dev_err(&pdev->dev, "failed to register cpufreq notifier\n"); in s3c24xx_i2c_probe()
1163 clk_unprepare(i2c->clk); in s3c24xx_i2c_probe()
1173 i2c->adap.nr = i2c->pdata->bus_num; in s3c24xx_i2c_probe()
1174 i2c->adap.dev.of_node = pdev->dev.of_node; in s3c24xx_i2c_probe()
1178 pm_runtime_enable(&pdev->dev); in s3c24xx_i2c_probe()
1180 ret = i2c_add_numbered_adapter(&i2c->adap); in s3c24xx_i2c_probe()
1182 pm_runtime_disable(&pdev->dev); in s3c24xx_i2c_probe()
1184 clk_unprepare(i2c->clk); in s3c24xx_i2c_probe()
1188 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev)); in s3c24xx_i2c_probe()
1196 clk_unprepare(i2c->clk); in s3c24xx_i2c_remove()
1198 pm_runtime_disable(&pdev->dev); in s3c24xx_i2c_remove()
1202 i2c_del_adapter(&i2c->adap); in s3c24xx_i2c_remove()
1212 i2c_mark_adapter_suspended(&i2c->adap); in s3c24xx_i2c_suspend_noirq()
1214 if (!IS_ERR(i2c->sysreg)) in s3c24xx_i2c_suspend_noirq()
1215 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg); in s3c24xx_i2c_suspend_noirq()
1225 if (!IS_ERR(i2c->sysreg)) in s3c24xx_i2c_resume_noirq()
1226 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg); in s3c24xx_i2c_resume_noirq()
1228 ret = clk_enable(i2c->clk); in s3c24xx_i2c_resume_noirq()
1232 clk_disable(i2c->clk); in s3c24xx_i2c_resume_noirq()
1233 i2c_mark_adapter_resumed(&i2c->adap); in s3c24xx_i2c_resume_noirq()
1255 .name = "s3c-i2c",