Lines Matching +full:i2c +full:- +full:fast +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
3 * drivers/i2c/busses/i2c-tegra.c
13 #include <linux/dma-mapping.h>
15 #include <linux/i2c.h>
50 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
51 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
129 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
130 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
143 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
153 * @MSG_END_REPEAT_START: Send repeat-start.
154 * @MSG_END_CONTINUE: Don't send stop or repeat-start.
164 * @has_continue_xfer_support: continue-transfer supported
169 * @clk_divisor_hs_mode: Clock divisor in HS mode.
170 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
171 * applicable if there is no fast clock source i.e. single clock
173 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
174 * applicable if there is no fast clock source i.e. single clock
176 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
177 * applicable if there is no fast clock source (i.e. single
179 * @has_multi_master_mode: The I2C controller supports running in single-master
180 * or multi-master mode.
181 * @has_slcg_override_reg: The I2C controller supports a register that
183 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
186 * @quirks: I2C adapter quirks for limiting write/read transfer size and not
191 * @tlow_std_mode: Low period of the clock in standard mode.
192 * @thigh_std_mode: High period of the clock in standard mode.
193 * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
194 * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
196 * in standard mode.
198 * conditions in fast/fast-plus modes.
200 * in HS mode.
229 * struct tegra_i2c_dev - per device I2C context
231 * @hw: Tegra I2C HW feature
232 * @adapter: core I2C layer adapter information
233 * @div_clk: clock reference for div clock of I2C controller
234 * @clocks: array of I2C controller clocks
236 * @rst: reset control for the I2C controller
238 * @base_phys: physical base address of the I2C controller
239 * @cont_id: I2C controller ID, used for packet header
241 * @is_dvc: identifies the DVC I2C controller, has a different register layout
242 * @is_vi: identifies the VI I2C controller, has a different register layout
248 * @bus_clk_rate: current I2C bus clock rate
249 * @multimaster_mode: indicates that I2C controller is in multi-master mode
301 writel_relaxed(val, i2c_dev->base + reg); in dvc_writel()
306 return readl_relaxed(i2c_dev->base + reg); in dvc_readl()
311 * in order to talk to the I2C block inside the DVC block.
315 if (i2c_dev->is_dvc) in tegra_i2c_reg_addr()
317 else if (i2c_dev->is_vi) in tegra_i2c_reg_addr()
325 writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
329 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
330 else if (i2c_dev->is_vi) in i2c_writel()
331 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS)); in i2c_writel()
336 return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_readl()
342 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_writesl()
351 * VI I2C controller has known hardware bug where writes get stuck in i2c_writesl_vi()
353 * Recommended software work around is to read I2C register after in i2c_writesl_vi()
356 while (len--) in i2c_writesl_vi()
363 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_readsl()
386 complete(&i2c_dev->dma_complete); in tegra_i2c_dma_complete()
395 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len); in tegra_i2c_dma_submit()
397 reinit_completion(&i2c_dev->dma_complete); in tegra_i2c_dma_submit()
399 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV; in tegra_i2c_dma_submit()
400 chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan; in tegra_i2c_dma_submit()
402 dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys, in tegra_i2c_dma_submit()
406 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n", in tegra_i2c_dma_submit()
407 i2c_dev->msg_read ? "RX" : "TX"); in tegra_i2c_dma_submit()
408 return -EINVAL; in tegra_i2c_dma_submit()
411 dma_desc->callback = tegra_i2c_dma_complete; in tegra_i2c_dma_submit()
412 dma_desc->callback_param = i2c_dev; in tegra_i2c_dma_submit()
422 if (i2c_dev->dma_buf) { in tegra_i2c_release_dma()
423 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, in tegra_i2c_release_dma()
424 i2c_dev->dma_buf, i2c_dev->dma_phys); in tegra_i2c_release_dma()
425 i2c_dev->dma_buf = NULL; in tegra_i2c_release_dma()
428 if (i2c_dev->tx_dma_chan) { in tegra_i2c_release_dma()
429 dma_release_channel(i2c_dev->tx_dma_chan); in tegra_i2c_release_dma()
430 i2c_dev->tx_dma_chan = NULL; in tegra_i2c_release_dma()
433 if (i2c_dev->rx_dma_chan) { in tegra_i2c_release_dma()
434 dma_release_channel(i2c_dev->rx_dma_chan); in tegra_i2c_release_dma()
435 i2c_dev->rx_dma_chan = NULL; in tegra_i2c_release_dma()
446 if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi) in tegra_i2c_init_dma()
450 dev_dbg(i2c_dev->dev, "DMA support not enabled\n"); in tegra_i2c_init_dma()
454 chan = dma_request_chan(i2c_dev->dev, "rx"); in tegra_i2c_init_dma()
460 i2c_dev->rx_dma_chan = chan; in tegra_i2c_init_dma()
462 chan = dma_request_chan(i2c_dev->dev, "tx"); in tegra_i2c_init_dma()
468 i2c_dev->tx_dma_chan = chan; in tegra_i2c_init_dma()
470 WARN_ON(i2c_dev->tx_dma_chan->device != i2c_dev->rx_dma_chan->device); in tegra_i2c_init_dma()
471 i2c_dev->dma_dev = chan->device->dev; in tegra_i2c_init_dma()
473 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len + in tegra_i2c_init_dma()
476 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size, in tegra_i2c_init_dma()
479 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n"); in tegra_i2c_init_dma()
480 err = -ENOMEM; in tegra_i2c_init_dma()
484 i2c_dev->dma_buf = dma_buf; in tegra_i2c_init_dma()
485 i2c_dev->dma_phys = dma_phys; in tegra_i2c_init_dma()
491 if (err != -EPROBE_DEFER) { in tegra_i2c_init_dma()
492 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err); in tegra_i2c_init_dma()
493 dev_err(i2c_dev->dev, "falling back to PIO\n"); in tegra_i2c_init_dma()
501 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
502 * block. This block is identical to the rest of the I2C blocks, except that
503 * it only supports master mode, it has registers moved around, and it needs
504 * some extra init to get it into I2C mode. The register moves are handled
554 void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg); in tegra_i2c_poll_register()
557 if (!i2c_dev->atomic_mode && !in_irq()) in tegra_i2c_poll_register()
570 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_flush_fifos()
586 dev_err(i2c_dev->dev, "failed to flush FIFO\n"); in tegra_i2c_flush_fifos()
597 if (!i2c_dev->hw->has_config_load_reg) in tegra_i2c_wait_for_config_load()
605 dev_err(i2c_dev->dev, "failed to load config\n"); in tegra_i2c_wait_for_config_load()
621 * kernel boot up since voltage regulators use I2C. Hence, we will in tegra_i2c_init()
625 err = reset_control_reset(i2c_dev->rst); in tegra_i2c_init()
628 if (i2c_dev->is_dvc) in tegra_i2c_init()
634 if (i2c_dev->hw->has_multi_master_mode) in tegra_i2c_init()
640 if (i2c_dev->is_vi) in tegra_i2c_init()
643 switch (i2c_dev->bus_clk_rate) { in tegra_i2c_init()
646 tlow = i2c_dev->hw->tlow_fast_fastplus_mode; in tegra_i2c_init()
647 thigh = i2c_dev->hw->thigh_fast_fastplus_mode; in tegra_i2c_init()
648 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; in tegra_i2c_init()
650 if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ) in tegra_i2c_init()
651 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; in tegra_i2c_init()
653 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; in tegra_i2c_init()
657 tlow = i2c_dev->hw->tlow_std_mode; in tegra_i2c_init()
658 thigh = i2c_dev->hw->thigh_std_mode; in tegra_i2c_init()
659 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; in tegra_i2c_init()
660 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; in tegra_i2c_init()
666 i2c_dev->hw->clk_divisor_hs_mode) | in tegra_i2c_init()
670 if (i2c_dev->hw->has_interface_timing_reg) { in tegra_i2c_init()
677 * Configure setup and hold times only when tsu_thd is non-zero. in tegra_i2c_init()
680 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) in tegra_i2c_init()
685 err = clk_set_rate(i2c_dev->div_clk, in tegra_i2c_init()
686 i2c_dev->bus_clk_rate * clk_multiplier); in tegra_i2c_init()
688 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); in tegra_i2c_init()
692 if (!i2c_dev->is_dvc && !i2c_dev->is_vi) { in tegra_i2c_init()
705 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg) in tegra_i2c_init()
720 * NACK interrupt is generated before the I2C controller generates in tegra_i2c_disable_packet_mode()
725 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); in tegra_i2c_disable_packet_mode()
736 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_empty_rx_fifo()
738 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_empty_rx_fifo()
745 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining))) in tegra_i2c_empty_rx_fifo()
746 return -EINVAL; in tegra_i2c_empty_rx_fifo()
748 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_empty_rx_fifo()
764 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_empty_rx_fifo()
765 rx_fifo_avail -= words_to_transfer; in tegra_i2c_empty_rx_fifo()
781 rx_fifo_avail--; in tegra_i2c_empty_rx_fifo()
786 return -EINVAL; in tegra_i2c_empty_rx_fifo()
788 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_empty_rx_fifo()
789 i2c_dev->msg_buf = buf; in tegra_i2c_empty_rx_fifo()
796 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_fill_tx_fifo()
798 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_fill_tx_fifo()
801 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_fill_tx_fifo()
829 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_fill_tx_fifo()
830 tx_fifo_avail -= words_to_transfer; in tegra_i2c_fill_tx_fifo()
832 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_fill_tx_fifo()
833 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_fill_tx_fifo()
835 if (i2c_dev->is_vi) in tegra_i2c_fill_tx_fifo()
852 * in this function for non-zero words_to_transfer. in tegra_i2c_fill_tx_fifo()
857 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_fill_tx_fifo()
858 i2c_dev->msg_buf = NULL; in tegra_i2c_fill_tx_fifo()
875 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n", in tegra_i2c_isr()
879 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
886 i2c_dev->msg_err |= I2C_ERR_NO_ACK; in tegra_i2c_isr()
888 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; in tegra_i2c_isr()
893 * I2C transfer is terminated during the bus clear, so skip in tegra_i2c_isr()
896 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE)) in tegra_i2c_isr()
899 if (!i2c_dev->dma_mode) { in tegra_i2c_isr()
900 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
907 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW; in tegra_i2c_isr()
912 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
913 if (i2c_dev->msg_buf_remaining) in tegra_i2c_isr()
922 if (i2c_dev->is_dvc) in tegra_i2c_isr()
931 * so forcing msg_buf_remaining to 0 in DMA mode. in tegra_i2c_isr()
934 if (i2c_dev->dma_mode) in tegra_i2c_isr()
935 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_isr()
940 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) { in tegra_i2c_isr()
941 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
944 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
956 if (i2c_dev->hw->supports_bus_clear) in tegra_i2c_isr()
961 if (i2c_dev->is_dvc) in tegra_i2c_isr()
964 if (i2c_dev->dma_mode) { in tegra_i2c_isr()
965 if (i2c_dev->msg_read) in tegra_i2c_isr()
966 dmaengine_terminate_async(i2c_dev->rx_dma_chan); in tegra_i2c_isr()
968 dmaengine_terminate_async(i2c_dev->tx_dma_chan); in tegra_i2c_isr()
970 complete(&i2c_dev->dma_complete); in tegra_i2c_isr()
973 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
986 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
991 if (i2c_dev->dma_mode) { in tegra_i2c_config_fifo_trig()
999 if (i2c_dev->msg_read) { in tegra_i2c_config_fifo_trig()
1000 chan = i2c_dev->rx_dma_chan; in tegra_i2c_config_fifo_trig()
1003 slv_config.src_addr = i2c_dev->base_phys + reg_offset; in tegra_i2c_config_fifo_trig()
1007 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1012 chan = i2c_dev->tx_dma_chan; in tegra_i2c_config_fifo_trig()
1015 slv_config.dst_addr = i2c_dev->base_phys + reg_offset; in tegra_i2c_config_fifo_trig()
1019 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1028 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err); in tegra_i2c_config_fifo_trig()
1029 dev_err(i2c_dev->dev, "falling back to PIO\n"); in tegra_i2c_config_fifo_trig()
1032 i2c_dev->dma_mode = false; in tegra_i2c_config_fifo_trig()
1038 if (i2c_dev->hw->has_mst_fifo) in tegra_i2c_config_fifo_trig()
1059 tegra_i2c_isr(i2c_dev->irq, i2c_dev); in tegra_i2c_poll_completion()
1080 if (i2c_dev->atomic_mode) { in tegra_i2c_wait_completion()
1083 enable_irq(i2c_dev->irq); in tegra_i2c_wait_completion()
1086 disable_irq(i2c_dev->irq); in tegra_i2c_wait_completion()
1092 * case we will get timeout if I2C transfer is running on in tegra_i2c_wait_completion()
1111 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_issue_bus_clear()
1125 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50); in tegra_i2c_issue_bus_clear()
1129 dev_err(i2c_dev->dev, "failed to clear bus\n"); in tegra_i2c_issue_bus_clear()
1130 return -ETIMEDOUT; in tegra_i2c_issue_bus_clear()
1135 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n"); in tegra_i2c_issue_bus_clear()
1136 return -EIO; in tegra_i2c_issue_bus_clear()
1139 return -EAGAIN; in tegra_i2c_issue_bus_clear()
1146 u32 *dma_buf = i2c_dev->dma_buf; in tegra_i2c_push_packet_header()
1152 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) | in tegra_i2c_push_packet_header()
1155 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1160 packet_header = msg->len - 1; in tegra_i2c_push_packet_header()
1162 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1174 if (msg->flags & I2C_M_TEN) { in tegra_i2c_push_packet_header()
1175 packet_header |= msg->addr; in tegra_i2c_push_packet_header()
1178 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; in tegra_i2c_push_packet_header()
1181 if (msg->flags & I2C_M_IGNORE_NAK) in tegra_i2c_push_packet_header()
1184 if (msg->flags & I2C_M_RD) in tegra_i2c_push_packet_header()
1187 if (i2c_dev->dma_mode && !i2c_dev->msg_read) in tegra_i2c_push_packet_header()
1196 if (i2c_dev->msg_err == I2C_ERR_NONE) in tegra_i2c_error_recover()
1201 /* start recovery upon arbitration loss in single master mode */ in tegra_i2c_error_recover()
1202 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) { in tegra_i2c_error_recover()
1203 if (!i2c_dev->multimaster_mode) in tegra_i2c_error_recover()
1204 return i2c_recover_bus(&i2c_dev->adapter); in tegra_i2c_error_recover()
1206 return -EAGAIN; in tegra_i2c_error_recover()
1209 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { in tegra_i2c_error_recover()
1210 if (msg->flags & I2C_M_IGNORE_NAK) in tegra_i2c_error_recover()
1213 return -EREMOTEIO; in tegra_i2c_error_recover()
1216 return -EIO; in tegra_i2c_error_recover()
1232 i2c_dev->msg_buf = msg->buf; in tegra_i2c_xfer_msg()
1233 i2c_dev->msg_buf_remaining = msg->len; in tegra_i2c_xfer_msg()
1234 i2c_dev->msg_err = I2C_ERR_NONE; in tegra_i2c_xfer_msg()
1235 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD); in tegra_i2c_xfer_msg()
1236 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_xfer_msg()
1238 if (i2c_dev->msg_read) in tegra_i2c_xfer_msg()
1239 xfer_size = msg->len; in tegra_i2c_xfer_msg()
1241 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE; in tegra_i2c_xfer_msg()
1245 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN && in tegra_i2c_xfer_msg()
1246 i2c_dev->dma_buf && !i2c_dev->atomic_mode; in tegra_i2c_xfer_msg()
1255 i2c_dev->bus_clk_rate); in tegra_i2c_xfer_msg()
1260 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1261 if (i2c_dev->msg_read) { in tegra_i2c_xfer_msg()
1262 dma_sync_single_for_device(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1263 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1270 dma_sync_single_for_cpu(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1271 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1278 if (!i2c_dev->msg_read) { in tegra_i2c_xfer_msg()
1279 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1280 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE, in tegra_i2c_xfer_msg()
1281 msg->buf, msg->len); in tegra_i2c_xfer_msg()
1283 dma_sync_single_for_device(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1284 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1295 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) in tegra_i2c_xfer_msg()
1298 if (!i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1299 if (msg->flags & I2C_M_RD) in tegra_i2c_xfer_msg()
1301 else if (i2c_dev->msg_buf_remaining) in tegra_i2c_xfer_msg()
1306 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n", in tegra_i2c_xfer_msg()
1309 if (i2c_dev->dma_mode) { in tegra_i2c_xfer_msg()
1311 &i2c_dev->dma_complete, in tegra_i2c_xfer_msg()
1319 dmaengine_synchronize(i2c_dev->msg_read ? in tegra_i2c_xfer_msg()
1320 i2c_dev->rx_dma_chan : in tegra_i2c_xfer_msg()
1321 i2c_dev->tx_dma_chan); in tegra_i2c_xfer_msg()
1323 dmaengine_terminate_sync(i2c_dev->msg_read ? in tegra_i2c_xfer_msg()
1324 i2c_dev->rx_dma_chan : in tegra_i2c_xfer_msg()
1325 i2c_dev->tx_dma_chan); in tegra_i2c_xfer_msg()
1327 if (!time_left && !completion_done(&i2c_dev->dma_complete)) { in tegra_i2c_xfer_msg()
1328 dev_err(i2c_dev->dev, "DMA transfer timed out\n"); in tegra_i2c_xfer_msg()
1330 return -ETIMEDOUT; in tegra_i2c_xfer_msg()
1333 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) { in tegra_i2c_xfer_msg()
1334 dma_sync_single_for_cpu(i2c_dev->dma_dev, in tegra_i2c_xfer_msg()
1335 i2c_dev->dma_phys, in tegra_i2c_xfer_msg()
1338 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len); in tegra_i2c_xfer_msg()
1342 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, in tegra_i2c_xfer_msg()
1348 dev_err(i2c_dev->dev, "I2C transfer timed out\n"); in tegra_i2c_xfer_msg()
1350 return -ETIMEDOUT; in tegra_i2c_xfer_msg()
1353 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", in tegra_i2c_xfer_msg()
1354 time_left, completion_done(&i2c_dev->msg_complete), in tegra_i2c_xfer_msg()
1355 i2c_dev->msg_err); in tegra_i2c_xfer_msg()
1357 i2c_dev->dma_mode = false; in tegra_i2c_xfer_msg()
1372 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_xfer()
1374 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); in tegra_i2c_xfer()
1375 pm_runtime_put_noidle(i2c_dev->dev); in tegra_i2c_xfer()
1382 if (i < (num - 1)) { in tegra_i2c_xfer()
1394 pm_runtime_put(i2c_dev->dev); in tegra_i2c_xfer()
1405 i2c_dev->atomic_mode = true; in tegra_i2c_xfer_atomic()
1407 i2c_dev->atomic_mode = false; in tegra_i2c_xfer_atomic()
1418 if (i2c_dev->hw->has_continue_xfer_support) in tegra_i2c_func()
1434 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1439 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1615 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1616 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1617 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1618 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1619 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1620 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1621 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1622 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1623 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1630 struct device_node *np = i2c_dev->dev->of_node; in tegra_i2c_parse_dt()
1634 err = of_property_read_u32(np, "clock-frequency", in tegra_i2c_parse_dt()
1635 &i2c_dev->bus_clk_rate); in tegra_i2c_parse_dt()
1637 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ; in tegra_i2c_parse_dt()
1639 multi_mode = of_property_read_bool(np, "multi-master"); in tegra_i2c_parse_dt()
1640 i2c_dev->multimaster_mode = multi_mode; in tegra_i2c_parse_dt()
1642 if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc")) in tegra_i2c_parse_dt()
1643 i2c_dev->is_dvc = true; in tegra_i2c_parse_dt()
1645 if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi")) in tegra_i2c_parse_dt()
1646 i2c_dev->is_vi = true; in tegra_i2c_parse_dt()
1653 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk"; in tegra_i2c_init_clocks()
1655 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw) in tegra_i2c_init_clocks()
1656 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk"; in tegra_i2c_init_clocks()
1658 if (i2c_dev->is_vi) in tegra_i2c_init_clocks()
1659 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow"; in tegra_i2c_init_clocks()
1661 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks, in tegra_i2c_init_clocks()
1662 i2c_dev->clocks); in tegra_i2c_init_clocks()
1666 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_init_clocks()
1670 i2c_dev->div_clk = i2c_dev->clocks[0].clk; in tegra_i2c_init_clocks()
1672 if (!i2c_dev->multimaster_mode) in tegra_i2c_init_clocks()
1675 err = clk_enable(i2c_dev->div_clk); in tegra_i2c_init_clocks()
1677 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err); in tegra_i2c_init_clocks()
1684 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_init_clocks()
1691 if (i2c_dev->multimaster_mode) in tegra_i2c_release_clocks()
1692 clk_disable(i2c_dev->div_clk); in tegra_i2c_release_clocks()
1694 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_release_clocks()
1701 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_init_hardware()
1703 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret); in tegra_i2c_init_hardware()
1707 pm_runtime_put(i2c_dev->dev); in tegra_i2c_init_hardware()
1718 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in tegra_i2c_probe()
1720 return -ENOMEM; in tegra_i2c_probe()
1724 init_completion(&i2c_dev->msg_complete); in tegra_i2c_probe()
1725 init_completion(&i2c_dev->dma_complete); in tegra_i2c_probe()
1727 i2c_dev->hw = of_device_get_match_data(&pdev->dev); in tegra_i2c_probe()
1728 i2c_dev->cont_id = pdev->id; in tegra_i2c_probe()
1729 i2c_dev->dev = &pdev->dev; in tegra_i2c_probe()
1731 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in tegra_i2c_probe()
1732 if (IS_ERR(i2c_dev->base)) in tegra_i2c_probe()
1733 return PTR_ERR(i2c_dev->base); in tegra_i2c_probe()
1735 i2c_dev->base_phys = res->start; in tegra_i2c_probe()
1741 i2c_dev->irq = err; in tegra_i2c_probe()
1744 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN); in tegra_i2c_probe()
1746 err = devm_request_irq(i2c_dev->dev, i2c_dev->irq, tegra_i2c_isr, in tegra_i2c_probe()
1747 IRQF_NO_SUSPEND, dev_name(i2c_dev->dev), in tegra_i2c_probe()
1752 i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c"); in tegra_i2c_probe()
1753 if (IS_ERR(i2c_dev->rst)) { in tegra_i2c_probe()
1754 dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst), in tegra_i2c_probe()
1756 return PTR_ERR(i2c_dev->rst); in tegra_i2c_probe()
1770 * VI I2C is in VE power domain which is not always ON and not in tegra_i2c_probe()
1771 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a in tegra_i2c_probe()
1772 * non IRQ-safe domain because this prevents powering off the power in tegra_i2c_probe()
1775 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't in tegra_i2c_probe()
1778 if (!i2c_dev->is_vi) in tegra_i2c_probe()
1779 pm_runtime_irq_safe(i2c_dev->dev); in tegra_i2c_probe()
1781 pm_runtime_enable(i2c_dev->dev); in tegra_i2c_probe()
1787 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); in tegra_i2c_probe()
1788 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node; in tegra_i2c_probe()
1789 i2c_dev->adapter.dev.parent = i2c_dev->dev; in tegra_i2c_probe()
1790 i2c_dev->adapter.retries = 1; in tegra_i2c_probe()
1791 i2c_dev->adapter.timeout = 6 * HZ; in tegra_i2c_probe()
1792 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; in tegra_i2c_probe()
1793 i2c_dev->adapter.owner = THIS_MODULE; in tegra_i2c_probe()
1794 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; in tegra_i2c_probe()
1795 i2c_dev->adapter.algo = &tegra_i2c_algo; in tegra_i2c_probe()
1796 i2c_dev->adapter.nr = pdev->id; in tegra_i2c_probe()
1798 if (i2c_dev->hw->supports_bus_clear) in tegra_i2c_probe()
1799 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info; in tegra_i2c_probe()
1801 strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev), in tegra_i2c_probe()
1802 sizeof(i2c_dev->adapter.name)); in tegra_i2c_probe()
1804 err = i2c_add_numbered_adapter(&i2c_dev->adapter); in tegra_i2c_probe()
1811 pm_runtime_disable(i2c_dev->dev); in tegra_i2c_probe()
1824 i2c_del_adapter(&i2c_dev->adapter); in tegra_i2c_remove()
1825 pm_runtime_disable(i2c_dev->dev); in tegra_i2c_remove()
1842 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_resume()
1847 * VI I2C device is attached to VE power domain which goes through in tegra_i2c_runtime_resume()
1849 * controller needs to be re-initialized after power ON. in tegra_i2c_runtime_resume()
1851 if (i2c_dev->is_vi) { in tegra_i2c_runtime_resume()
1860 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_resume()
1869 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks); in tegra_i2c_runtime_suspend()
1879 i2c_mark_adapter_suspended(&i2c_dev->adapter); in tegra_i2c_suspend()
1918 i2c_mark_adapter_resumed(&i2c_dev->adapter); in tegra_i2c_resume()
1933 .name = "tegra-i2c",
1940 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");