Lines Matching +full:30 +full:mhz

6  *  linux/drivers/ide/pdc202xx.c	Version 0.35	Mar. 30, 2002
91  * ATA Timing Tables based on 133 MHz PLL output clock.
93  * If the PLL outputs 100 MHz clock, the ASIC hardware will set
95  * issued to the device. However, if the PLL output clock is 133 MHz,
137 	 * automatically set the timing registers based on 100 MHz PLL output.  in pdcnew_set_dma_mode()
139 	 * As we set up the PLL to output 133 MHz for UltraDMA/133 capable  in pdcnew_set_dma_mode()
223 		 * The 30-bit decrementing counter is read in 4 pieces.  in read_counter()
238  * E.g. 16949000 on 33 MHz PCI bus, i.e. half of the PCI clock.
270 	 * (the clock counter is 30 bit wide and counts down)  in detect_pll_input_clock()
316 		case 4: /* it's 133 MHz for Ultra133 chips */  in init_chipset_pdcnew()
319 		case 3: /* and  100 MHz for Ultra100 chips */  in init_chipset_pdcnew()
328 	 * (e.g. 25 or 40 MHz), we have to adjust the cycle time.  in init_chipset_pdcnew()
402 	mdelay(30);  in init_chipset_pdcnew()