2  *  Copyright (c) 1997-1998  Mark Lord
7  *  June 22, 2004 - get rid of check_region
8  *                   - Jesper Juhl
13  * This module provides support for the bus-master IDE DMA function
14  * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
15  * including a "Precision Instruments" board.  The TRM290 pre-dates
16  * the sff-8038 standard (ide-dma.c) by a few months, and differs
18  * while re-using others from ide-dma.c.
22  * Works reliably for me in DMA mode (READs only),
23  * DMA WRITEs are disabled by default (see #define below);
25  * DMA is not enabled automatically for this chipset,
26  * but can be turned on manually (with "hdparm -d1") at run time.
33 #define TRM290_NO_DMA_WRITES	/* DMA writes seem unreliable sometimes */
36  * TRM-290 PCI-IDE2 Bus Master Chip
41  * trm290_base depends on jumper settings, and is probed for by ide-dma.c
43  * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
45  *	bits6-2 undefined
47  *	bit0 1=test_mode, 0=normal(default)
49  * trm290_base+2 when READ: status register (byte, read-only)
50  *	bits7-2 undefined
55  *	bits7-5 undefined
59  *	bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
60  *	bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
63  *	bit7 1=autoincrement CPR bits 2-0 after each access of CDR
64  *	bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
65  *	bit5 0=enabled master burst access (default), 1=disable  (write only)
66  *	bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
68  *	bits2-0 register index for accesses through CDR port
72  *	selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
75  * Index-0 Base address register for command block (word)
78  * Index-1 general config register (byte)
79  *	bit7 1=DMA enable, 0=DMA disable
80  *	bit6 1=activate IDE_RESET, 0=no action (default)
81  *	bit5 1=enable IORDY, 0=disable IORDY (default)
82  *	bit4 0=16-bit data port(default), 1=8-bit (XT) data port
83  *	bit3 interrupt polarity: 1=active_low, 0=active_high(default)
84  *	bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
85  *	bit1 bus_master_mode(?): 1=enable, 0=disable(default)
86  *	bit0 enable_io_ports: 1=enable(default), 0=disable
88  * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
89  *	bits7-0 bits7-0 of readahead count
91  * Index-3 read-ahead config register (byte, write only)
92  *	bit7 1=enable_readahead, 0=disable_readahead(default)
95  *	bit4 mode4 timing control: 1=enable, 0=disable(default)
98  *	bits1-0 bits9-8 of read-ahead count
100  * Index-4 base address register for control block (word)
103  * Index-5 data port timings (shared by both drives) (byte)
104  *	standard PCI "clk" (clock) counts, default value = 0xf5
106  *	bits7-6 setup time:  00=1clk, 01=2clk, 10=3clk, 11=4clk
107  *	bits5-3 hold time:	000=1clk, 001=2clk, 010=3clk,
110  *	bits2-0 active time:	000=2clk, 001=3clk, 010=4clk,
114  * Index-6 command/control port timings (shared by both drives) (byte)
115  *	same layout as Index-5, default value = 0xde
147 	ide_hwif_t *hwif = drive->hwif;  in trm290_prepare_drive()
151 	/* select PIO or DMA */  in trm290_prepare_drive()
156 	if (reg != hwif->select_data) {  in trm290_prepare_drive()
157 		hwif->select_data = reg;  in trm290_prepare_drive()
158 		/* set PIO/DMA */  in trm290_prepare_drive()
159 		outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);  in trm290_prepare_drive()
160 		outw(reg & 0xff, hwif->config_data);  in trm290_prepare_drive()
164 	if (drive->dev_flags & IDE_DFLAG_PRESENT) {  in trm290_prepare_drive()
165 		reg = inw(hwif->config_data + 3);  in trm290_prepare_drive()
167 		reg &= ~(1 << hwif->channel);  in trm290_prepare_drive()
168 		outw(reg, hwif->config_data + 3);  in trm290_prepare_drive()
176 	trm290_prepare_drive(drive, !!(drive->dev_flags & IDE_DFLAG_USING_DMA));  in trm290_dev_select()
178 	outb(drive->select | ATA_DEVICE_OBS, drive->hwif->io_ports.device_addr);  in trm290_dev_select()
183 	if (cmd->tf_flags & IDE_TFLAG_WRITE) {  in trm290_dma_check()
194 	ide_hwif_t *hwif = drive->hwif;  in trm290_dma_setup()
195 	unsigned int count, rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 1 : 2;  in trm290_dma_setup()
199 		/* try PIO instead of DMA */  in trm290_dma_setup()
202 	outl(hwif->dmatable_dma | rw, hwif->dma_base);  in trm290_dma_setup()
203 	/* start DMA */  in trm290_dma_setup()
204 	outw(count * 2 - 1, hwif->dma_base + 2);  in trm290_dma_setup()
216 	u16 status = inw(drive->hwif->dma_base + 2);  in trm290_dma_end()
225 	u16 status = inw(drive->hwif->dma_base + 2);  in trm290_dma_test_irq()
236 	struct pci_dev *dev	= to_pci_dev(hwif->dev);  in init_hwif_trm290()
241 	if ((dev->class & 5) && cfg_base)  in init_hwif_trm290()
245 		printk(KERN_INFO DRV_NAME " %s: using default", pci_name(dev));  in init_hwif_trm290()
248 	hwif->config_data = cfg_base;  in init_hwif_trm290()
249 	hwif->dma_base = (cfg_base + 4) ^ (hwif->channel ? 0x80 : 0);  in init_hwif_trm290()
251 	printk(KERN_INFO "    %s: BM-DMA at 0x%04lx-0x%04lx\n",  in init_hwif_trm290()
252 	       hwif->name, hwif->dma_base, hwif->dma_base + 3);  in init_hwif_trm290()
258 	/* put config reg into first byte of hwif->select_data */  in init_hwif_trm290()
259 	outb(0x51 | (hwif->channel << 3), hwif->config_data + 1);  in init_hwif_trm290()
260 	/* select PIO as default */  in init_hwif_trm290()
261 	hwif->select_data = 0x21;  in init_hwif_trm290()
262 	outb(hwif->select_data, hwif->config_data);  in init_hwif_trm290()
264 	reg = inb(hwif->config_data + 3);  in init_hwif_trm290()
267 	outb(reg, hwif->config_data + 3);  in init_hwif_trm290()
272 		hwif->irq = hwif->channel ? 15 : 14;  in init_hwif_trm290()
277 	 * My trm290-based card doesn't seem to work with all possible values  in init_hwif_trm290()
279 	 * values that are known to work.  Ugh.		-ml  in init_hwif_trm290()
281 		u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;  in init_hwif_trm290()
285 		outb(0x54 | (hwif->channel << 3), hwif->config_data + 1);  in init_hwif_trm290()
286 		old = inw(hwif->config_data);  in init_hwif_trm290()
292 			hwif->io_ports.ctl_addr = compat + 2;  in init_hwif_trm290()
293 			outw(compat | 1, hwif->config_data);  in init_hwif_trm290()
294 			new = inw(hwif->config_data);  in init_hwif_trm290()
297 				hwif->name, old, new & ~1);  in init_hwif_trm290()