Lines Matching +full:iommu +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for MTK architected m4u v1 implementations
5 * Copyright (c) 2015-2016 MediaTek Inc.
8 * Based on driver/iommu/mtk_iommu.c
15 #include <linux/dma-mapping.h>
16 #include <linux/dma-iommu.h>
20 #include <linux/iommu.h>
31 #include <asm/dma-iommu.h>
33 #include <dt-bindings/memory/mt2701-larb-port.h>
79 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
81 /* MTK generation one iommu HW only support 4K size mapping */
113 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) in mt2701_m4u_to_larb()
124 return id - mt2701_m4u_in_larb[larb]; in mt2701_m4u_to_port()
130 data->base + REG_MMU_INV_SEL); in mtk_iommu_tlb_flush_all()
131 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); in mtk_iommu_tlb_flush_all()
142 data->base + REG_MMU_INV_SEL); in mtk_iommu_tlb_flush_range()
144 data->base + REG_MMU_INVLD_START_A); in mtk_iommu_tlb_flush_range()
145 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, in mtk_iommu_tlb_flush_range()
146 data->base + REG_MMU_INVLD_END_A); in mtk_iommu_tlb_flush_range()
147 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); in mtk_iommu_tlb_flush_range()
149 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, in mtk_iommu_tlb_flush_range()
152 dev_warn(data->dev, in mtk_iommu_tlb_flush_range()
157 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); in mtk_iommu_tlb_flush_range()
163 struct mtk_iommu_domain *dom = data->m4u_dom; in mtk_iommu_isr()
168 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); in mtk_iommu_isr()
169 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); in mtk_iommu_isr()
172 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); in mtk_iommu_isr()
173 regval = readl_relaxed(data->base + REG_MMU_INT_ID); in mtk_iommu_isr()
178 * MTK v1 iommu HW could not determine whether the fault is read or in mtk_iommu_isr()
181 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, in mtk_iommu_isr()
183 dev_err_ratelimited(data->dev, in mtk_iommu_isr()
189 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); in mtk_iommu_isr()
191 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); in mtk_iommu_isr()
206 for (i = 0; i < fwspec->num_ids; ++i) { in mtk_iommu_config()
207 larbid = mt2701_m4u_to_larb(fwspec->ids[i]); in mtk_iommu_config()
208 portid = mt2701_m4u_to_port(fwspec->ids[i]); in mtk_iommu_config()
209 larb_mmu = &data->larb_imu[larbid]; in mtk_iommu_config()
211 dev_dbg(dev, "%s iommu port: %d\n", in mtk_iommu_config()
215 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); in mtk_iommu_config()
217 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); in mtk_iommu_config()
223 struct mtk_iommu_domain *dom = data->m4u_dom; in mtk_iommu_domain_finalise()
225 spin_lock_init(&dom->pgtlock); in mtk_iommu_domain_finalise()
227 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE, in mtk_iommu_domain_finalise()
228 &dom->pgt_pa, GFP_KERNEL); in mtk_iommu_domain_finalise()
229 if (!dom->pgt_va) in mtk_iommu_domain_finalise()
230 return -ENOMEM; in mtk_iommu_domain_finalise()
232 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_domain_finalise()
234 dom->data = data; in mtk_iommu_domain_finalise()
250 return &dom->domain; in mtk_iommu_domain_alloc()
256 struct mtk_iommu_data *data = dom->data; in mtk_iommu_domain_free()
258 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, in mtk_iommu_domain_free()
259 dom->pgt_va, dom->pgt_pa); in mtk_iommu_domain_free()
272 mtk_mapping = data->mapping; in mtk_iommu_attach_device()
273 if (mtk_mapping->domain != domain) in mtk_iommu_attach_device()
276 if (!data->m4u_dom) { in mtk_iommu_attach_device()
277 data->m4u_dom = dom; in mtk_iommu_attach_device()
280 data->m4u_dom = NULL; in mtk_iommu_attach_device()
304 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); in mtk_iommu_map()
308 spin_lock_irqsave(&dom->pgtlock, flags); in mtk_iommu_map()
319 spin_unlock_irqrestore(&dom->pgtlock, flags); in mtk_iommu_map()
321 mtk_iommu_tlb_flush_range(dom->data, iova, size); in mtk_iommu_map()
323 return map_size == size ? 0 : -EEXIST; in mtk_iommu_map()
332 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); in mtk_iommu_unmap()
335 spin_lock_irqsave(&dom->pgtlock, flags); in mtk_iommu_unmap()
337 spin_unlock_irqrestore(&dom->pgtlock, flags); in mtk_iommu_unmap()
339 mtk_iommu_tlb_flush_range(dom->data, iova, size); in mtk_iommu_unmap()
351 spin_lock_irqsave(&dom->pgtlock, flags); in mtk_iommu_iova_to_phys()
352 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); in mtk_iommu_iova_to_phys()
353 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); in mtk_iommu_iova_to_phys()
354 spin_unlock_irqrestore(&dom->pgtlock, flags); in mtk_iommu_iova_to_phys()
362 * MTK generation one iommu HW only support one iommu domain, and all the client
374 if (args->args_count != 1) { in mtk_iommu_create_mapping()
375 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", in mtk_iommu_create_mapping()
376 args->args_count); in mtk_iommu_create_mapping()
377 return -EINVAL; in mtk_iommu_create_mapping()
381 ret = iommu_fwspec_init(dev, &args->np->fwnode, &mtk_iommu_ops); in mtk_iommu_create_mapping()
385 } else if (dev_iommu_fwspec_get(dev)->ops != &mtk_iommu_ops) { in mtk_iommu_create_mapping()
386 return -EINVAL; in mtk_iommu_create_mapping()
391 m4updev = of_find_device_by_node(args->np); in mtk_iommu_create_mapping()
393 return -EINVAL; in mtk_iommu_create_mapping()
398 ret = iommu_fwspec_add_ids(dev, args->args, 1); in mtk_iommu_create_mapping()
403 mtk_mapping = data->mapping; in mtk_iommu_create_mapping()
405 /* MTK iommu support 4GB iova address space. */ in mtk_iommu_create_mapping()
411 data->mapping = mtk_mapping; in mtk_iommu_create_mapping()
430 of_for_each_phandle(&it, err, dev->of_node, "iommus", in mtk_iommu_probe_device()
431 "#iommu-cells", -1) { in mtk_iommu_probe_device()
439 /* dev->iommu_fwspec might have changed */ in mtk_iommu_probe_device()
445 if (!fwspec || fwspec->ops != &mtk_iommu_ops) in mtk_iommu_probe_device()
446 return ERR_PTR(-ENODEV); /* Not a iommu client device */ in mtk_iommu_probe_device()
450 return &data->iommu; in mtk_iommu_probe_device()
460 mtk_mapping = data->mapping; in mtk_iommu_probe_finalize()
464 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); in mtk_iommu_probe_finalize()
471 if (!fwspec || fwspec->ops != &mtk_iommu_ops) in mtk_iommu_release_device()
482 ret = clk_prepare_enable(data->bclk); in mtk_iommu_hw_init()
484 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); in mtk_iommu_hw_init()
489 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
499 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); in mtk_iommu_hw_init()
502 writel_relaxed(data->protect_base, in mtk_iommu_hw_init()
503 data->base + REG_MMU_IVRP_PADDR); in mtk_iommu_hw_init()
505 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); in mtk_iommu_hw_init()
507 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, in mtk_iommu_hw_init()
508 dev_name(data->dev), (void *)data)) { in mtk_iommu_hw_init()
509 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_hw_init()
510 clk_disable_unprepare(data->bclk); in mtk_iommu_hw_init()
511 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); in mtk_iommu_hw_init()
512 return -ENODEV; in mtk_iommu_hw_init()
535 { .compatible = "mediatek,mt2701-m4u", },
547 struct device *dev = &pdev->dev; in mtk_iommu_probe()
557 return -ENOMEM; in mtk_iommu_probe()
559 data->dev = dev; in mtk_iommu_probe()
565 return -ENOMEM; in mtk_iommu_probe()
566 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); in mtk_iommu_probe()
569 data->base = devm_ioremap_resource(dev, res); in mtk_iommu_probe()
570 if (IS_ERR(data->base)) in mtk_iommu_probe()
571 return PTR_ERR(data->base); in mtk_iommu_probe()
573 data->irq = platform_get_irq(pdev, 0); in mtk_iommu_probe()
574 if (data->irq < 0) in mtk_iommu_probe()
575 return data->irq; in mtk_iommu_probe()
577 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_probe()
578 if (IS_ERR(data->bclk)) in mtk_iommu_probe()
579 return PTR_ERR(data->bclk); in mtk_iommu_probe()
582 of_for_each_phandle(&it, err, dev->of_node, in mtk_iommu_probe()
602 return -EPROBE_DEFER; in mtk_iommu_probe()
606 data->larb_imu[larb_nr].dev = &plarbdev->dev; in mtk_iommu_probe()
618 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, in mtk_iommu_probe()
619 dev_name(&pdev->dev)); in mtk_iommu_probe()
623 iommu_device_set_ops(&data->iommu, &mtk_iommu_ops); in mtk_iommu_probe()
625 ret = iommu_device_register(&data->iommu); in mtk_iommu_probe()
643 iommu_device_unregister(&data->iommu); in mtk_iommu_probe()
645 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_probe()
647 clk_disable_unprepare(data->bclk); in mtk_iommu_probe()
655 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_remove()
656 iommu_device_unregister(&data->iommu); in mtk_iommu_remove()
661 clk_disable_unprepare(data->bclk); in mtk_iommu_remove()
662 devm_free_irq(&pdev->dev, data->irq, data); in mtk_iommu_remove()
663 component_master_del(&pdev->dev, &mtk_iommu_com_ops); in mtk_iommu_remove()
670 struct mtk_iommu_suspend_reg *reg = &data->reg; in mtk_iommu_suspend()
671 void __iomem *base = data->base; in mtk_iommu_suspend()
673 reg->standard_axi_mode = readl_relaxed(base + in mtk_iommu_suspend()
675 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); in mtk_iommu_suspend()
676 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); in mtk_iommu_suspend()
677 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); in mtk_iommu_suspend()
684 struct mtk_iommu_suspend_reg *reg = &data->reg; in mtk_iommu_resume()
685 void __iomem *base = data->base; in mtk_iommu_resume()
687 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_resume()
688 writel_relaxed(reg->standard_axi_mode, in mtk_iommu_resume()
690 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); in mtk_iommu_resume()
691 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); in mtk_iommu_resume()
692 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); in mtk_iommu_resume()
693 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); in mtk_iommu_resume()
705 .name = "mtk-iommu-v1",