1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright (C) 2014-2024 Broadcom
35 /* Register offsets in the L2 latched interrupt controller */
45 /* Register offsets in the L2 level interrupt controller */
49 	.cpu_clear		= -1, /* Register not present */
55 /* L2 intc private data structure */
66  * brcmstb_l2_mask_and_ack - Mask and ack pending interrupt
82 	u32 mask = d->mask;  in brcmstb_l2_mask_and_ack()
85 	irq_reg_writel(gc, mask, ct->regs.disable);  in brcmstb_l2_mask_and_ack()
86 	*ct->mask_cache &= ~mask;  in brcmstb_l2_mask_and_ack()
87 	irq_reg_writel(gc, mask, ct->regs.ack);  in brcmstb_l2_mask_and_ack()
100 	status = irq_reg_readl(b->gc, b->status_offset) &  in brcmstb_l2_intc_irq_handle()
101 		~(irq_reg_readl(b->gc, b->mask_offset));  in brcmstb_l2_intc_irq_handle()
104 		raw_spin_lock(&desc->lock);  in brcmstb_l2_intc_irq_handle()
106 		raw_spin_unlock(&desc->lock);  in brcmstb_l2_intc_irq_handle()
111 		irq = ffs(status) - 1;  in brcmstb_l2_intc_irq_handle()
113 		generic_handle_irq(irq_linear_revmap(b->domain, irq));  in brcmstb_l2_intc_irq_handle()
126 	struct brcmstb_l2_intc_data *b = gc->private;  in brcmstb_l2_intc_suspend()
131 	b->saved_mask = irq_reg_readl(gc, ct->regs.mask);  in brcmstb_l2_intc_suspend()
133 	if (b->can_wake) {  in brcmstb_l2_intc_suspend()
135 		irq_reg_writel(gc, ~gc->wake_active, ct->regs.disable);  in brcmstb_l2_intc_suspend()
136 		irq_reg_writel(gc, gc->wake_active, ct->regs.enable);  in brcmstb_l2_intc_suspend()
145 	struct brcmstb_l2_intc_data *b = gc->private;  in brcmstb_l2_intc_resume()
149 	if (ct->chip.irq_ack) {  in brcmstb_l2_intc_resume()
150 		/* Clear unmasked non-wakeup interrupts */  in brcmstb_l2_intc_resume()
151 		irq_reg_writel(gc, ~b->saved_mask & ~gc->wake_active,  in brcmstb_l2_intc_resume()
152 				ct->regs.ack);  in brcmstb_l2_intc_resume()
156 	irq_reg_writel(gc, b->saved_mask, ct->regs.disable);  in brcmstb_l2_intc_resume()
157 	irq_reg_writel(gc, ~b->saved_mask, ct->regs.enable);  in brcmstb_l2_intc_resume()
177 		return -ENOMEM;  in brcmstb_l2_intc_of_init()
181 		pr_err("failed to remap intc L2 registers\n");  in brcmstb_l2_intc_of_init()
182 		ret = -ENOMEM;  in brcmstb_l2_intc_of_init()
187 	writel(0xffffffff, base + init_params->cpu_mask_set);  in brcmstb_l2_intc_of_init()
190 	data->can_wake = of_property_read_bool(np, "brcm,irq-can-wake");  in brcmstb_l2_intc_of_init()
191 	if (!data->can_wake && (init_params->cpu_clear >= 0))  in brcmstb_l2_intc_of_init()
192 		writel(0xffffffff, base + init_params->cpu_clear);  in brcmstb_l2_intc_of_init()
197 		ret = -EINVAL;  in brcmstb_l2_intc_of_init()
201 	data->domain = irq_domain_add_linear(np, 32,  in brcmstb_l2_intc_of_init()
203 	if (!data->domain) {  in brcmstb_l2_intc_of_init()
204 		ret = -ENOMEM;  in brcmstb_l2_intc_of_init()
209 	 * peripheral registers for CPU-native byte order.  in brcmstb_l2_intc_of_init()
215 	if (init_params->handler == handle_level_irq)  in brcmstb_l2_intc_of_init()
219 	ret = irq_alloc_domain_generic_chips(data->domain, 32, 1,  in brcmstb_l2_intc_of_init()
220 			np->full_name, init_params->handler, clr, set, flags);  in brcmstb_l2_intc_of_init()
230 	data->gc = irq_get_domain_generic_chip(data->domain, 0);  in brcmstb_l2_intc_of_init()
231 	data->gc->reg_base = base;  in brcmstb_l2_intc_of_init()
232 	data->gc->private = data;  in brcmstb_l2_intc_of_init()
233 	data->status_offset = init_params->cpu_status;  in brcmstb_l2_intc_of_init()
234 	data->mask_offset = init_params->cpu_mask_status;  in brcmstb_l2_intc_of_init()
236 	ct = data->gc->chip_types;  in brcmstb_l2_intc_of_init()
238 	if (init_params->cpu_clear >= 0) {  in brcmstb_l2_intc_of_init()
239 		ct->regs.ack = init_params->cpu_clear;  in brcmstb_l2_intc_of_init()
240 		ct->chip.irq_ack = irq_gc_ack_set_bit;  in brcmstb_l2_intc_of_init()
241 		ct->chip.irq_mask_ack = brcmstb_l2_mask_and_ack;  in brcmstb_l2_intc_of_init()
243 		/* No Ack - but still slightly more efficient to define this */  in brcmstb_l2_intc_of_init()
244 		ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;  in brcmstb_l2_intc_of_init()
247 	ct->chip.irq_mask = irq_gc_mask_disable_reg;  in brcmstb_l2_intc_of_init()
248 	ct->regs.disable = init_params->cpu_mask_set;  in brcmstb_l2_intc_of_init()
249 	ct->regs.mask = init_params->cpu_mask_status;  in brcmstb_l2_intc_of_init()
251 	ct->chip.irq_unmask = irq_gc_unmask_enable_reg;  in brcmstb_l2_intc_of_init()
252 	ct->regs.enable = init_params->cpu_mask_clear;  in brcmstb_l2_intc_of_init()
254 	ct->chip.irq_suspend = brcmstb_l2_intc_suspend;  in brcmstb_l2_intc_of_init()
255 	ct->chip.irq_resume = brcmstb_l2_intc_resume;  in brcmstb_l2_intc_of_init()
256 	ct->chip.irq_pm_shutdown = brcmstb_l2_intc_suspend;  in brcmstb_l2_intc_of_init()
258 	if (data->can_wake) {  in brcmstb_l2_intc_of_init()
262 		data->gc->wake_enabled = 0xffffffff;  in brcmstb_l2_intc_of_init()
263 		ct->chip.irq_set_wake = irq_gc_set_wake;  in brcmstb_l2_intc_of_init()
267 	pr_info("registered L2 intc (%pOF, parent irq: %d)\n", np, parent_irq);  in brcmstb_l2_intc_of_init()
272 	irq_domain_remove(data->domain);  in brcmstb_l2_intc_of_init()
285 IRQCHIP_DECLARE(brcmstb_l2_intc, "brcm,l2-intc", brcmstb_l2_edge_intc_of_init);
286 IRQCHIP_DECLARE(brcmstb_hif_spi_l2_intc, "brcm,hif-spi-l2-intc",
288 IRQCHIP_DECLARE(brcmstb_upg_aux_aon_l2_intc, "brcm,upg-aux-aon-l2-intc",
296 IRQCHIP_DECLARE(bcm7271_l2_intc, "brcm,bcm7271-l2-intc",