Lines Matching +full:non +full:- +full:secure +full:- +full:domain
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
23 #include <linux/irqchip/arm-gic-common.h>
24 #include <linux/irqchip/arm-gic-v3.h>
25 #include <linux/irqchip/irq-partition-percpu.h>
32 #include "irq-gic-common.h"
53 struct irq_domain *domain; member
71 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
75 * When security is enabled, non-secure priority values from the (re)distributor
79 * If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
85 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
87 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
105 * When the Non-secure world has access to group 0 interrupts (as a
110 * written by software is moved to the Non-secure range by the Distributor.
133 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
171 return __get_intid_range(d->hwirq); in get_intid_range()
176 return d->hwirq; in gic_irq()
197 /* SGI+PPI -> SGI_base for this CPU */ in gic_dist_base()
202 /* SPI -> dist_base */ in gic_dist_base()
215 count--; in gic_do_wait_for_rwp()
273 while (--count) { in gic_enable_redist()
294 *index = d->hwirq; in convert_offset_index()
302 *index = d->hwirq - EPPI_BASE_INTID + 32; in convert_offset_index()
305 *index = d->hwirq - ESPI_BASE_INTID; in convert_offset_index()
334 *index = d->hwirq; in convert_offset_index()
411 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ in gic_irq_set_irqchip_state()
412 return -EINVAL; in gic_irq_set_irqchip_state()
428 return -EINVAL; in gic_irq_set_irqchip_state()
438 if (d->hwirq >= 8192) /* PPI/SPI only */ in gic_irq_get_irqchip_state()
439 return -EINVAL; in gic_irq_get_irqchip_state()
455 return -EINVAL; in gic_irq_get_irqchip_state()
475 return d->hwirq - 16; in gic_get_ppi_index()
477 return d->hwirq - EPPI_BASE_INTID + 16; in gic_get_ppi_index()
485 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_setup()
488 return -EINVAL; in gic_irq_nmi_setup()
491 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_setup()
492 return -EINVAL; in gic_irq_nmi_setup()
500 return -EINVAL; in gic_irq_nmi_setup()
509 desc->handle_irq = handle_percpu_devid_fasteoi_nmi; in gic_irq_nmi_setup()
512 desc->handle_irq = handle_fasteoi_nmi; in gic_irq_nmi_setup()
522 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_teardown()
528 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_teardown()
545 desc->handle_irq = handle_percpu_devid_irq; in gic_irq_nmi_teardown()
547 desc->handle_irq = handle_fasteoi_irq; in gic_irq_nmi_teardown()
582 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; in gic_set_type()
587 return -EINVAL; in gic_set_type()
602 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); in gic_set_type()
612 return -EINVAL; in gic_irq_set_vcpu_affinity()
659 err = handle_domain_nmi(gic_data.domain, irqnr, regs); in gic_handle_nmi()
727 if (handle_domain_irq(gic_data.domain, irqnr, regs)) { in gic_handle_irq()
754 * setting the highest possible, non-zero priority in PMR. in gic_has_group0()
758 * actual priority in the non-secure range. In the process, it in gic_has_group0()
763 gic_write_pmr(BIT(8 - gic_get_pribits())); in gic_has_group0()
783 * Configure SPIs as non-secure Group-1. This will only matter in gic_dist_init()
785 * do the right thing if the kernel is running in secure mode, in gic_dist_init()
832 int ret = -ENODEV; in gic_iterate_rdists()
866 return ret ? -ENODEV : 0; in gic_iterate_rdists()
886 u64 offset = ptr - region->redist_base; in __gic_populate_rdist()
887 raw_spin_lock_init(&gic_data_rdist()->rd_lock); in __gic_populate_rdist()
889 gic_data_rdist()->phys_base = region->phys_base + offset; in __gic_populate_rdist()
893 (int)(region - gic_data.redist_regions), in __gic_populate_rdist()
894 &gic_data_rdist()->phys_base); in __gic_populate_rdist()
908 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", in gic_populate_rdist()
911 return -ENODEV; in gic_populate_rdist()
919 /* Boot-time cleanip */ in __gic_update_rdist_properties()
937 /* RVPEID implies some form of DirectLPI, no matter what the doc says... :-/ */ in __gic_update_rdist_properties()
943 /* Detect non-sensical configurations */ in __gic_update_rdist_properties()
1019 * any pre-emptive interrupts from working at all). Writing a zero in gic_cpu_sys_reg_init()
1088 * - The write is ignored. in gic_cpu_sys_reg_init()
1089 * - The RS field is treated as 0. in gic_cpu_sys_reg_init()
1128 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1171 cpu--; in gic_compute_target_list()
1203 if (WARN_ON(d->hwirq >= 16)) in gic_ipi_send_mask()
1217 gic_send_sgi(cluster_id, tlist, d->hwirq); in gic_ipi_send_mask()
1236 /* Register all 8 non-secure SGIs */ in gic_smp_init()
1237 base_sgi = __irq_domain_alloc_irqs(gic_data.domain, -1, 8, in gic_smp_init()
1261 return -EINVAL; in gic_set_affinity()
1264 return -EINVAL; in gic_set_affinity()
1378 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1386 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1392 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1400 return -EPERM; in gic_irq_domain_map()
1401 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1406 return -EPERM; in gic_irq_domain_map()
1419 if (fwspec->param_count == 1 && fwspec->param[0] < 16) { in gic_irq_domain_translate()
1420 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1425 if (is_of_node(fwspec->fwnode)) { in gic_irq_domain_translate()
1426 if (fwspec->param_count < 3) in gic_irq_domain_translate()
1427 return -EINVAL; in gic_irq_domain_translate()
1429 switch (fwspec->param[0]) { in gic_irq_domain_translate()
1431 *hwirq = fwspec->param[1] + 32; in gic_irq_domain_translate()
1434 *hwirq = fwspec->param[1] + 16; in gic_irq_domain_translate()
1437 *hwirq = fwspec->param[1] + ESPI_BASE_INTID; in gic_irq_domain_translate()
1440 *hwirq = fwspec->param[1] + EPPI_BASE_INTID; in gic_irq_domain_translate()
1443 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1446 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1447 if (fwspec->param[1] >= 16) in gic_irq_domain_translate()
1448 *hwirq += EPPI_BASE_INTID - 16; in gic_irq_domain_translate()
1453 return -EINVAL; in gic_irq_domain_translate()
1456 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in gic_irq_domain_translate()
1463 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); in gic_irq_domain_translate()
1467 if (is_fwnode_irqchip(fwspec->fwnode)) { in gic_irq_domain_translate()
1468 if(fwspec->param_count != 2) in gic_irq_domain_translate()
1469 return -EINVAL; in gic_irq_domain_translate()
1471 if (fwspec->param[0] < 16) { in gic_irq_domain_translate()
1473 fwspec->param[0]); in gic_irq_domain_translate()
1474 return -EINVAL; in gic_irq_domain_translate()
1477 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1478 *type = fwspec->param[1]; in gic_irq_domain_translate()
1484 return -EINVAL; in gic_irq_domain_translate()
1487 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, in gic_irq_domain_alloc() argument
1495 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); in gic_irq_domain_alloc()
1500 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); in gic_irq_domain_alloc()
1508 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, in gic_irq_domain_free() argument
1514 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); in gic_irq_domain_free()
1525 if (fwspec->fwnode != d->fwnode) in gic_irq_domain_select()
1528 /* If this is not DT, then we have a single domain */ in gic_irq_domain_select()
1529 if (!is_of_node(fwspec->fwnode)) in gic_irq_domain_select()
1533 * If this is a PPI and we have a 4th (non-null) parameter, in gic_irq_domain_select()
1534 * then we need to match the partition domain. in gic_irq_domain_select()
1536 if (fwspec->param_count >= 4 && in gic_irq_domain_select()
1537 fwspec->param[0] == 1 && fwspec->param[3] != 0 && in gic_irq_domain_select()
1539 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); in gic_irq_domain_select()
1541 return d == gic_data.domain; in gic_irq_domain_select()
1560 return -ENOMEM; in partition_domain_translate()
1562 np = of_find_node_by_phandle(fwspec->param[3]); in partition_domain_translate()
1564 return -EINVAL; in partition_domain_translate()
1566 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], in partition_domain_translate()
1572 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in partition_domain_translate()
1586 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; in gic_enable_quirk_msm8996()
1595 d->flags |= FLAGS_WORKAROUND_MTK_GICR_SAVE; in gic_enable_quirk_mtk_gicr()
1604 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; in gic_enable_quirk_cavium_38539()
1614 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite in gic_enable_quirk_hip06_07()
1616 * that GIC-600 doesn't have ESPI, so nothing to do in that case. in gic_enable_quirk_hip06_07()
1620 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { in gic_enable_quirk_hip06_07()
1622 d->rdists.gicd_typer &= ~GENMASK(9, 8); in gic_enable_quirk_hip06_07()
1632 .compatible = "qcom,msm8996-gic-v3",
1637 .property = "mediatek,broken-save-restore-fw",
1656 * - ThunderX: CN88xx
1657 * - OCTEON TX: CN83xx, CN81xx
1658 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1696 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", in gic_enable_nmi_support()
1702 * and if Group 0 interrupts can be delivered to Linux in the non-secure in gic_enable_nmi_support()
1708 * ----------------------------------------------------------- in gic_enable_nmi_support()
1709 * 1 | - | unchanged | unchanged in gic_enable_nmi_support()
1710 * ----------------------------------------------------------- in gic_enable_nmi_support()
1711 * 0 | 1 | non-secure | non-secure in gic_enable_nmi_support()
1712 * ----------------------------------------------------------- in gic_enable_nmi_support()
1713 * 0 | 0 | unchanged | non-secure in gic_enable_nmi_support()
1715 * where non-secure means that the value is right-shifted by one and the in gic_enable_nmi_support()
1716 * MSB bit set, to make it fit in the non-secure priority range. in gic_enable_nmi_support()
1723 * be in the non-secure range, we use a different PMR value to mask IRQs in gic_enable_nmi_support()
1767 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); in gic_init_bases()
1777 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, in gic_init_bases()
1785 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { in gic_init_bases()
1786 err = -ENOMEM; in gic_init_bases()
1790 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); in gic_init_bases()
1797 err = mbi_init(handle, gic_data.domain); in gic_init_bases()
1812 its_init(handle, &gic_data.rdists, gic_data.domain); in gic_init_bases()
1816 gicv2m_init(handle, gic_data.domain); in gic_init_bases()
1824 if (gic_data.domain) in gic_init_bases()
1825 irq_domain_remove(gic_data.domain); in gic_init_bases()
1835 return -ENODEV; in gic_validate_dist_version()
1848 parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); in gic_populate_ppi_partitions()
1871 part->partition_id = of_node_to_fwnode(child_part); in gic_populate_ppi_partitions()
1902 cpumask_set_cpu(cpu, &part->mask); in gic_populate_ppi_partitions()
1950 if (of_property_read_u32(node, "#redistributor-regions", in gic_of_setup_kvm_info()
1975 return -ENXIO; in gic_of_init()
1984 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) in gic_of_init()
1990 err = -ENOMEM; in gic_of_init()
2002 err = -ENODEV; in gic_of_init()
2008 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) in gic_of_init()
2014 redist_stride, &node->fwnode); in gic_of_init()
2034 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2068 redist_base = ioremap(redist->base_address, redist->length); in gic_acpi_parse_madt_redist()
2070 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); in gic_acpi_parse_madt_redist()
2071 return -ENOMEM; in gic_acpi_parse_madt_redist()
2074 gic_acpi_register_redist(redist->base_address, redist_base); in gic_acpi_parse_madt_redist()
2089 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_parse_madt_gicc()
2092 redist_base = ioremap(gicc->gicr_base_address, size); in gic_acpi_parse_madt_gicc()
2094 return -ENOMEM; in gic_acpi_parse_madt_gicc()
2096 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); in gic_acpi_parse_madt_gicc()
2118 return -ENODEV; in gic_acpi_collect_gicr_base()
2138 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { in gic_acpi_match_gicc()
2147 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_match_gicc()
2150 return -ENODEV; in gic_acpi_match_gicc()
2186 if (dist->version != ape->driver_data) in acpi_validate_gic_table()
2207 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_parse_virt_madt_gicc()
2210 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? in gic_acpi_parse_virt_madt_gicc()
2216 acpi_data.maint_irq = gicc->vgic_interrupt; in gic_acpi_parse_virt_madt_gicc()
2218 acpi_data.vcpu_base = gicc->gicv_base_address; in gic_acpi_parse_virt_madt_gicc()
2226 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || in gic_acpi_parse_virt_madt_gicc()
2228 (acpi_data.vcpu_base != gicc->gicv_base_address)) in gic_acpi_parse_virt_madt_gicc()
2229 return -EINVAL; in gic_acpi_parse_virt_madt_gicc()
2270 vcpu->flags = IORESOURCE_MEM; in gic_acpi_setup_kvm_info()
2271 vcpu->start = acpi_data.vcpu_base; in gic_acpi_setup_kvm_info()
2272 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; in gic_acpi_setup_kvm_info()
2290 acpi_data.dist_base = ioremap(dist->base_address, in gic_acpi_init()
2294 return -ENOMEM; in gic_acpi_init()
2307 err = -ENOMEM; in gic_acpi_init()
2315 domain_handle = irq_domain_alloc_fwnode(&dist->base_address); in gic_acpi_init()
2317 err = -ENOMEM; in gic_acpi_init()