Lines Matching +full:num +full:- +full:irqs
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2010-2013 Imagination Technologies Ltd.
66 * struct pdc_intc_priv - private pdc interrupt data.
71 * @domain: IRQ domain for PDC peripheral and syswake IRQs.
92 iowrite32(data, priv->pdc_base + reg_offs); in pdc_write()
98 return ioread32(priv->pdc_base + reg_offs); in pdc_read()
112 return hw - SYS0_HWIRQ; in hwirq_to_syswake()
122 return (struct pdc_intc_priv *)data->domain->host_data; in irqd_to_priv()
135 raw_spin_lock(&priv->lock); in perip_irq_mask()
136 priv->irq_route &= ~data->mask; in perip_irq_mask()
137 pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); in perip_irq_mask()
138 raw_spin_unlock(&priv->lock); in perip_irq_mask()
145 raw_spin_lock(&priv->lock); in perip_irq_unmask()
146 priv->irq_route |= data->mask; in perip_irq_unmask()
147 pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); in perip_irq_unmask()
148 raw_spin_unlock(&priv->lock); in perip_irq_unmask()
154 unsigned int syswake = hwirq_to_syswake(data->hwirq); in syswake_irq_set_type()
176 return -EINVAL; in syswake_irq_set_type()
179 raw_spin_lock(&priv->lock); in syswake_irq_set_type()
191 raw_spin_unlock(&priv->lock); in syswake_irq_set_type()
200 irq_hw_number_t hw = data->hwirq; in pdc_irq_set_wake()
204 raw_spin_lock(&priv->lock); in pdc_irq_set_wake()
206 priv->irq_route |= mask; in pdc_irq_set_wake()
208 priv->irq_route &= ~mask; in pdc_irq_set_wake()
209 pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); in pdc_irq_set_wake()
210 raw_spin_unlock(&priv->lock); in pdc_irq_set_wake()
214 dst_irq = priv->syswake_irq; in pdc_irq_set_wake()
216 dst_irq = priv->perip_irqs[hw]; in pdc_irq_set_wake()
231 for (i = 0; i < priv->nr_perips; ++i) in pdc_intc_perip_isr()
232 if (irq == priv->perip_irqs[i]) in pdc_intc_perip_isr()
240 irq_no = irq_linear_revmap(priv->domain, i); in pdc_intc_perip_isr()
254 status &= (1 << priv->nr_syswakes) - 1; in pdc_intc_syswake_isr()
261 irq_no = irq_linear_revmap(priv->domain, in pdc_intc_syswake_isr()
283 priv->irq_route = ((PDC_IRQ_ROUTE_EXT_EN_SYS0 << priv->nr_syswakes) - in pdc_intc_setup()
285 pdc_write(priv, PDC_IRQ_ROUTE, priv->irq_route); in pdc_intc_setup()
288 for (i = 0; i < priv->nr_syswakes; ++i) { in pdc_intc_setup()
300 struct device_node *node = pdev->dev.of_node; in pdc_intc_probe()
308 return -ENOENT; in pdc_intc_probe()
313 dev_err(&pdev->dev, "cannot find registers resource\n"); in pdc_intc_probe()
314 return -ENOENT; in pdc_intc_probe()
318 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); in pdc_intc_probe()
320 dev_err(&pdev->dev, "cannot allocate device data\n"); in pdc_intc_probe()
321 return -ENOMEM; in pdc_intc_probe()
323 raw_spin_lock_init(&priv->lock); in pdc_intc_probe()
327 priv->pdc_base = devm_ioremap(&pdev->dev, res_regs->start, in pdc_intc_probe()
329 if (!priv->pdc_base) in pdc_intc_probe()
330 return -EIO; in pdc_intc_probe()
333 ret = of_property_read_u32(node, "num-perips", &val); in pdc_intc_probe()
335 dev_err(&pdev->dev, "No num-perips node property found\n"); in pdc_intc_probe()
336 return -EINVAL; in pdc_intc_probe()
339 dev_err(&pdev->dev, "num-perips (%u) out of range\n", val); in pdc_intc_probe()
340 return -EINVAL; in pdc_intc_probe()
342 priv->nr_perips = val; in pdc_intc_probe()
345 ret = of_property_read_u32(node, "num-syswakes", &val); in pdc_intc_probe()
347 dev_err(&pdev->dev, "No num-syswakes node property found\n"); in pdc_intc_probe()
348 return -EINVAL; in pdc_intc_probe()
351 dev_err(&pdev->dev, "num-syswakes (%u) out of range\n", val); in pdc_intc_probe()
352 return -EINVAL; in pdc_intc_probe()
354 priv->nr_syswakes = val; in pdc_intc_probe()
357 priv->perip_irqs = devm_kcalloc(&pdev->dev, 4, priv->nr_perips, in pdc_intc_probe()
359 if (!priv->perip_irqs) { in pdc_intc_probe()
360 dev_err(&pdev->dev, "cannot allocate perip IRQ list\n"); in pdc_intc_probe()
361 return -ENOMEM; in pdc_intc_probe()
363 for (i = 0; i < priv->nr_perips; ++i) { in pdc_intc_probe()
367 priv->perip_irqs[i] = irq; in pdc_intc_probe()
371 dev_err(&pdev->dev, "surplus perip IRQs detected\n"); in pdc_intc_probe()
372 return -EINVAL; in pdc_intc_probe()
379 priv->syswake_irq = irq; in pdc_intc_probe()
382 priv->domain = irq_domain_add_linear(node, 16, &irq_generic_chip_ops, in pdc_intc_probe()
384 if (unlikely(!priv->domain)) { in pdc_intc_probe()
385 dev_err(&pdev->dev, "cannot add IRQ domain\n"); in pdc_intc_probe()
386 return -ENOMEM; in pdc_intc_probe()
391 * The first one for peripheral irqs (only 1 chip type used) in pdc_intc_probe()
392 * The second one for syswake irqs (edge and level chip types) in pdc_intc_probe()
394 ret = irq_alloc_domain_generic_chips(priv->domain, 8, 2, "pdc", in pdc_intc_probe()
402 gc = irq_get_domain_generic_chip(priv->domain, 0); in pdc_intc_probe()
403 gc->unused = ~(BIT(priv->nr_perips) - 1); in pdc_intc_probe()
404 gc->reg_base = priv->pdc_base; in pdc_intc_probe()
409 gc->chip_types[0].regs.mask = PDC_IRQ_ROUTE; in pdc_intc_probe()
410 gc->chip_types[0].chip.irq_mask = perip_irq_mask; in pdc_intc_probe()
411 gc->chip_types[0].chip.irq_unmask = perip_irq_unmask; in pdc_intc_probe()
412 gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake; in pdc_intc_probe()
416 gc = irq_get_domain_generic_chip(priv->domain, 8); in pdc_intc_probe()
417 gc->unused = ~(BIT(priv->nr_syswakes) - 1); in pdc_intc_probe()
418 gc->reg_base = priv->pdc_base; in pdc_intc_probe()
421 gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH; in pdc_intc_probe()
422 gc->chip_types[0].handler = handle_edge_irq; in pdc_intc_probe()
423 gc->chip_types[0].regs.ack = PDC_IRQ_CLEAR; in pdc_intc_probe()
424 gc->chip_types[0].regs.mask = PDC_IRQ_ENABLE; in pdc_intc_probe()
425 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; in pdc_intc_probe()
426 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; in pdc_intc_probe()
427 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; in pdc_intc_probe()
428 gc->chip_types[0].chip.irq_set_type = syswake_irq_set_type; in pdc_intc_probe()
429 gc->chip_types[0].chip.irq_set_wake = pdc_irq_set_wake; in pdc_intc_probe()
431 gc->chip_types[0].chip.flags = IRQCHIP_MASK_ON_SUSPEND; in pdc_intc_probe()
434 gc->chip_types[1].type = IRQ_TYPE_LEVEL_MASK; in pdc_intc_probe()
435 gc->chip_types[1].handler = handle_level_irq; in pdc_intc_probe()
436 gc->chip_types[1].regs.ack = PDC_IRQ_CLEAR; in pdc_intc_probe()
437 gc->chip_types[1].regs.mask = PDC_IRQ_ENABLE; in pdc_intc_probe()
438 gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit; in pdc_intc_probe()
439 gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; in pdc_intc_probe()
440 gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; in pdc_intc_probe()
441 gc->chip_types[1].chip.irq_set_type = syswake_irq_set_type; in pdc_intc_probe()
442 gc->chip_types[1].chip.irq_set_wake = pdc_irq_set_wake; in pdc_intc_probe()
444 gc->chip_types[1].chip.flags = IRQCHIP_MASK_ON_SUSPEND; in pdc_intc_probe()
449 /* Setup chained handlers for the peripheral IRQs */ in pdc_intc_probe()
450 for (i = 0; i < priv->nr_perips; ++i) { in pdc_intc_probe()
451 irq = priv->perip_irqs[i]; in pdc_intc_probe()
457 irq_set_chained_handler_and_data(priv->syswake_irq, in pdc_intc_probe()
460 dev_info(&pdev->dev, in pdc_intc_probe()
461 "PDC IRQ controller initialised (%u perip IRQs, %u syswake IRQs)\n", in pdc_intc_probe()
462 priv->nr_perips, in pdc_intc_probe()
463 priv->nr_syswakes); in pdc_intc_probe()
467 irq_domain_remove(priv->domain); in pdc_intc_probe()
475 irq_domain_remove(priv->domain); in pdc_intc_remove()
480 { .compatible = "img,pdc-intc" },
486 .name = "pdc-intc",