1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
58 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_get_irqchip_state()
68 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_set_irqchip_state()
76 	int pin_out = d->hwirq;  in pdc_enable_intr()
93 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_disable()
102 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_enable()
111 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_mask()
119 	if (d->hwirq == GPIO_NO_WAKE_IRQ)  in qcom_pdc_gic_unmask()
127  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
149  * qcom_pdc_gic_set_type: Configure PDC for the interrupt
154  * If @type is edge triggered, forward that as Rising edge as PDC
156  * If @type is level, then forward that as level high as PDC
161 	int pin_out = d->hwirq;  in qcom_pdc_gic_set_type()
190 		return -EINVAL;  in qcom_pdc_gic_set_type()
201 	 * When we change types the PDC can give a phantom interrupt.  in qcom_pdc_gic_set_type()
216 	.name			= "PDC",
241 		if (pin >= region->pin_base &&  in get_parent_hwirq()
242 		    pin < region->pin_base + region->cnt)  in get_parent_hwirq()
243 			return (region->parent_base + pin - region->pin_base);  in get_parent_hwirq()
252 	if (is_of_node(fwspec->fwnode)) {  in qcom_pdc_translate()
253 		if (fwspec->param_count != 2)  in qcom_pdc_translate()
254 			return -EINVAL;  in qcom_pdc_translate()
256 		*hwirq = fwspec->param[0];  in qcom_pdc_translate()
257 		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;  in qcom_pdc_translate()
261 	return -EINVAL;  in qcom_pdc_translate()
292 	parent_fwspec.fwnode      = domain->parent->fwnode;  in qcom_pdc_alloc()
339 	parent_fwspec.fwnode      = domain->parent->fwnode;  in qcom_pdc_gpio_alloc()
367 	n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));  in pdc_setup_pin_mapping()
369 		return -EINVAL;  in pdc_setup_pin_mapping()
375 		return -ENOMEM;  in pdc_setup_pin_mapping()
379 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
384 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
389 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
414 		pr_err("%pOF: unable to map PDC registers\n", node);  in qcom_pdc_init()
415 		return -ENXIO;  in qcom_pdc_init()
420 		pr_err("%pOF: unable to find PDC's parent domain\n", node);  in qcom_pdc_init()
421 		ret = -ENXIO;  in qcom_pdc_init()
427 		pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);  in qcom_pdc_init()
436 		ret = -ENOMEM;  in qcom_pdc_init()
446 		pr_err("%pOF: PDC domain add failed for GPIO domain\n", node);  in qcom_pdc_init()
447 		ret = -ENOMEM;  in qcom_pdc_init()
463 IRQCHIP_DECLARE(qcom_pdc, "qcom,pdc", qcom_pdc_init);