Lines Matching +full:mu +full:- +full:side +full:- +full:b
1 // SPDX-License-Identifier: GPL-2.0
19 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
20 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
21 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
25 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
27 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
29 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
31 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
34 /* TX0/RX0/RXDB[0-3] */
94 iowrite32(val, priv->base + offs); in imx_mu_write()
99 return ioread32(priv->base + offs); in imx_mu_read()
107 spin_lock_irqsave(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
108 val = imx_mu_read(priv, priv->dcfg->xCR); in imx_mu_xcr_rmw()
111 imx_mu_write(priv, val, priv->dcfg->xCR); in imx_mu_xcr_rmw()
112 spin_unlock_irqrestore(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
123 switch (cp->type) { in imx_mu_generic_tx()
125 imx_mu_write(priv, *arg, priv->dcfg->xTR[cp->idx]); in imx_mu_generic_tx()
126 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); in imx_mu_generic_tx()
129 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0); in imx_mu_generic_tx()
130 tasklet_schedule(&cp->txdb_tasklet); in imx_mu_generic_tx()
133 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_generic_tx()
134 return -EINVAL; in imx_mu_generic_tx()
145 dat = imx_mu_read(priv, priv->dcfg->xRR[cp->idx]); in imx_mu_generic_rx()
146 mbox_chan_received_data(cp->chan, (void *)&dat); in imx_mu_generic_rx()
160 switch (cp->type) { in imx_mu_scu_tx()
163 * msg->hdr.size specifies the number of u32 words while in imx_mu_scu_tx()
167 if (msg->hdr.size > sizeof(*msg) / 4) { in imx_mu_scu_tx()
172 …dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on TX; got: %i bytes\n", sizeof(*msg… in imx_mu_scu_tx()
173 return -EINVAL; in imx_mu_scu_tx()
176 for (i = 0; i < 4 && i < msg->hdr.size; i++) in imx_mu_scu_tx()
177 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]); in imx_mu_scu_tx()
178 for (; i < msg->hdr.size; i++) { in imx_mu_scu_tx()
179 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, in imx_mu_scu_tx()
184 dev_err(priv->dev, "Send data index: %d timeout\n", i); in imx_mu_scu_tx()
187 imx_mu_write(priv, *arg++, priv->dcfg->xTR[i % 4]); in imx_mu_scu_tx()
190 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); in imx_mu_scu_tx()
193 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_scu_tx()
194 return -EINVAL; in imx_mu_scu_tx()
209 *data++ = imx_mu_read(priv, priv->dcfg->xRR[0]); in imx_mu_scu_rx()
212 …dev_err(priv->dev, "Maximal message size (%zu bytes) exceeded on RX; got: %i bytes\n", sizeof(msg)… in imx_mu_scu_rx()
213 return -EINVAL; in imx_mu_scu_rx()
217 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR, xsr, in imx_mu_scu_rx()
220 dev_err(priv->dev, "timeout read idx %d\n", i); in imx_mu_scu_rx()
223 *data++ = imx_mu_read(priv, priv->dcfg->xRR[i % 4]); in imx_mu_scu_rx()
227 mbox_chan_received_data(cp->chan, (void *)&msg); in imx_mu_scu_rx()
236 mbox_chan_txdone(cp->chan, 0); in imx_mu_txdb_tasklet()
242 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_isr()
243 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_isr()
246 ctrl = imx_mu_read(priv, priv->dcfg->xCR); in imx_mu_isr()
247 val = imx_mu_read(priv, priv->dcfg->xSR); in imx_mu_isr()
249 switch (cp->type) { in imx_mu_isr()
251 val &= IMX_MU_xSR_TEn(cp->idx) & in imx_mu_isr()
252 (ctrl & IMX_MU_xCR_TIEn(cp->idx)); in imx_mu_isr()
255 val &= IMX_MU_xSR_RFn(cp->idx) & in imx_mu_isr()
256 (ctrl & IMX_MU_xCR_RIEn(cp->idx)); in imx_mu_isr()
259 val &= IMX_MU_xSR_GIPn(cp->idx) & in imx_mu_isr()
260 (ctrl & IMX_MU_xCR_GIEn(cp->idx)); in imx_mu_isr()
269 if (val == IMX_MU_xSR_TEn(cp->idx)) { in imx_mu_isr()
270 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); in imx_mu_isr()
272 } else if (val == IMX_MU_xSR_RFn(cp->idx)) { in imx_mu_isr()
273 priv->dcfg->rx(priv, cp); in imx_mu_isr()
274 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { in imx_mu_isr()
275 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), priv->dcfg->xSR); in imx_mu_isr()
278 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); in imx_mu_isr()
282 if (priv->suspend) in imx_mu_isr()
290 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_send_data()
291 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_send_data()
293 return priv->dcfg->tx(priv, cp, data); in imx_mu_send_data()
298 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_startup()
299 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_startup()
303 pm_runtime_get_sync(priv->dev); in imx_mu_startup()
304 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_startup()
306 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet, in imx_mu_startup()
311 /* IPC MU should be with IRQF_NO_SUSPEND set */ in imx_mu_startup()
312 if (!priv->dev->pm_domain) in imx_mu_startup()
315 ret = request_irq(priv->irq, imx_mu_isr, irq_flag, in imx_mu_startup()
316 cp->irq_desc, chan); in imx_mu_startup()
318 dev_err(priv->dev, in imx_mu_startup()
319 "Unable to acquire IRQ %d\n", priv->irq); in imx_mu_startup()
323 switch (cp->type) { in imx_mu_startup()
325 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0); in imx_mu_startup()
328 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0); in imx_mu_startup()
334 priv->suspend = true; in imx_mu_startup()
341 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_shutdown()
342 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_shutdown()
344 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_shutdown()
345 tasklet_kill(&cp->txdb_tasklet); in imx_mu_shutdown()
346 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
350 switch (cp->type) { in imx_mu_shutdown()
352 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); in imx_mu_shutdown()
355 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_RIEn(cp->idx)); in imx_mu_shutdown()
358 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_GIEn(cp->idx)); in imx_mu_shutdown()
364 free_irq(priv->irq, chan); in imx_mu_shutdown()
365 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
379 if (sp->args_count != 2) { in imx_mu_scu_xlate()
380 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_scu_xlate()
381 return ERR_PTR(-EINVAL); in imx_mu_scu_xlate()
384 type = sp->args[0]; /* channel type */ in imx_mu_scu_xlate()
385 idx = sp->args[1]; /* index */ in imx_mu_scu_xlate()
391 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); in imx_mu_scu_xlate()
398 dev_err(mbox->dev, "Invalid chan type: %d\n", type); in imx_mu_scu_xlate()
399 return ERR_PTR(-EINVAL); in imx_mu_scu_xlate()
402 if (chan >= mbox->num_chans) { in imx_mu_scu_xlate()
403 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_scu_xlate()
404 return ERR_PTR(-EINVAL); in imx_mu_scu_xlate()
407 return &mbox->chans[chan]; in imx_mu_scu_xlate()
415 if (sp->args_count != 2) { in imx_mu_xlate()
416 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_xlate()
417 return ERR_PTR(-EINVAL); in imx_mu_xlate()
420 type = sp->args[0]; /* channel type */ in imx_mu_xlate()
421 idx = sp->args[1]; /* index */ in imx_mu_xlate()
424 if (chan >= mbox->num_chans) { in imx_mu_xlate()
425 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_xlate()
426 return ERR_PTR(-EINVAL); in imx_mu_xlate()
429 return &mbox->chans[chan]; in imx_mu_xlate()
437 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_init_generic()
439 cp->idx = i % 4; in imx_mu_init_generic()
440 cp->type = i >> 2; in imx_mu_init_generic()
441 cp->chan = &priv->mbox_chans[i]; in imx_mu_init_generic()
442 priv->mbox_chans[i].con_priv = cp; in imx_mu_init_generic()
443 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_init_generic()
444 "imx_mu_chan[%i-%i]", cp->type, cp->idx); in imx_mu_init_generic()
447 priv->mbox.num_chans = IMX_MU_CHANS; in imx_mu_init_generic()
448 priv->mbox.of_xlate = imx_mu_xlate; in imx_mu_init_generic()
450 if (priv->side_b) in imx_mu_init_generic()
453 /* Set default MU configuration */ in imx_mu_init_generic()
454 imx_mu_write(priv, 0, priv->dcfg->xCR); in imx_mu_init_generic()
462 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_init_scu()
464 cp->idx = i < 2 ? 0 : i - 2; in imx_mu_init_scu()
465 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; in imx_mu_init_scu()
466 cp->chan = &priv->mbox_chans[i]; in imx_mu_init_scu()
467 priv->mbox_chans[i].con_priv = cp; in imx_mu_init_scu()
468 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_init_scu()
469 "imx_mu_chan[%i-%i]", cp->type, cp->idx); in imx_mu_init_scu()
472 priv->mbox.num_chans = IMX_MU_SCU_CHANS; in imx_mu_init_scu()
473 priv->mbox.of_xlate = imx_mu_scu_xlate; in imx_mu_init_scu()
475 /* Set default MU configuration */ in imx_mu_init_scu()
476 imx_mu_write(priv, 0, priv->dcfg->xCR); in imx_mu_init_scu()
481 struct device *dev = &pdev->dev; in imx_mu_probe()
482 struct device_node *np = dev->of_node; in imx_mu_probe()
489 return -ENOMEM; in imx_mu_probe()
491 priv->dev = dev; in imx_mu_probe()
493 priv->base = devm_platform_ioremap_resource(pdev, 0); in imx_mu_probe()
494 if (IS_ERR(priv->base)) in imx_mu_probe()
495 return PTR_ERR(priv->base); in imx_mu_probe()
497 priv->irq = platform_get_irq(pdev, 0); in imx_mu_probe()
498 if (priv->irq < 0) in imx_mu_probe()
499 return priv->irq; in imx_mu_probe()
503 return -EINVAL; in imx_mu_probe()
504 priv->dcfg = dcfg; in imx_mu_probe()
506 priv->clk = devm_clk_get(dev, NULL); in imx_mu_probe()
507 if (IS_ERR(priv->clk)) { in imx_mu_probe()
508 if (PTR_ERR(priv->clk) != -ENOENT) in imx_mu_probe()
509 return PTR_ERR(priv->clk); in imx_mu_probe()
511 priv->clk = NULL; in imx_mu_probe()
514 ret = clk_prepare_enable(priv->clk); in imx_mu_probe()
520 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); in imx_mu_probe()
522 priv->dcfg->init(priv); in imx_mu_probe()
524 spin_lock_init(&priv->xcr_lock); in imx_mu_probe()
526 priv->mbox.dev = dev; in imx_mu_probe()
527 priv->mbox.ops = &imx_mu_ops; in imx_mu_probe()
528 priv->mbox.chans = priv->mbox_chans; in imx_mu_probe()
529 priv->mbox.txdone_irq = true; in imx_mu_probe()
533 ret = devm_mbox_controller_register(dev, &priv->mbox); in imx_mu_probe()
535 clk_disable_unprepare(priv->clk); in imx_mu_probe()
551 clk_disable_unprepare(priv->clk); in imx_mu_probe()
553 priv->suspend = false; in imx_mu_probe()
559 clk_disable_unprepare(priv->clk); in imx_mu_probe()
567 pm_runtime_disable(priv->dev); in imx_mu_remove()
603 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
604 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
605 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
614 if (!priv->clk) in imx_mu_suspend_noirq()
615 priv->xcr = imx_mu_read(priv, priv->dcfg->xCR); in imx_mu_suspend_noirq()
625 * ONLY restore MU when context lost, the TIE could in imx_mu_resume_noirq()
626 * be set during noirq resume as there is MU data in imx_mu_resume_noirq()
628 * value will overwrite the TIE and cause MU data in imx_mu_resume_noirq()
632 if (!imx_mu_read(priv, priv->dcfg->xCR) && !priv->clk) in imx_mu_resume_noirq()
633 imx_mu_write(priv, priv->xcr, priv->dcfg->xCR); in imx_mu_resume_noirq()
642 clk_disable_unprepare(priv->clk); in imx_mu_runtime_suspend()
652 ret = clk_prepare_enable(priv->clk); in imx_mu_runtime_resume()