Lines Matching full:slv
376 /* Set SLV-T Bank : 0xAE */ in cxd2841er_dvbs2_set_symbol_rate()
408 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_s_to_active_s()
413 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_s_to_active_s()
417 /* Set SLV-T Bank : 0xAE */ in cxd2841er_sleep_s_to_active_s()
421 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_s_to_active_s()
431 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_s_to_active_s()
435 /* Set SLV-T Bank : 0xA3 */ in cxd2841er_sleep_s_to_active_s()
442 /* Set SLV-T Bank : 0xAB */ in cxd2841er_sleep_s_to_active_s()
457 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_s_to_active_s()
497 /* Set SLV-T Bank : 0x00 */ in cxd2841er_retune_active()
536 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_s_to_sleep_s()
544 /* Set SLV-X Bank : 0x00 */ in cxd2841er_active_s_to_sleep_s()
548 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_s_to_sleep_s()
560 /* Set SLV-T Bank : 0xAE */ in cxd2841er_active_s_to_sleep_s()
564 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_s_to_sleep_s()
580 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_s_to_shutdown()
586 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_s_to_shutdown()
604 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_tc_to_shutdown()
622 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_t_to_sleep_tc()
630 /* Set SLV-X Bank : 0x00 */ in cxd2841er_active_t_to_sleep_tc()
634 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_t_to_sleep_tc()
658 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_t2_to_sleep_tc()
676 /* Set SLV-X Bank : 0x00 */ in cxd2841er_active_t2_to_sleep_tc()
680 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_t2_to_sleep_tc()
704 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_c_to_sleep_tc()
715 /* Set SLV-X Bank : 0x00 */ in cxd2841er_active_c_to_sleep_tc()
719 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_c_to_sleep_tc()
743 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_i_to_sleep_tc()
754 /* Set SLV-X Bank : 0x00 */ in cxd2841er_active_i_to_sleep_tc()
758 /* Set SLV-T Bank : 0x00 */ in cxd2841er_active_i_to_sleep_tc()
782 /* Set SLV-X Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_s()
787 /* Set SLV-X Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_s()
815 /* Set SLV-T Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_s()
842 /* Set SLV-X Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_tc()
847 /* Set SLV-X Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_tc()
872 /* Set SLV-T Bank : 0x00 */ in cxd2841er_shutdown_to_sleep_tc()
888 /* Set SLV-T Bank : 0x00 */ in cxd2841er_tune_done()
904 /* Set SLV-T Bank : 0x00 */ in cxd2841er_set_ts_clock_mode()
914 * <SLV-T> 00h C4h [1:0] 2'b?? OSERCKMODE in cxd2841er_set_ts_clock_mode()
920 * <SLV-T> 00h D1h [1:0] 2'b?? OSERDUTYMODE in cxd2841er_set_ts_clock_mode()
926 * <SLV-T> 00h D9h [7:0] 8'h08 OTSCKPERIOD in cxd2841er_set_ts_clock_mode()
932 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN in cxd2841er_set_ts_clock_mode()
937 * <SLV-T> 00h 33h [1:0] 2'b01 OREG_CKSEL_TSIF in cxd2841er_set_ts_clock_mode()
944 * <SLV-T> 00h 32h [0] 1'b1 OREG_CK_TSIF_EN in cxd2841er_set_ts_clock_mode()
985 /* Set SLV-T Bank : 0xA0 */ in cxd2841er_read_status_s()
989 * <SLV-T> A0h 11h [2] ITSLOCK in cxd2841er_read_status_s()
1012 /* Set SLV-T Bank : 0x10 */ in cxd2841er_read_status_t_t2()
1015 /* Set SLV-T Bank : 0x20 */ in cxd2841er_read_status_t_t2()
1059 /* Set SLV-T Bank : 0x60 */ in cxd2841er_read_status_i()
1142 * <SLV-T> A0h 10h [0] ITRL_LOCK in cxd2841er_get_carrier_offset_s_s2()
1149 * <SLV-T> A0h 50h [4] IHSMODE in cxd2841er_get_carrier_offset_s_s2()
1161 * <SLV-T> A0h 45h [4:0] ICFRL_CTRLVAL[20:16] in cxd2841er_get_carrier_offset_s_s2()
1162 * <SLV-T> A0h 46h [7:0] ICFRL_CTRLVAL[15:8] in cxd2841er_get_carrier_offset_s_s2()
1163 * <SLV-T> A0h 47h [7:0] ICFRL_CTRLVAL[7:0] in cxd2841er_get_carrier_offset_s_s2()
1486 /* Set SLV-T Bank : 0xA0 */ in cxd2841er_mon_read_ber_s()
1490 * <SLV-T> A0h 35h [0] IFVBER_VALID in cxd2841er_mon_read_ber_s()
1491 * <SLV-T> A0h 36h [5:0] IFVBER_BITERR[21:16] in cxd2841er_mon_read_ber_s()
1492 * <SLV-T> A0h 37h [7:0] IFVBER_BITERR[15:8] in cxd2841er_mon_read_ber_s()
1493 * <SLV-T> A0h 38h [7:0] IFVBER_BITERR[7:0] in cxd2841er_mon_read_ber_s()
1494 * <SLV-T> A0h 3Dh [5:0] IFVBER_BITNUM[21:16] in cxd2841er_mon_read_ber_s()
1495 * <SLV-T> A0h 3Eh [7:0] IFVBER_BITNUM[15:8] in cxd2841er_mon_read_ber_s()
1496 * <SLV-T> A0h 3Fh [7:0] IFVBER_BITNUM[7:0] in cxd2841er_mon_read_ber_s()
1525 /* Set SLV-T Bank : 0xB2 */ in cxd2841er_mon_read_ber_s2()
1529 * <SLV-T> B2h 30h [0] IFLBER_VALID in cxd2841er_mon_read_ber_s2()
1530 * <SLV-T> B2h 31h [3:0] IFLBER_BITERR[27:24] in cxd2841er_mon_read_ber_s2()
1531 * <SLV-T> B2h 32h [7:0] IFLBER_BITERR[23:16] in cxd2841er_mon_read_ber_s2()
1532 * <SLV-T> B2h 33h [7:0] IFLBER_BITERR[15:8] in cxd2841er_mon_read_ber_s2()
1533 * <SLV-T> B2h 34h [7:0] IFLBER_BITERR[7:0] in cxd2841er_mon_read_ber_s2()
1543 /* Set SLV-T Bank : 0xA0 */ in cxd2841er_mon_read_ber_s2()
1678 /* Set SLV-T Bank : 0xA1 */ in cxd2841er_dvbs_read_snr()
1682 * <SLV-T> A1h 10h [0] ICPM_QUICKRDY in cxd2841er_dvbs_read_snr()
1683 * <SLV-T> A1h 11h [4:0] ICPM_QUICKCNDT[12:8] in cxd2841er_dvbs_read_snr()
1684 * <SLV-T> A1h 12h [7:0] ICPM_QUICKCNDT[7:0] in cxd2841er_dvbs_read_snr()
1928 /* Set SLV-T Bank : 0xA0 */ in cxd2841er_read_agc_gain_s()
1932 * <SLV-T> A0h 1Fh [4:0] IRFAGC_GAIN[12:8] in cxd2841er_read_agc_gain_s()
1933 * <SLV-T> A0h 20h [7:0] IRFAGC_GAIN[7:0] in cxd2841er_read_agc_gain_s()
2137 /* Set SLV-T Bank : 0x2E */ in cxd2841er_dvbt2_set_profile()
2141 /* Set SLV-T Bank : 0x2B */ in cxd2841er_dvbt2_set_profile()
2159 /* Set SLV-T Bank : 0x23 */ in cxd2841er_dvbt2_set_plp_config()
2256 /* Set SLV-T Bank : 0x20 */ in cxd2841er_sleep_tc_to_active_t2_band()
2265 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2_band()
2270 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2_band()
2295 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2_band()
2300 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2_band()
2325 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2_band()
2330 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2_band()
2355 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2_band()
2360 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2_band()
2385 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2_band()
2390 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2_band()
2479 /* Set SLV-T Bank : 0x13 */ in cxd2841er_sleep_tc_to_active_t_band()
2486 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t_band()
2692 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_i_band()
2862 /* Set SLV-T Bank : 0x11 */ in cxd2841er_sleep_tc_to_active_c_band()
2875 /* Set SLV-T Bank : 0x40 */ in cxd2841er_sleep_tc_to_active_c_band()
2905 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t()
2909 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t()
2927 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t()
2931 /* Set SLV-T Bank : 0x11 */ in cxd2841er_sleep_tc_to_active_t()
2935 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t()
2940 /* Set SLV-T Bank : 0x18 */ in cxd2841er_sleep_tc_to_active_t()
2947 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t()
2954 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t()
2962 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t()
2979 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t2()
2983 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t2()
3006 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2()
3010 /* Set SLV-T Bank : 0x11 */ in cxd2841er_sleep_tc_to_active_t2()
3014 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_t2()
3019 /* Set SLV-T Bank : 0x20 */ in cxd2841er_sleep_tc_to_active_t2()
3023 /* Set SLV-T Bank : 0x2b */ in cxd2841er_sleep_tc_to_active_t2()
3026 /* Set SLV-T Bank : 0x23 */ in cxd2841er_sleep_tc_to_active_t2()
3030 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t2()
3041 /* Set SLV-T Bank : 0x2a */ in cxd2841er_sleep_tc_to_active_t2()
3044 /* Set SLV-T Bank : 0x2b */ in cxd2841er_sleep_tc_to_active_t2()
3050 /* Set SLV-T Bank : 0x11 */ in cxd2841er_sleep_tc_to_active_t2()
3057 /* Set SLV-T Bank : 0x20 */ in cxd2841er_sleep_tc_to_active_t2()
3070 /* Set SLV-T Bank : 0x24 */ in cxd2841er_sleep_tc_to_active_t2()
3088 /* Set SLV-T Bank : 0x25 */ in cxd2841er_sleep_tc_to_active_t2()
3092 /* Set SLV-T Bank : 0x27 */ in cxd2841er_sleep_tc_to_active_t2()
3096 /* Set SLV-T Bank : 0x2B */ in cxd2841er_sleep_tc_to_active_t2()
3101 /* Set SLV-T Bank : 0x2D */ in cxd2841er_sleep_tc_to_active_t2()
3107 /* Set SLV-T Bank : 0x5E */ in cxd2841er_sleep_tc_to_active_t2()
3116 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_t2()
3136 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_i()
3140 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_i()
3162 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_i()
3166 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_i()
3176 /* Set SLV-T Bank : 0x15 */ in cxd2841er_sleep_tc_to_active_i()
3179 /* Set SLV-T Bank : 0x1E */ in cxd2841er_sleep_tc_to_active_i()
3182 /* Set SLV-T Bank : 0x63 */ in cxd2841er_sleep_tc_to_active_i()
3187 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_i()
3190 /* Set SLV-T Bank : 0x60 */ in cxd2841er_sleep_tc_to_active_i()
3195 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_i()
3212 /* Set SLV-X Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_c()
3216 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_c()
3231 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_c()
3235 /* Set SLV-T Bank : 0x11 */ in cxd2841er_sleep_tc_to_active_c()
3239 /* Set SLV-T Bank : 0x10 */ in cxd2841er_sleep_tc_to_active_c()
3244 /* Set SLV-T Bank : 0x40 */ in cxd2841er_sleep_tc_to_active_c()
3248 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_c()
3255 /* Set SLV-T Bank : 0x00 */ in cxd2841er_sleep_tc_to_active_c()