78 			    const struct smiapp_pll_limits *limits,  in check_all_bounds()  argument
86 			    limits->min_pll_ip_freq_hz,  in check_all_bounds()
87 			    limits->max_pll_ip_freq_hz,  in check_all_bounds()
92 			limits->min_pll_multiplier, limits->max_pll_multiplier,  in check_all_bounds()
97 			limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz,  in check_all_bounds()
127 			limits->vt.min_sys_clk_freq_hz,  in check_all_bounds()
128 			limits->vt.max_sys_clk_freq_hz,  in check_all_bounds()
133 			limits->vt.min_pix_clk_freq_hz,  in check_all_bounds()
134 			limits->vt.max_pix_clk_freq_hz,  in check_all_bounds()
152 	struct device *dev, const struct smiapp_pll_limits *limits,  in __smiapp_pll_calculate()  argument
163 	 * There are limits for all values in the clock tree. These  in __smiapp_pll_calculate()
179 	more_mul_max = limits->max_pll_multiplier / mul;  in __smiapp_pll_calculate()
186 		      limits->max_pll_op_freq_hz  in __smiapp_pll_calculate()
198 			   DIV_ROUND_UP(limits->max_pll_multiplier, mul));  in __smiapp_pll_calculate()
203 	more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz,  in __smiapp_pll_calculate()
210 			   DIV_ROUND_UP(limits->min_pll_multiplier, mul));  in __smiapp_pll_calculate()
267 	if (limits->min_line_length_pck_bin > limits->min_line_length_pck  in __smiapp_pll_calculate()
283 	 * Find absolute limits for the factor of vt divider.  in __smiapp_pll_calculate()
295 				      limits->vt.max_pix_clk_freq_hz));  in __smiapp_pll_calculate()
299 			   limits->vt.min_pix_clk_div  in __smiapp_pll_calculate()
300 			   * limits->vt.min_sys_clk_div);  in __smiapp_pll_calculate()
303 	max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div;  in __smiapp_pll_calculate()
307 				      limits->vt.min_pix_clk_freq_hz));  in __smiapp_pll_calculate()
315 	min_sys_div = limits->vt.min_sys_clk_div;  in __smiapp_pll_calculate()
319 				       limits->vt.max_pix_clk_div));  in __smiapp_pll_calculate()
323 			  / limits->vt.max_sys_clk_freq_hz);  in __smiapp_pll_calculate()
328 	max_sys_div = limits->vt.max_sys_clk_div;  in __smiapp_pll_calculate()
332 				       limits->vt.min_pix_clk_div));  in __smiapp_pll_calculate()
336 				       limits->vt.min_pix_clk_freq_hz));  in __smiapp_pll_calculate()
351 			if (pix_div < limits->vt.min_pix_clk_div  in __smiapp_pll_calculate()
352 			    || pix_div > limits->vt.max_pix_clk_div) {  in __smiapp_pll_calculate()
356 					limits->vt.min_pix_clk_div,  in __smiapp_pll_calculate()
357 					limits->vt.max_pix_clk_div);  in __smiapp_pll_calculate()
383 	return check_all_bounds(dev, limits, op_limits, pll, op_pll);  in __smiapp_pll_calculate()
387 			 const struct smiapp_pll_limits *limits,  in smiapp_pll_calculate()  argument
390 	const struct smiapp_pll_branch_limits *op_limits = &limits->op;  in smiapp_pll_calculate()
405 		op_limits = &limits->vt;  in smiapp_pll_calculate()
433 	/* Figure out limits for pre-pll divider based on extclk */  in smiapp_pll_calculate()
435 		limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);  in smiapp_pll_calculate()
437 		min_t(uint16_t, limits->max_pre_pll_clk_div,  in smiapp_pll_calculate()
439 				   limits->min_pll_ip_freq_hz));  in smiapp_pll_calculate()
441 		max_t(uint16_t, limits->min_pre_pll_clk_div,  in smiapp_pll_calculate()
444 					   limits->max_pll_ip_freq_hz)));  in smiapp_pll_calculate()
457 					   limits->max_pll_op_freq_hz)));  in smiapp_pll_calculate()
464 		rval = __smiapp_pll_calculate(dev, limits, op_limits, pll,  in smiapp_pll_calculate()