Lines Matching +full:gemini +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0-only
3 * lpc_ich.c - LPC interface for Intel ICH
7 * Power Management, System Management, GPIO, RTC, and LPC
13 * Author: Aaron Sierra <asierra@xes-inc.com>
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 322896-001, 322897-001: NM10
30 * document number 313056-003, 313057-017: 82801H (ICH8)
31 * document number 316972-004, 316973-012: 82801I (ICH9)
32 * document number 319973-002, 319974-002: 82801J (ICH10)
33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
34 * document number 320066-003, 320257-008: EP80597 (IICH)
35 * document number 324645-001, 324646-001: Cougar Point (CPT)
101 /* ACPI - TCO */
105 /* ACPI - SMI */
120 /* ACPI - GPE0 */
148 .name = "intel-spi",
159 LPC_ICH2M, /* ICH2-M */
160 LPC_ICH3, /* ICH3-S */
161 LPC_ICH3M, /* ICH3-M */
163 LPC_ICH4M, /* ICH4-M */
164 LPC_CICH, /* C-ICH */
168 LPC_ICH6M, /* ICH6-M */
173 LPC_ICH7M, /* ICH7-M & ICH7-U */
174 LPC_ICH7MDH, /* ICH7-M DH */
180 LPC_ICH8ME, /* ICH8M-E */
186 LPC_ICH9ME, /* ICH9M-E */
214 LPC_LPT_LP, /* Lynx Point-LP */
219 LPC_WPT_LP, /* Wildcat Point-LP */
224 LPC_GLK, /* Gemini Lake SoC */
242 .name = "ICH2-M",
246 .name = "ICH3-S",
250 .name = "ICH3-M",
258 .name = "ICH4-M",
262 .name = "C-ICH",
279 .name = "ICH6-M",
304 .name = "ICH7-M or ICH7-U",
309 .name = "ICH7-M DH",
339 .name = "ICH8M-E",
369 .name = "ICH9M-E",
555 .name = "Gemini Lake SoC",
814 if (priv->abase_save >= 0) { in lpc_ich_restore_config_space()
815 pci_write_config_byte(dev, priv->abase, priv->abase_save); in lpc_ich_restore_config_space()
816 priv->abase_save = -1; in lpc_ich_restore_config_space()
819 if (priv->actrl_pbase_save >= 0) { in lpc_ich_restore_config_space()
820 pci_write_config_byte(dev, priv->actrl_pbase, in lpc_ich_restore_config_space()
821 priv->actrl_pbase_save); in lpc_ich_restore_config_space()
822 priv->actrl_pbase_save = -1; in lpc_ich_restore_config_space()
825 if (priv->gctrl_save >= 0) { in lpc_ich_restore_config_space()
826 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); in lpc_ich_restore_config_space()
827 priv->gctrl_save = -1; in lpc_ich_restore_config_space()
836 switch (lpc_chipset_info[priv->chipset].iTCO_version) { in lpc_ich_enable_acpi_space()
842 pci_read_config_byte(dev, priv->abase, ®_save); in lpc_ich_enable_acpi_space()
843 pci_write_config_byte(dev, priv->abase, reg_save | 0x2); in lpc_ich_enable_acpi_space()
844 priv->abase_save = reg_save; in lpc_ich_enable_acpi_space()
851 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); in lpc_ich_enable_acpi_space()
852 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); in lpc_ich_enable_acpi_space()
853 priv->actrl_pbase_save = reg_save; in lpc_ich_enable_acpi_space()
863 pci_read_config_byte(dev, priv->gctrl, ®_save); in lpc_ich_enable_gpio_space()
864 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); in lpc_ich_enable_gpio_space()
865 priv->gctrl_save = reg_save; in lpc_ich_enable_gpio_space()
873 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); in lpc_ich_enable_pmc_space()
874 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); in lpc_ich_enable_pmc_space()
876 priv->actrl_pbase_save = reg_save; in lpc_ich_enable_pmc_space()
886 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); in lpc_ich_finalize_wdt_cell()
888 return -ENOMEM; in lpc_ich_finalize_wdt_cell()
890 info = &lpc_chipset_info[priv->chipset]; in lpc_ich_finalize_wdt_cell()
892 pdata->version = info->iTCO_version; in lpc_ich_finalize_wdt_cell()
893 strlcpy(pdata->name, info->name, sizeof(pdata->name)); in lpc_ich_finalize_wdt_cell()
895 cell->platform_data = pdata; in lpc_ich_finalize_wdt_cell()
896 cell->pdata_size = sizeof(*pdata); in lpc_ich_finalize_wdt_cell()
905 cell->platform_data = &lpc_chipset_info[priv->chipset]; in lpc_ich_finalize_gpio_cell()
906 cell->pdata_size = sizeof(struct lpc_ich_info); in lpc_ich_finalize_gpio_cell()
920 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) in lpc_ich_check_conflict_gpio()
923 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) in lpc_ich_check_conflict_gpio()
926 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); in lpc_ich_check_conflict_gpio()
943 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); in lpc_ich_init_gpio()
946 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); in lpc_ich_init_gpio()
947 lpc_ich_gpio_cell.num_resources--; in lpc_ich_init_gpio()
952 res->start = base_addr + ACPIBASE_GPE_OFF; in lpc_ich_init_gpio()
953 res->end = base_addr + ACPIBASE_GPE_END; in lpc_ich_init_gpio()
961 lpc_ich_gpio_cell.num_resources--; in lpc_ich_init_gpio()
969 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); in lpc_ich_init_gpio()
972 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); in lpc_ich_init_gpio()
973 ret = -ENODEV; in lpc_ich_init_gpio()
979 res->start = base_addr; in lpc_ich_init_gpio()
980 switch (lpc_chipset_info[priv->chipset].gpio_version) { in lpc_ich_init_gpio()
983 res->end = res->start + 128 - 1; in lpc_ich_init_gpio()
986 res->end = res->start + 64 - 1; in lpc_ich_init_gpio()
996 lpc_chipset_info[priv->chipset].use_gpio = ret; in lpc_ich_init_gpio()
1000 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, in lpc_ich_init_gpio()
1020 return -ENODEV; in lpc_ich_init_wdt()
1023 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); in lpc_ich_init_wdt()
1026 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); in lpc_ich_init_wdt()
1027 ret = -ENODEV; in lpc_ich_init_wdt()
1032 res->start = base_addr + ACPIBASE_TCO_OFF; in lpc_ich_init_wdt()
1033 res->end = base_addr + ACPIBASE_TCO_END; in lpc_ich_init_wdt()
1036 res->start = base_addr + ACPIBASE_SMI_OFF; in lpc_ich_init_wdt()
1037 res->end = base_addr + ACPIBASE_SMI_END; in lpc_ich_init_wdt()
1043 * Get the Memory-Mapped GCS register. To get access to it in lpc_ich_init_wdt()
1052 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { in lpc_ich_init_wdt()
1054 lpc_ich_wdt_cell.num_resources--; in lpc_ich_init_wdt()
1055 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { in lpc_ich_init_wdt()
1059 dev_notice(&dev->dev, "RCBA is disabled by " in lpc_ich_init_wdt()
1061 ret = -ENODEV; in lpc_ich_init_wdt()
1065 res->start = base_addr + ACPIBASE_GCS_OFF; in lpc_ich_init_wdt()
1066 res->end = base_addr + ACPIBASE_GCS_END; in lpc_ich_init_wdt()
1067 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { in lpc_ich_init_wdt()
1073 res->start = base_addr + ACPIBASE_PMC_OFF; in lpc_ich_init_wdt()
1074 res->end = base_addr + ACPIBASE_PMC_END; in lpc_ich_init_wdt()
1081 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, in lpc_ich_init_wdt()
1140 info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); in lpc_ich_init_spi()
1142 return -ENOMEM; in lpc_ich_init_spi()
1144 info->type = lpc_chipset_info[priv->chipset].spi_type; in lpc_ich_init_spi()
1146 switch (info->type) { in lpc_ich_init_spi()
1150 res->start = spi_base & ~(SPIBASE_BYT_SZ - 1); in lpc_ich_init_spi()
1151 res->end = res->start + SPIBASE_BYT_SZ - 1; in lpc_ich_init_spi()
1153 info->set_writeable = lpc_ich_byt_set_writeable; in lpc_ich_init_spi()
1161 res->start = spi_base + SPIBASE_LPT; in lpc_ich_init_spi()
1162 res->end = res->start + SPIBASE_LPT_SZ - 1; in lpc_ich_init_spi()
1164 info->set_writeable = lpc_ich_lpt_set_writeable; in lpc_ich_init_spi()
1165 info->data = dev; in lpc_ich_init_spi()
1172 struct pci_bus *bus = dev->bus; in lpc_ich_init_spi()
1183 res->start = spi_base & 0xfffffff0; in lpc_ich_init_spi()
1184 res->end = res->start + SPIBASE_APL_SZ - 1; in lpc_ich_init_spi()
1186 info->set_writeable = lpc_ich_bxt_set_writeable; in lpc_ich_init_spi()
1187 info->data = bus; in lpc_ich_init_spi()
1195 return -EINVAL; in lpc_ich_init_spi()
1198 if (!res->start) in lpc_ich_init_spi()
1199 return -ENODEV; in lpc_ich_init_spi()
1204 return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE, in lpc_ich_init_spi()
1215 priv = devm_kzalloc(&dev->dev, in lpc_ich_probe()
1218 return -ENOMEM; in lpc_ich_probe()
1220 priv->chipset = id->driver_data; in lpc_ich_probe()
1222 priv->actrl_pbase_save = -1; in lpc_ich_probe()
1223 priv->abase_save = -1; in lpc_ich_probe()
1225 priv->abase = ACPIBASE; in lpc_ich_probe()
1226 priv->actrl_pbase = ACPICTRL_PMCBASE; in lpc_ich_probe()
1228 priv->gctrl_save = -1; in lpc_ich_probe()
1229 if (priv->chipset <= LPC_ICH5) { in lpc_ich_probe()
1230 priv->gbase = GPIOBASE_ICH0; in lpc_ich_probe()
1231 priv->gctrl = GPIOCTRL_ICH0; in lpc_ich_probe()
1233 priv->gbase = GPIOBASE_ICH6; in lpc_ich_probe()
1234 priv->gctrl = GPIOCTRL_ICH6; in lpc_ich_probe()
1239 if (lpc_chipset_info[priv->chipset].iTCO_version) { in lpc_ich_probe()
1245 if (lpc_chipset_info[priv->chipset].gpio_version) { in lpc_ich_probe()
1251 if (lpc_chipset_info[priv->chipset].spi_type) { in lpc_ich_probe()
1262 dev_warn(&dev->dev, "No MFD cells added\n"); in lpc_ich_probe()
1264 return -ENODEV; in lpc_ich_probe()
1272 mfd_remove_devices(&dev->dev); in lpc_ich_remove()
1285 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");