Lines Matching +full:ddr +full:- +full:sel +full:- +full:low
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 MediaTek Inc.
10 #include <linux/dma-mapping.h>
34 #include <linux/mmc/slot-gpio.h>
40 /*--------------------------------------------------------------------------*/
42 /*--------------------------------------------------------------------------*/
49 /*--------------------------------------------------------------------------*/
51 /*--------------------------------------------------------------------------*/
85 /*--------------------------------------------------------------------------*/
87 /*--------------------------------------------------------------------------*/
92 /*--------------------------------------------------------------------------*/
94 /*--------------------------------------------------------------------------*/
308 /*--------------------------------------------------------------------------*/
310 /*--------------------------------------------------------------------------*/
440 bool internal_cd; /* Use internal card-detect logic */
564 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
565 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
566 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
567 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
568 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
569 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
570 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
571 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
572 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
598 tv |= ((val) << (ffs((unsigned int)field) - 1)); in sdr_set_field()
606 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); in sdr_get_field()
613 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
614 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) in msdc_reset_hw()
617 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); in msdc_reset_hw()
618 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) in msdc_reset_hw()
621 val = readl(host->base + MSDC_INT); in msdc_reset_hw()
622 writel(val, host->base + MSDC_INT); in msdc_reset_hw()
642 return 0xff - (u8) sum; in msdc_dma_calcs()
655 sg = data->sg; in msdc_dma_setup()
657 gpd = dma->gpd; in msdc_dma_setup()
658 bd = dma->bd; in msdc_dma_setup()
661 gpd->gpd_info |= GPDMA_DESC_HWO; in msdc_dma_setup()
662 gpd->gpd_info |= GPDMA_DESC_BDP; in msdc_dma_setup()
664 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; in msdc_dma_setup()
665 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; in msdc_dma_setup()
668 for_each_sg(data->sg, sg, data->sg_count, j) { in msdc_dma_setup()
676 if (host->dev_comp->support_64g) { in msdc_dma_setup()
682 if (host->dev_comp->support_64g) { in msdc_dma_setup()
690 if (j == data->sg_count - 1) /* the last bd */ in msdc_dma_setup()
700 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); in msdc_dma_setup()
701 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
704 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
705 if (host->dev_comp->support_64g) in msdc_dma_setup()
706 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, in msdc_dma_setup()
707 upper_32_bits(dma->gpd_addr) & 0xf); in msdc_dma_setup()
708 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); in msdc_dma_setup()
713 struct mmc_data *data = mrq->data; in msdc_prepare_data()
715 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { in msdc_prepare_data()
716 data->host_cookie |= MSDC_PREPARE_FLAG; in msdc_prepare_data()
717 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, in msdc_prepare_data()
724 struct mmc_data *data = mrq->data; in msdc_unprepare_data()
726 if (data->host_cookie & MSDC_ASYNC_FLAG) in msdc_unprepare_data()
729 if (data->host_cookie & MSDC_PREPARE_FLAG) { in msdc_unprepare_data()
730 dma_unmap_sg(host->dev, data->sg, data->sg_len, in msdc_unprepare_data()
732 data->host_cookie &= ~MSDC_PREPARE_FLAG; in msdc_unprepare_data()
742 if (mmc->actual_clock == 0) { in msdc_timeout_cal()
746 do_div(clk_ns, mmc->actual_clock); in msdc_timeout_cal()
747 timeout = ns + clk_ns - 1; in msdc_timeout_cal()
752 if (host->dev_comp->clk_div_bits == 8) in msdc_timeout_cal()
753 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
756 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
758 /*DDR mode will double the clk cycles for data timeout */ in msdc_timeout_cal()
760 timeout = timeout > 1 ? timeout - 1 : 0; in msdc_timeout_cal()
770 host->timeout_ns = ns; in msdc_set_timeout()
771 host->timeout_clks = clks; in msdc_set_timeout()
774 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, in msdc_set_timeout()
783 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, in msdc_set_busy_timeout()
789 clk_disable_unprepare(host->src_clk_cg); in msdc_gate_clock()
790 clk_disable_unprepare(host->src_clk); in msdc_gate_clock()
791 clk_disable_unprepare(host->bus_clk); in msdc_gate_clock()
792 clk_disable_unprepare(host->h_clk); in msdc_gate_clock()
797 clk_prepare_enable(host->h_clk); in msdc_ungate_clock()
798 clk_prepare_enable(host->bus_clk); in msdc_ungate_clock()
799 clk_prepare_enable(host->src_clk); in msdc_ungate_clock()
800 clk_prepare_enable(host->src_clk_cg); in msdc_ungate_clock()
801 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) in msdc_ungate_clock()
812 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_mclk()
815 dev_dbg(host->dev, "set mclk to 0\n"); in msdc_set_mclk()
816 host->mclk = 0; in msdc_set_mclk()
817 mmc->actual_clock = 0; in msdc_set_mclk()
818 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
822 flags = readl(host->base + MSDC_INTEN); in msdc_set_mclk()
823 sdr_clr_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
824 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
825 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
827 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
835 mode = 0x2; /* ddr mode and use divisor */ in msdc_set_mclk()
837 if (hz >= (host->src_clk_freq >> 2)) { in msdc_set_mclk()
839 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
841 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
842 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
847 hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
848 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
849 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
852 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
854 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
857 } else if (hz >= host->src_clk_freq) { in msdc_set_mclk()
860 sclk = host->src_clk_freq; in msdc_set_mclk()
863 if (hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
865 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
867 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
868 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
871 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
876 if (host->src_clk_cg) in msdc_set_mclk()
877 clk_disable_unprepare(host->src_clk_cg); in msdc_set_mclk()
879 clk_disable_unprepare(clk_get_parent(host->src_clk)); in msdc_set_mclk()
880 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
881 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
885 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
888 if (host->src_clk_cg) in msdc_set_mclk()
889 clk_prepare_enable(host->src_clk_cg); in msdc_set_mclk()
891 clk_prepare_enable(clk_get_parent(host->src_clk)); in msdc_set_mclk()
893 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) in msdc_set_mclk()
895 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
896 mmc->actual_clock = sclk; in msdc_set_mclk()
897 host->mclk = hz; in msdc_set_mclk()
898 host->timing = timing; in msdc_set_mclk()
900 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); in msdc_set_mclk()
901 sdr_set_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
907 if (mmc->actual_clock <= 52000000) { in msdc_set_mclk()
908 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
909 if (host->top_base) { in msdc_set_mclk()
910 writel(host->def_tune_para.emmc_top_control, in msdc_set_mclk()
911 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
912 writel(host->def_tune_para.emmc_top_cmd, in msdc_set_mclk()
913 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
915 writel(host->def_tune_para.pad_tune, in msdc_set_mclk()
916 host->base + tune_reg); in msdc_set_mclk()
919 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
920 writel(host->saved_tune_para.pad_cmd_tune, in msdc_set_mclk()
921 host->base + PAD_CMD_TUNE); in msdc_set_mclk()
922 if (host->top_base) { in msdc_set_mclk()
923 writel(host->saved_tune_para.emmc_top_control, in msdc_set_mclk()
924 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
925 writel(host->saved_tune_para.emmc_top_cmd, in msdc_set_mclk()
926 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
928 writel(host->saved_tune_para.pad_tune, in msdc_set_mclk()
929 host->base + tune_reg); in msdc_set_mclk()
934 host->dev_comp->hs400_tune) in msdc_set_mclk()
935 sdr_set_field(host->base + tune_reg, in msdc_set_mclk()
937 host->hs400_cmd_int_delay); in msdc_set_mclk()
938 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, in msdc_set_mclk()
978 u32 opcode = cmd->opcode; in msdc_cmd_prepare_raw_cmd()
982 host->cmd_rsp = resp; in msdc_cmd_prepare_raw_cmd()
984 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || in msdc_cmd_prepare_raw_cmd()
996 if (cmd->data) { in msdc_cmd_prepare_raw_cmd()
997 struct mmc_data *data = cmd->data; in msdc_cmd_prepare_raw_cmd()
1000 if (mmc_card_mmc(mmc->card) && mrq->sbc && in msdc_cmd_prepare_raw_cmd()
1001 !(mrq->sbc->arg & 0xFFFF0000)) in msdc_cmd_prepare_raw_cmd()
1005 rawcmd |= ((data->blksz & 0xFFF) << 16); in msdc_cmd_prepare_raw_cmd()
1006 if (data->flags & MMC_DATA_WRITE) in msdc_cmd_prepare_raw_cmd()
1008 if (data->blocks > 1) in msdc_cmd_prepare_raw_cmd()
1013 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1015 if (host->timeout_ns != data->timeout_ns || in msdc_cmd_prepare_raw_cmd()
1016 host->timeout_clks != data->timeout_clks) in msdc_cmd_prepare_raw_cmd()
1017 msdc_set_timeout(host, data->timeout_ns, in msdc_cmd_prepare_raw_cmd()
1018 data->timeout_clks); in msdc_cmd_prepare_raw_cmd()
1020 writel(data->blocks, host->base + SDC_BLK_NUM); in msdc_cmd_prepare_raw_cmd()
1030 WARN_ON(host->data); in msdc_start_data()
1031 host->data = data; in msdc_start_data()
1032 read = data->flags & MMC_DATA_READ; in msdc_start_data()
1034 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_data()
1035 msdc_dma_setup(host, &host->dma, data); in msdc_start_data()
1036 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_start_data()
1037 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); in msdc_start_data()
1038 dev_dbg(host->dev, "DMA start\n"); in msdc_start_data()
1039 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", in msdc_start_data()
1040 __func__, cmd->opcode, data->blocks, read); in msdc_start_data()
1046 u32 *rsp = cmd->resp; in msdc_auto_cmd_done()
1048 rsp[0] = readl(host->base + SDC_ACMD_RESP); in msdc_auto_cmd_done()
1051 cmd->error = 0; in msdc_auto_cmd_done()
1055 cmd->error = -EILSEQ; in msdc_auto_cmd_done()
1056 host->error |= REQ_STOP_EIO; in msdc_auto_cmd_done()
1058 cmd->error = -ETIMEDOUT; in msdc_auto_cmd_done()
1059 host->error |= REQ_STOP_TMO; in msdc_auto_cmd_done()
1061 dev_err(host->dev, in msdc_auto_cmd_done()
1063 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); in msdc_auto_cmd_done()
1065 return cmd->error; in msdc_auto_cmd_done()
1069 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1080 if (mmc->caps & MMC_CAP_SDIO_IRQ) { in msdc_recheck_sdio_irq()
1081 reg_inten = readl(host->base + MSDC_INTEN); in msdc_recheck_sdio_irq()
1083 reg_int = readl(host->base + MSDC_INT); in msdc_recheck_sdio_irq()
1084 reg_ps = readl(host->base + MSDC_PS); in msdc_recheck_sdio_irq()
1097 if (host->error) in msdc_track_cmd_data()
1098 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", in msdc_track_cmd_data()
1099 __func__, cmd->opcode, cmd->arg, host->error); in msdc_track_cmd_data()
1110 cancel_delayed_work(&host->req_timeout); in msdc_request_done()
1112 spin_lock_irqsave(&host->lock, flags); in msdc_request_done()
1113 host->mrq = NULL; in msdc_request_done()
1114 spin_unlock_irqrestore(&host->lock, flags); in msdc_request_done()
1116 msdc_track_cmd_data(host, mrq->cmd, mrq->data); in msdc_request_done()
1117 if (mrq->data) in msdc_request_done()
1119 if (host->error) in msdc_request_done()
1122 if (host->dev_comp->recheck_sdio_irq) in msdc_request_done()
1135 if (mrq->sbc && cmd == mrq->cmd && in msdc_cmd_done()
1138 msdc_auto_cmd_done(host, events, mrq->sbc); in msdc_cmd_done()
1140 sbc_error = mrq->sbc && mrq->sbc->error; in msdc_cmd_done()
1147 spin_lock_irqsave(&host->lock, flags); in msdc_cmd_done()
1148 done = !host->cmd; in msdc_cmd_done()
1149 host->cmd = NULL; in msdc_cmd_done()
1150 spin_unlock_irqrestore(&host->lock, flags); in msdc_cmd_done()
1154 rsp = cmd->resp; in msdc_cmd_done()
1156 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_cmd_done()
1158 if (cmd->flags & MMC_RSP_PRESENT) { in msdc_cmd_done()
1159 if (cmd->flags & MMC_RSP_136) { in msdc_cmd_done()
1160 rsp[0] = readl(host->base + SDC_RESP3); in msdc_cmd_done()
1161 rsp[1] = readl(host->base + SDC_RESP2); in msdc_cmd_done()
1162 rsp[2] = readl(host->base + SDC_RESP1); in msdc_cmd_done()
1163 rsp[3] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1165 rsp[0] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1171 (cmd->opcode != MMC_SEND_TUNING_BLOCK && in msdc_cmd_done()
1172 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) in msdc_cmd_done()
1180 cmd->error = -EILSEQ; in msdc_cmd_done()
1181 host->error |= REQ_CMD_EIO; in msdc_cmd_done()
1183 cmd->error = -ETIMEDOUT; in msdc_cmd_done()
1184 host->error |= REQ_CMD_TMO; in msdc_cmd_done()
1187 if (cmd->error) in msdc_cmd_done()
1188 dev_dbg(host->dev, in msdc_cmd_done()
1190 __func__, cmd->opcode, cmd->arg, rsp[0], in msdc_cmd_done()
1191 cmd->error); in msdc_cmd_done()
1207 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && in msdc_cmd_is_ready()
1210 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { in msdc_cmd_is_ready()
1211 dev_err(host->dev, "CMD bus busy detected\n"); in msdc_cmd_is_ready()
1212 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1217 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { in msdc_cmd_is_ready()
1220 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && in msdc_cmd_is_ready()
1223 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { in msdc_cmd_is_ready()
1224 dev_err(host->dev, "Controller busy detected\n"); in msdc_cmd_is_ready()
1225 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1239 WARN_ON(host->cmd); in msdc_start_command()
1240 host->cmd = cmd; in msdc_start_command()
1242 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_command()
1246 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || in msdc_start_command()
1247 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { in msdc_start_command()
1248 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); in msdc_start_command()
1252 cmd->error = 0; in msdc_start_command()
1255 spin_lock_irqsave(&host->lock, flags); in msdc_start_command()
1256 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_start_command()
1257 spin_unlock_irqrestore(&host->lock, flags); in msdc_start_command()
1259 writel(cmd->arg, host->base + SDC_ARG); in msdc_start_command()
1260 writel(rawcmd, host->base + SDC_CMD); in msdc_start_command()
1266 if ((cmd->error && in msdc_cmd_next()
1267 !(cmd->error == -EILSEQ && in msdc_cmd_next()
1268 (cmd->opcode == MMC_SEND_TUNING_BLOCK || in msdc_cmd_next()
1269 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || in msdc_cmd_next()
1270 (mrq->sbc && mrq->sbc->error)) in msdc_cmd_next()
1272 else if (cmd == mrq->sbc) in msdc_cmd_next()
1273 msdc_start_command(host, mrq, mrq->cmd); in msdc_cmd_next()
1274 else if (!cmd->data) in msdc_cmd_next()
1277 msdc_start_data(host, mrq, cmd, cmd->data); in msdc_cmd_next()
1284 host->error = 0; in msdc_ops_request()
1285 WARN_ON(host->mrq); in msdc_ops_request()
1286 host->mrq = mrq; in msdc_ops_request()
1288 if (mrq->data) in msdc_ops_request()
1295 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || in msdc_ops_request()
1296 (mrq->sbc->arg & 0xFFFF0000))) in msdc_ops_request()
1297 msdc_start_command(host, mrq, mrq->sbc); in msdc_ops_request()
1299 msdc_start_command(host, mrq, mrq->cmd); in msdc_ops_request()
1305 struct mmc_data *data = mrq->data; in msdc_pre_req()
1311 data->host_cookie |= MSDC_ASYNC_FLAG; in msdc_pre_req()
1320 data = mrq->data; in msdc_post_req()
1323 if (data->host_cookie) { in msdc_post_req()
1324 data->host_cookie &= ~MSDC_ASYNC_FLAG; in msdc_post_req()
1332 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && in msdc_data_xfer_next()
1333 !mrq->sbc) in msdc_data_xfer_next()
1334 msdc_start_command(host, mrq, mrq->stop); in msdc_data_xfer_next()
1350 spin_lock_irqsave(&host->lock, flags); in msdc_data_xfer_done()
1351 done = !host->data; in msdc_data_xfer_done()
1353 host->data = NULL; in msdc_data_xfer_done()
1354 spin_unlock_irqrestore(&host->lock, flags); in msdc_data_xfer_done()
1358 stop = data->stop; in msdc_data_xfer_done()
1360 if (check_data || (stop && stop->error)) { in msdc_data_xfer_done()
1361 dev_dbg(host->dev, "DMA status: 0x%8X\n", in msdc_data_xfer_done()
1362 readl(host->base + MSDC_DMA_CFG)); in msdc_data_xfer_done()
1363 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, in msdc_data_xfer_done()
1365 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) in msdc_data_xfer_done()
1367 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_data_xfer_done()
1368 dev_dbg(host->dev, "DMA stop\n"); in msdc_data_xfer_done()
1370 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { in msdc_data_xfer_done()
1371 data->bytes_xfered = data->blocks * data->blksz; in msdc_data_xfer_done()
1373 dev_dbg(host->dev, "interrupt events: %x\n", events); in msdc_data_xfer_done()
1375 host->error |= REQ_DAT_ERR; in msdc_data_xfer_done()
1376 data->bytes_xfered = 0; in msdc_data_xfer_done()
1379 data->error = -ETIMEDOUT; in msdc_data_xfer_done()
1381 data->error = -EILSEQ; in msdc_data_xfer_done()
1383 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", in msdc_data_xfer_done()
1384 __func__, mrq->cmd->opcode, data->blocks); in msdc_data_xfer_done()
1385 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", in msdc_data_xfer_done()
1386 (int)data->error, data->bytes_xfered); in msdc_data_xfer_done()
1397 u32 val = readl(host->base + SDC_CFG); in msdc_set_buswidth()
1414 writel(val, host->base + SDC_CFG); in msdc_set_buswidth()
1415 dev_dbg(host->dev, "Bus Width = %d", width); in msdc_set_buswidth()
1423 if (!IS_ERR(mmc->supply.vqmmc)) { in msdc_ops_switch_volt()
1424 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && in msdc_ops_switch_volt()
1425 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { in msdc_ops_switch_volt()
1426 dev_err(host->dev, "Unsupported signal voltage!\n"); in msdc_ops_switch_volt()
1427 return -EINVAL; in msdc_ops_switch_volt()
1432 dev_dbg(host->dev, "Regulator set error %d (%d)\n", in msdc_ops_switch_volt()
1433 ret, ios->signal_voltage); in msdc_ops_switch_volt()
1438 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in msdc_ops_switch_volt()
1439 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_ops_switch_volt()
1441 pinctrl_select_state(host->pinctrl, host->pins_default); in msdc_ops_switch_volt()
1449 u32 status = readl(host->base + MSDC_PS); in msdc_card_busy()
1451 /* only check if data0 is low */ in msdc_card_busy()
1461 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); in msdc_request_timeout()
1462 if (host->mrq) { in msdc_request_timeout()
1463 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, in msdc_request_timeout()
1464 host->mrq, host->mrq->cmd->opcode); in msdc_request_timeout()
1465 if (host->cmd) { in msdc_request_timeout()
1466 dev_err(host->dev, "%s: aborting cmd=%d\n", in msdc_request_timeout()
1467 __func__, host->cmd->opcode); in msdc_request_timeout()
1468 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, in msdc_request_timeout()
1469 host->cmd); in msdc_request_timeout()
1470 } else if (host->data) { in msdc_request_timeout()
1471 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", in msdc_request_timeout()
1472 __func__, host->mrq->cmd->opcode, in msdc_request_timeout()
1473 host->data->blocks); in msdc_request_timeout()
1474 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, in msdc_request_timeout()
1475 host->data); in msdc_request_timeout()
1483 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1484 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1485 if (host->dev_comp->recheck_sdio_irq) in __msdc_enable_sdio_irq()
1488 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1489 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1498 spin_lock_irqsave(&host->lock, flags); in msdc_enable_sdio_irq()
1500 spin_unlock_irqrestore(&host->lock, flags); in msdc_enable_sdio_irq()
1503 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1505 pm_runtime_put_noidle(host->dev); in msdc_enable_sdio_irq()
1514 cmd_err = -EILSEQ; in msdc_cmdq_irq()
1515 dev_err(host->dev, "%s: CMD CRC ERR", __func__); in msdc_cmdq_irq()
1517 cmd_err = -ETIMEDOUT; in msdc_cmdq_irq()
1518 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1522 dat_err = -EILSEQ; in msdc_cmdq_irq()
1523 dev_err(host->dev, "%s: DATA CRC ERR", __func__); in msdc_cmdq_irq()
1525 dat_err = -ETIMEDOUT; in msdc_cmdq_irq()
1526 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1530 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", in msdc_cmdq_irq()
1549 spin_lock_irqsave(&host->lock, flags); in msdc_irq()
1550 events = readl(host->base + MSDC_INT); in msdc_irq()
1551 event_mask = readl(host->base + MSDC_INTEN); in msdc_irq()
1555 writel(events & event_mask, host->base + MSDC_INT); in msdc_irq()
1557 mrq = host->mrq; in msdc_irq()
1558 cmd = host->cmd; in msdc_irq()
1559 data = host->data; in msdc_irq()
1560 spin_unlock_irqrestore(&host->lock, flags); in msdc_irq()
1566 if (host->internal_cd) in msdc_irq()
1574 if ((mmc->caps2 & MMC_CAP2_CQE) && in msdc_irq()
1578 writel(events, host->base + MSDC_INT); in msdc_irq()
1583 dev_err(host->dev, in msdc_irq()
1590 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); in msdc_irq()
1604 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_init_hw()
1606 if (host->reset) { in msdc_init_hw()
1607 reset_control_assert(host->reset); in msdc_init_hw()
1609 reset_control_deassert(host->reset); in msdc_init_hw()
1613 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
1619 writel(0, host->base + MSDC_INTEN); in msdc_init_hw()
1620 val = readl(host->base + MSDC_INT); in msdc_init_hw()
1621 writel(val, host->base + MSDC_INT); in msdc_init_hw()
1624 if (host->internal_cd) { in msdc_init_hw()
1625 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, in msdc_init_hw()
1627 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1628 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1629 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1631 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1632 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1633 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1636 if (host->top_base) { in msdc_init_hw()
1637 writel(0, host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1638 writel(0, host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1640 writel(0, host->base + tune_reg); in msdc_init_hw()
1642 writel(0, host->base + MSDC_IOCON); in msdc_init_hw()
1643 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); in msdc_init_hw()
1644 writel(0x403c0046, host->base + MSDC_PATCH_BIT); in msdc_init_hw()
1645 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); in msdc_init_hw()
1646 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); in msdc_init_hw()
1647 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); in msdc_init_hw()
1649 if (host->dev_comp->stop_clk_fix) { in msdc_init_hw()
1650 sdr_set_field(host->base + MSDC_PATCH_BIT1, in msdc_init_hw()
1652 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1654 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1658 if (host->dev_comp->busy_check) in msdc_init_hw()
1659 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); in msdc_init_hw()
1661 if (host->dev_comp->async_fifo) { in msdc_init_hw()
1662 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1664 if (host->dev_comp->enhance_rx) { in msdc_init_hw()
1665 if (host->top_base) in msdc_init_hw()
1666 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1669 sdr_set_bits(host->base + SDC_ADV_CFG0, in msdc_init_hw()
1672 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1674 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1678 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1680 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1684 if (host->dev_comp->support_64g) in msdc_init_hw()
1685 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1687 if (host->dev_comp->data_tune) { in msdc_init_hw()
1688 if (host->top_base) { in msdc_init_hw()
1689 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1691 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1693 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1696 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1702 if (host->top_base) in msdc_init_hw()
1703 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1706 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1713 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1716 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in msdc_init_hw()
1717 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1720 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); in msdc_init_hw()
1722 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1723 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1724 if (host->top_base) { in msdc_init_hw()
1725 host->def_tune_para.emmc_top_control = in msdc_init_hw()
1726 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1727 host->def_tune_para.emmc_top_cmd = in msdc_init_hw()
1728 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1729 host->saved_tune_para.emmc_top_control = in msdc_init_hw()
1730 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1731 host->saved_tune_para.emmc_top_cmd = in msdc_init_hw()
1732 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1734 host->def_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1735 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1737 dev_dbg(host->dev, "init hardware done!"); in msdc_init_hw()
1744 if (host->internal_cd) { in msdc_deinit_hw()
1745 /* Disabled card-detect */ in msdc_deinit_hw()
1746 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_deinit_hw()
1747 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_deinit_hw()
1751 writel(0, host->base + MSDC_INTEN); in msdc_deinit_hw()
1753 val = readl(host->base + MSDC_INT); in msdc_deinit_hw()
1754 writel(val, host->base + MSDC_INT); in msdc_deinit_hw()
1760 struct mt_gpdma_desc *gpd = dma->gpd; in msdc_init_gpd_bd()
1761 struct mt_bdma_desc *bd = dma->bd; in msdc_init_gpd_bd()
1767 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); in msdc_init_gpd_bd()
1768 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ in msdc_init_gpd_bd()
1769 /* gpd->next is must set for desc DMA in msdc_init_gpd_bd()
1772 gpd->next = lower_32_bits(dma_addr); in msdc_init_gpd_bd()
1773 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1774 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; in msdc_init_gpd_bd()
1776 dma_addr = dma->bd_addr; in msdc_init_gpd_bd()
1777 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ in msdc_init_gpd_bd()
1778 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1779 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; in msdc_init_gpd_bd()
1782 for (i = 0; i < (MAX_BD_NUM - 1); i++) { in msdc_init_gpd_bd()
1783 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); in msdc_init_gpd_bd()
1785 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1795 msdc_set_buswidth(host, ios->bus_width); in msdc_ops_set_ios()
1798 switch (ios->power_mode) { in msdc_ops_set_ios()
1800 if (!IS_ERR(mmc->supply.vmmc)) { in msdc_ops_set_ios()
1802 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in msdc_ops_set_ios()
1803 ios->vdd); in msdc_ops_set_ios()
1805 dev_err(host->dev, "Failed to set vmmc power!\n"); in msdc_ops_set_ios()
1811 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in msdc_ops_set_ios()
1812 ret = regulator_enable(mmc->supply.vqmmc); in msdc_ops_set_ios()
1814 dev_err(host->dev, "Failed to set vqmmc power!\n"); in msdc_ops_set_ios()
1816 host->vqmmc_enabled = true; in msdc_ops_set_ios()
1820 if (!IS_ERR(mmc->supply.vmmc)) in msdc_ops_set_ios()
1821 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in msdc_ops_set_ios()
1823 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in msdc_ops_set_ios()
1824 regulator_disable(mmc->supply.vqmmc); in msdc_ops_set_ios()
1825 host->vqmmc_enabled = false; in msdc_ops_set_ios()
1832 if (host->mclk != ios->clock || host->timing != ios->timing) in msdc_ops_set_ios()
1833 msdc_set_mclk(host, ios->timing, ios->clock); in msdc_ops_set_ios()
1846 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { in get_delay_len()
1850 return PAD_DELAY_MAX - start_bit; in get_delay_len()
1861 dev_err(host->dev, "phase error: [map:%x]\n", delay); in get_best_delay()
1882 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", in get_best_delay()
1893 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_cmd_delay()
1895 if (host->top_base) in msdc_set_cmd_delay()
1896 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, in msdc_set_cmd_delay()
1899 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, in msdc_set_cmd_delay()
1905 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_data_delay()
1907 if (host->top_base) in msdc_set_data_delay()
1908 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
1911 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, in msdc_set_data_delay()
1923 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_tune_response()
1927 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in msdc_tune_response()
1928 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in msdc_tune_response()
1929 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
1931 host->hs200_cmd_int_delay); in msdc_tune_response()
1933 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
1957 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
1982 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
1985 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
1990 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) in msdc_tune_response()
1994 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2000 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); in msdc_tune_response()
2002 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, in msdc_tune_response()
2005 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in msdc_tune_response()
2006 return final_delay == 0xff ? -EIO : 0; in msdc_tune_response()
2019 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); in hs400_tune_response()
2020 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); in hs400_tune_response()
2022 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in hs400_tune_response()
2023 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in hs400_tune_response()
2024 sdr_set_field(host->base + MSDC_PAD_TUNE, in hs400_tune_response()
2026 host->hs200_cmd_int_delay); in hs400_tune_response()
2028 if (host->hs400_cmd_resp_sel_rising) in hs400_tune_response()
2029 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2031 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2033 sdr_set_field(host->base + PAD_CMD_TUNE, in hs400_tune_response()
2051 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, in hs400_tune_response()
2055 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in hs400_tune_response()
2056 return final_delay == 0xff ? -EIO : 0; in hs400_tune_response()
2067 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_data()
2068 host->latch_ck); in msdc_tune_data()
2069 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2070 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2083 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2084 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2096 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2097 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2100 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2101 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2106 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); in msdc_tune_data()
2107 return final_delay == 0xff ? -EIO : 0; in msdc_tune_data()
2122 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_together()
2123 host->latch_ck); in msdc_tune_together()
2125 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2126 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2141 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2142 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2156 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2157 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2161 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2162 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2170 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); in msdc_tune_together()
2171 return final_delay == 0xff ? -EIO : 0; in msdc_tune_together()
2178 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_execute_tuning()
2180 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { in msdc_execute_tuning()
2182 if (host->hs400_mode) { in msdc_execute_tuning()
2183 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_execute_tuning()
2189 if (host->hs400_mode && in msdc_execute_tuning()
2190 host->dev_comp->hs400_tune) in msdc_execute_tuning()
2194 if (ret == -EIO) { in msdc_execute_tuning()
2195 dev_err(host->dev, "Tune response fail!\n"); in msdc_execute_tuning()
2198 if (host->hs400_mode == false) { in msdc_execute_tuning()
2200 if (ret == -EIO) in msdc_execute_tuning()
2201 dev_err(host->dev, "Tune data fail!\n"); in msdc_execute_tuning()
2205 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_execute_tuning()
2206 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_execute_tuning()
2207 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_execute_tuning()
2208 if (host->top_base) { in msdc_execute_tuning()
2209 host->saved_tune_para.emmc_top_control = readl(host->top_base + in msdc_execute_tuning()
2211 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + in msdc_execute_tuning()
2220 host->hs400_mode = true; in msdc_prepare_hs400_tuning()
2222 if (host->top_base) in msdc_prepare_hs400_tuning()
2223 writel(host->hs400_ds_delay, in msdc_prepare_hs400_tuning()
2224 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2226 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2228 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); in msdc_prepare_hs400_tuning()
2230 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); in msdc_prepare_hs400_tuning()
2239 sdr_set_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2241 sdr_clr_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2249 spin_lock_irqsave(&host->lock, flags); in msdc_ack_sdio_irq()
2251 spin_unlock_irqrestore(&host->lock, flags); in msdc_ack_sdio_irq()
2259 if (mmc->caps & MMC_CAP_NONREMOVABLE) in msdc_get_cd()
2262 if (!host->internal_cd) in msdc_get_cd()
2265 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; in msdc_get_cd()
2266 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) in msdc_get_cd()
2277 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); in msdc_cqe_enable()
2279 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_enable()
2292 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); in msdc_cqe_disable()
2294 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_disable()
2296 val = readl(host->base + MSDC_INT); in msdc_cqe_disable()
2297 writel(val, host->base + MSDC_INT); in msdc_cqe_disable()
2300 sdr_set_field(host->base + MSDC_DMA_CTRL, in msdc_cqe_disable()
2302 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, in msdc_cqe_disable()
2311 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_pre_enable()
2321 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_post_disable()
2355 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", in msdc_of_property_parse()
2356 &host->latch_ck); in msdc_of_property_parse()
2358 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", in msdc_of_property_parse()
2359 &host->hs400_ds_delay); in msdc_of_property_parse()
2361 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", in msdc_of_property_parse()
2362 &host->hs200_cmd_int_delay); in msdc_of_property_parse()
2364 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", in msdc_of_property_parse()
2365 &host->hs400_cmd_int_delay); in msdc_of_property_parse()
2367 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2368 "mediatek,hs400-cmd-resp-sel-rising")) in msdc_of_property_parse()
2369 host->hs400_cmd_resp_sel_rising = true; in msdc_of_property_parse()
2371 host->hs400_cmd_resp_sel_rising = false; in msdc_of_property_parse()
2373 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2374 "supports-cqe")) in msdc_of_property_parse()
2375 host->cqhci = true; in msdc_of_property_parse()
2377 host->cqhci = false; in msdc_of_property_parse()
2387 if (!pdev->dev.of_node) { in msdc_drv_probe()
2388 dev_err(&pdev->dev, "No DT found\n"); in msdc_drv_probe()
2389 return -EINVAL; in msdc_drv_probe()
2393 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); in msdc_drv_probe()
2395 return -ENOMEM; in msdc_drv_probe()
2402 host->base = devm_platform_ioremap_resource(pdev, 0); in msdc_drv_probe()
2403 if (IS_ERR(host->base)) { in msdc_drv_probe()
2404 ret = PTR_ERR(host->base); in msdc_drv_probe()
2410 host->top_base = devm_ioremap_resource(&pdev->dev, res); in msdc_drv_probe()
2411 if (IS_ERR(host->top_base)) in msdc_drv_probe()
2412 host->top_base = NULL; in msdc_drv_probe()
2419 host->src_clk = devm_clk_get(&pdev->dev, "source"); in msdc_drv_probe()
2420 if (IS_ERR(host->src_clk)) { in msdc_drv_probe()
2421 ret = PTR_ERR(host->src_clk); in msdc_drv_probe()
2425 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); in msdc_drv_probe()
2426 if (IS_ERR(host->h_clk)) { in msdc_drv_probe()
2427 ret = PTR_ERR(host->h_clk); in msdc_drv_probe()
2431 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); in msdc_drv_probe()
2432 if (IS_ERR(host->bus_clk)) in msdc_drv_probe()
2433 host->bus_clk = NULL; in msdc_drv_probe()
2435 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); in msdc_drv_probe()
2436 if (IS_ERR(host->src_clk_cg)) in msdc_drv_probe()
2437 host->src_clk_cg = NULL; in msdc_drv_probe()
2439 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, in msdc_drv_probe()
2441 if (IS_ERR(host->reset)) in msdc_drv_probe()
2442 return PTR_ERR(host->reset); in msdc_drv_probe()
2444 host->irq = platform_get_irq(pdev, 0); in msdc_drv_probe()
2445 if (host->irq < 0) { in msdc_drv_probe()
2446 ret = host->irq; in msdc_drv_probe()
2450 host->pinctrl = devm_pinctrl_get(&pdev->dev); in msdc_drv_probe()
2451 if (IS_ERR(host->pinctrl)) { in msdc_drv_probe()
2452 ret = PTR_ERR(host->pinctrl); in msdc_drv_probe()
2453 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); in msdc_drv_probe()
2457 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); in msdc_drv_probe()
2458 if (IS_ERR(host->pins_default)) { in msdc_drv_probe()
2459 ret = PTR_ERR(host->pins_default); in msdc_drv_probe()
2460 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); in msdc_drv_probe()
2464 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); in msdc_drv_probe()
2465 if (IS_ERR(host->pins_uhs)) { in msdc_drv_probe()
2466 ret = PTR_ERR(host->pins_uhs); in msdc_drv_probe()
2467 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); in msdc_drv_probe()
2473 host->dev = &pdev->dev; in msdc_drv_probe()
2474 host->dev_comp = of_device_get_match_data(&pdev->dev); in msdc_drv_probe()
2475 host->src_clk_freq = clk_get_rate(host->src_clk); in msdc_drv_probe()
2477 mmc->ops = &mt_msdc_ops; in msdc_drv_probe()
2478 if (host->dev_comp->clk_div_bits == 8) in msdc_drv_probe()
2479 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); in msdc_drv_probe()
2481 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); in msdc_drv_probe()
2483 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && in msdc_drv_probe()
2485 host->dev_comp->use_internal_cd) { in msdc_drv_probe()
2490 host->internal_cd = true; in msdc_drv_probe()
2493 if (mmc->caps & MMC_CAP_SDIO_IRQ) in msdc_drv_probe()
2494 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in msdc_drv_probe()
2496 mmc->caps |= MMC_CAP_CMD23; in msdc_drv_probe()
2497 if (host->cqhci) in msdc_drv_probe()
2498 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in msdc_drv_probe()
2500 mmc->max_segs = MAX_BD_NUM; in msdc_drv_probe()
2501 if (host->dev_comp->support_64g) in msdc_drv_probe()
2502 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; in msdc_drv_probe()
2504 mmc->max_seg_size = BDMA_DESC_BUFLEN; in msdc_drv_probe()
2505 mmc->max_blk_size = 2048; in msdc_drv_probe()
2506 mmc->max_req_size = 512 * 1024; in msdc_drv_probe()
2507 mmc->max_blk_count = mmc->max_req_size / 512; in msdc_drv_probe()
2508 if (host->dev_comp->support_64g) in msdc_drv_probe()
2509 host->dma_mask = DMA_BIT_MASK(36); in msdc_drv_probe()
2511 host->dma_mask = DMA_BIT_MASK(32); in msdc_drv_probe()
2512 mmc_dev(mmc)->dma_mask = &host->dma_mask; in msdc_drv_probe()
2514 host->timeout_clks = 3 * 1048576; in msdc_drv_probe()
2515 host->dma.gpd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2517 &host->dma.gpd_addr, GFP_KERNEL); in msdc_drv_probe()
2518 host->dma.bd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2520 &host->dma.bd_addr, GFP_KERNEL); in msdc_drv_probe()
2521 if (!host->dma.gpd || !host->dma.bd) { in msdc_drv_probe()
2522 ret = -ENOMEM; in msdc_drv_probe()
2525 msdc_init_gpd_bd(host, &host->dma); in msdc_drv_probe()
2526 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); in msdc_drv_probe()
2527 spin_lock_init(&host->lock); in msdc_drv_probe()
2533 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_drv_probe()
2534 host->cq_host = devm_kzalloc(mmc->parent, in msdc_drv_probe()
2535 sizeof(*host->cq_host), in msdc_drv_probe()
2537 if (!host->cq_host) { in msdc_drv_probe()
2538 ret = -ENOMEM; in msdc_drv_probe()
2541 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in msdc_drv_probe()
2542 host->cq_host->mmio = host->base + 0x800; in msdc_drv_probe()
2543 host->cq_host->ops = &msdc_cmdq_ops; in msdc_drv_probe()
2544 ret = cqhci_init(host->cq_host, mmc, true); in msdc_drv_probe()
2547 mmc->max_segs = 128; in msdc_drv_probe()
2549 /* 0 size, means 65536 so we don't have to -1 here */ in msdc_drv_probe()
2550 mmc->max_seg_size = 64 * 1024; in msdc_drv_probe()
2553 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, in msdc_drv_probe()
2554 IRQF_TRIGGER_NONE, pdev->name, host); in msdc_drv_probe()
2558 pm_runtime_set_active(host->dev); in msdc_drv_probe()
2559 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); in msdc_drv_probe()
2560 pm_runtime_use_autosuspend(host->dev); in msdc_drv_probe()
2561 pm_runtime_enable(host->dev); in msdc_drv_probe()
2569 pm_runtime_disable(host->dev); in msdc_drv_probe()
2575 if (host->dma.gpd) in msdc_drv_probe()
2576 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
2578 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_probe()
2579 if (host->dma.bd) in msdc_drv_probe()
2580 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
2582 host->dma.bd, host->dma.bd_addr); in msdc_drv_probe()
2597 pm_runtime_get_sync(host->dev); in msdc_drv_remove()
2604 pm_runtime_disable(host->dev); in msdc_drv_remove()
2605 pm_runtime_put_noidle(host->dev); in msdc_drv_remove()
2606 dma_free_coherent(&pdev->dev, in msdc_drv_remove()
2608 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_remove()
2609 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), in msdc_drv_remove()
2610 host->dma.bd, host->dma.bd_addr); in msdc_drv_remove()
2619 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_save_reg()
2621 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
2622 host->save_para.iocon = readl(host->base + MSDC_IOCON); in msdc_save_reg()
2623 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); in msdc_save_reg()
2624 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); in msdc_save_reg()
2625 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); in msdc_save_reg()
2626 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); in msdc_save_reg()
2627 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); in msdc_save_reg()
2628 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_save_reg()
2629 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); in msdc_save_reg()
2630 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); in msdc_save_reg()
2631 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); in msdc_save_reg()
2632 if (host->top_base) { in msdc_save_reg()
2633 host->save_para.emmc_top_control = in msdc_save_reg()
2634 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_save_reg()
2635 host->save_para.emmc_top_cmd = in msdc_save_reg()
2636 readl(host->top_base + EMMC_TOP_CMD); in msdc_save_reg()
2637 host->save_para.emmc50_pad_ds_tune = in msdc_save_reg()
2638 readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_save_reg()
2640 host->save_para.pad_tune = readl(host->base + tune_reg); in msdc_save_reg()
2647 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_restore_reg()
2649 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()
2650 writel(host->save_para.iocon, host->base + MSDC_IOCON); in msdc_restore_reg()
2651 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); in msdc_restore_reg()
2652 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); in msdc_restore_reg()
2653 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); in msdc_restore_reg()
2654 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); in msdc_restore_reg()
2655 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); in msdc_restore_reg()
2656 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); in msdc_restore_reg()
2657 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); in msdc_restore_reg()
2658 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); in msdc_restore_reg()
2659 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); in msdc_restore_reg()
2660 if (host->top_base) { in msdc_restore_reg()
2661 writel(host->save_para.emmc_top_control, in msdc_restore_reg()
2662 host->top_base + EMMC_TOP_CONTROL); in msdc_restore_reg()
2663 writel(host->save_para.emmc_top_cmd, in msdc_restore_reg()
2664 host->top_base + EMMC_TOP_CMD); in msdc_restore_reg()
2665 writel(host->save_para.emmc50_pad_ds_tune, in msdc_restore_reg()
2666 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_restore_reg()
2668 writel(host->save_para.pad_tune, host->base + tune_reg); in msdc_restore_reg()
2701 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_suspend()
2705 val = readl(((struct msdc_host *)mmc_priv(mmc))->base + MSDC_INT); in msdc_suspend()
2706 writel(val, ((struct msdc_host *)mmc_priv(mmc))->base + MSDC_INT); in msdc_suspend()
2726 .name = "mtk-msdc",