Lines Matching full:esdhc

3  * Freescale eSDHC i.MX controller driver for the platform bus.
27 #include <linux/platform_data/mmc-esdhc-imx.h>
31 #include "sdhci-esdhc.h"
122  * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC:
123  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
124  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
125  * Define this macro DMA error INT for fsl eSDHC
145  * The flag tells that the ESDHC controller is an USDHC block that is
300 	{ .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, },
301 	{ .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, },
302 	{ .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, },
303 	{ .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, },
345 #define DRIVER_NAME "sdhci-esdhc-imx"
361 	ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n");  in esdhc_dump_debug_regs()
405 		/* In FSL esdhc IC module, only bit20 is used to indicate the  in esdhc_readl_le()
406 		 * ADMA2 capability of esdhc, but this bit is messed up on  in esdhc_readl_le()
484 			 * card interrupt. This is an eSDHC controller problem  in esdhc_writel_le()
486 			 * and set D3CD bit will make eSDHC re-sample the card  in esdhc_writel_le()
785 			 * The esdhc has a design violation to SDHC spec which  in esdhc_writeb_le()
787 			 * detection circuit. But esdhc clears its SYSCTL  in esdhc_writeb_le()
809 			 * The eSDHC DAT line software reset clears at least the  in esdhc_writeb_le()
1868 		.name	= "sdhci-esdhc-imx",
1879 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");