Lines Matching +full:default +full:- +full:sample +full:- +full:phase
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
25 #include <linux/firmware/xlnx-zynqmp.h>
28 #include "sdhci-cqhci.h"
29 #include "sdhci-pltfm.h"
48 /* Default settings for ZynqMP Clock Phases */
56 * On some SoCs the syscon area has a feature where the upper 16-bits of
57 * each 32-bit register act as a write mask for the lower 16-bits. This allows
65 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
69 * @shift: Bit offset within @reg of this field (or -1 if not avail)
78 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
97 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
100 * @sampleclk_ops: The sample clock related operations
108 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
114 * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
115 * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
131 * struct sdhci_arasan_data - Arasan Controller Data
165 * met at 25MHz for Default Speed mode, those controllers work at
185 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
191 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
203 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
222 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; in sdhci_arasan_syscon_write()
223 u32 reg = fld->reg; in sdhci_arasan_syscon_write()
224 u16 width = fld->width; in sdhci_arasan_syscon_write()
225 s16 shift = fld->shift; in sdhci_arasan_syscon_write()
235 return -EINVAL; in sdhci_arasan_syscon_write()
237 if (sdhci_arasan->soc_ctl_map->hiword_update) in sdhci_arasan_syscon_write()
249 mmc_hostname(host->mmc), ret); in sdhci_arasan_syscon_write()
258 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_set_clock()
261 if (!IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
262 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { in sdhci_arasan_set_clock()
276 sdhci_set_clock(host, host->max_clk); in sdhci_arasan_set_clock()
277 if (phy_power_on(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
279 mmc_hostname(host->mmc)); in sdhci_arasan_set_clock()
283 sdhci_arasan->is_phy_on = true; in sdhci_arasan_set_clock()
300 if (ctrl_phy && sdhci_arasan->is_phy_on) { in sdhci_arasan_set_clock()
301 phy_power_off(sdhci_arasan->phy); in sdhci_arasan_set_clock()
302 sdhci_arasan->is_phy_on = false; in sdhci_arasan_set_clock()
305 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) { in sdhci_arasan_set_clock()
308 * requirements met at 25MHz for Default Speed mode, in sdhci_arasan_set_clock()
315 /* Set the Input and Output Clock Phase Delays */ in sdhci_arasan_set_clock()
316 if (clk_data->set_clk_delays) in sdhci_arasan_set_clock()
317 clk_data->set_clk_delays(host); in sdhci_arasan_set_clock()
321 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) in sdhci_arasan_set_clock()
332 if (phy_power_on(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
334 mmc_hostname(host->mmc)); in sdhci_arasan_set_clock()
338 sdhci_arasan->is_phy_on = true; in sdhci_arasan_set_clock()
349 if (ios->enhanced_strobe) in sdhci_arasan_hs400_enhanced_strobe()
365 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { in sdhci_arasan_reset()
375 switch (ios->signal_voltage) { in sdhci_arasan_voltage_switch()
391 return -EINVAL; in sdhci_arasan_voltage_switch()
412 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_arasan_cqhci_irq()
462 * sdhci_arasan_suspend - Suspend method for the driver
476 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_arasan_suspend()
477 mmc_retune_needed(host->mmc); in sdhci_arasan_suspend()
479 if (sdhci_arasan->has_cqe) { in sdhci_arasan_suspend()
480 ret = cqhci_suspend(host->mmc); in sdhci_arasan_suspend()
489 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { in sdhci_arasan_suspend()
490 ret = phy_power_off(sdhci_arasan->phy); in sdhci_arasan_suspend()
498 sdhci_arasan->is_phy_on = false; in sdhci_arasan_suspend()
501 clk_disable(pltfm_host->clk); in sdhci_arasan_suspend()
502 clk_disable(sdhci_arasan->clk_ahb); in sdhci_arasan_suspend()
508 * sdhci_arasan_resume - Resume method for the driver
522 ret = clk_enable(sdhci_arasan->clk_ahb); in sdhci_arasan_resume()
528 ret = clk_enable(pltfm_host->clk); in sdhci_arasan_resume()
534 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { in sdhci_arasan_resume()
535 ret = phy_power_on(sdhci_arasan->phy); in sdhci_arasan_resume()
540 sdhci_arasan->is_phy_on = true; in sdhci_arasan_resume()
549 if (sdhci_arasan->has_cqe) in sdhci_arasan_resume()
550 return cqhci_resume(host->mmc); in sdhci_arasan_resume()
560 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
577 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_sdcardclk_recalc_rate()
579 return host->mmc->actual_clock; in sdhci_arasan_sdcardclk_recalc_rate()
587 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
595 * Return: The sample clock rate.
604 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_sampleclk_recalc_rate()
606 return host->mmc->actual_clock; in sdhci_arasan_sampleclk_recalc_rate()
614 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
617 * @degrees: The clock phase shift between 0 - 359.
629 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_sdcardclk_set_phase()
636 if (host->version < SDHCI_SPEC_300) in sdhci_zynqmp_sdcardclk_set_phase()
639 switch (host->timing) { in sdhci_zynqmp_sdcardclk_set_phase()
656 default: in sdhci_zynqmp_sdcardclk_set_phase()
662 /* Set the Clock Phase */ in sdhci_zynqmp_sdcardclk_set_phase()
679 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
682 * @degrees: The clock phase shift between 0 - 359.
694 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_sampleclk_set_phase()
701 if (host->version < SDHCI_SPEC_300) in sdhci_zynqmp_sampleclk_set_phase()
707 switch (host->timing) { in sdhci_zynqmp_sampleclk_set_phase()
724 default: in sdhci_zynqmp_sampleclk_set_phase()
730 /* Set the Clock Phase */ in sdhci_zynqmp_sampleclk_set_phase()
744 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
747 * @degrees: The clock phase shift between 0 - 359.
759 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_sdcardclk_set_phase()
763 if (host->version < SDHCI_SPEC_300) in sdhci_versal_sdcardclk_set_phase()
766 switch (host->timing) { in sdhci_versal_sdcardclk_set_phase()
783 default: in sdhci_versal_sdcardclk_set_phase()
789 /* Set the Clock Phase */ in sdhci_versal_sdcardclk_set_phase()
810 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
813 * @degrees: The clock phase shift between 0 - 359.
825 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_sampleclk_set_phase()
829 if (host->version < SDHCI_SPEC_300) in sdhci_versal_sampleclk_set_phase()
832 switch (host->timing) { in sdhci_versal_sampleclk_set_phase()
849 default: in sdhci_versal_sampleclk_set_phase()
855 /* Set the Clock Phase */ in sdhci_versal_sampleclk_set_phase()
900 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; in arasan_zynqmp_execute_tuning()
918 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
927 * - Many existing devices don't seem to do this and work fine. To keep
931 * - The value of corecfg_clockmultiplier should sync with that of corresponding
941 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_clockmultiplier()
948 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_clockmultiplier()
949 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_clockmultiplier()
950 mmc_hostname(host->mmc)); in sdhci_arasan_update_clockmultiplier()
954 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); in sdhci_arasan_update_clockmultiplier()
958 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
966 * - Many existing devices don't seem to do this and work fine. To keep
970 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
979 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_baseclkfreq()
980 u32 mhz = DIV_ROUND_CLOSEST(clk_get_rate(pltfm_host->clk), 1000000); in sdhci_arasan_update_baseclkfreq()
987 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_baseclkfreq()
988 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_baseclkfreq()
989 mmc_hostname(host->mmc)); in sdhci_arasan_update_baseclkfreq()
993 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); in sdhci_arasan_update_baseclkfreq()
1000 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_set_clk_delays()
1002 clk_set_phase(clk_data->sampleclk, in sdhci_arasan_set_clk_delays()
1003 clk_data->clk_phase_in[host->timing]); in sdhci_arasan_set_clk_delays()
1004 clk_set_phase(clk_data->sdcardclk, in sdhci_arasan_set_clk_delays()
1005 clk_data->clk_phase_out[host->timing]); in sdhci_arasan_set_clk_delays()
1012 struct device_node *np = dev->of_node; in arasan_dt_read_clk_phase()
1018 * Tap Values then use the pre-defined values. in arasan_dt_read_clk_phase()
1022 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n", in arasan_dt_read_clk_phase()
1023 prop, clk_data->clk_phase_in[timing], in arasan_dt_read_clk_phase()
1024 clk_data->clk_phase_out[timing]); in arasan_dt_read_clk_phase()
1029 clk_data->clk_phase_in[timing] = clk_phase[0]; in arasan_dt_read_clk_phase()
1030 clk_data->clk_phase_out[timing] = clk_phase[1]; in arasan_dt_read_clk_phase()
1034 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1052 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; in arasan_dt_parse_clk_phases()
1054 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { in arasan_dt_parse_clk_phases()
1060 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); in arasan_dt_parse_clk_phases()
1067 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1068 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1072 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) { in arasan_dt_parse_clk_phases()
1079 clk_data->clk_phase_in[i] = versal_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1080 clk_data->clk_phase_out[i] = versal_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1085 "clk-phase-legacy"); in arasan_dt_parse_clk_phases()
1087 "clk-phase-mmc-hs"); in arasan_dt_parse_clk_phases()
1089 "clk-phase-sd-hs"); in arasan_dt_parse_clk_phases()
1091 "clk-phase-uhs-sdr12"); in arasan_dt_parse_clk_phases()
1093 "clk-phase-uhs-sdr25"); in arasan_dt_parse_clk_phases()
1095 "clk-phase-uhs-sdr50"); in arasan_dt_parse_clk_phases()
1097 "clk-phase-uhs-sdr104"); in arasan_dt_parse_clk_phases()
1099 "clk-phase-uhs-ddr50"); in arasan_dt_parse_clk_phases()
1101 "clk-phase-mmc-ddr52"); in arasan_dt_parse_clk_phases()
1103 "clk-phase-mmc-hs200"); in arasan_dt_parse_clk_phases()
1105 "clk-phase-mmc-hs400"); in arasan_dt_parse_clk_phases()
1234 /* SoC-specific compatible strings w/ soc_ctl_map */
1236 .compatible = "rockchip,rk3399-sdhci-5.1",
1240 .compatible = "intel,lgm-sdhci-5.1-emmc",
1244 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1248 .compatible = "intel,keembay-sdhci-5.1-emmc",
1252 .compatible = "intel,keembay-sdhci-5.1-sd",
1256 .compatible = "intel,keembay-sdhci-5.1-sdio",
1261 .compatible = "arasan,sdhci-8.9a",
1265 .compatible = "arasan,sdhci-5.1",
1269 .compatible = "arasan,sdhci-4.9a",
1273 .compatible = "xlnx,zynqmp-8.9a",
1277 .compatible = "xlnx,versal-8.9a",
1285 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1302 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_register_sdcardclk()
1303 struct device_node *np = dev->of_node; in sdhci_arasan_register_sdcardclk()
1308 ret = of_property_read_string_index(np, "clock-output-names", 0, in sdhci_arasan_register_sdcardclk()
1311 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); in sdhci_arasan_register_sdcardclk()
1319 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops; in sdhci_arasan_register_sdcardclk()
1321 clk_data->sdcardclk_hw.init = &sdcardclk_init; in sdhci_arasan_register_sdcardclk()
1322 clk_data->sdcardclk = in sdhci_arasan_register_sdcardclk()
1323 devm_clk_register(dev, &clk_data->sdcardclk_hw); in sdhci_arasan_register_sdcardclk()
1324 if (IS_ERR(clk_data->sdcardclk)) in sdhci_arasan_register_sdcardclk()
1325 return PTR_ERR(clk_data->sdcardclk); in sdhci_arasan_register_sdcardclk()
1326 clk_data->sdcardclk_hw.init = NULL; in sdhci_arasan_register_sdcardclk()
1329 clk_data->sdcardclk); in sdhci_arasan_register_sdcardclk()
1337 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1354 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_register_sampleclk()
1355 struct device_node *np = dev->of_node; in sdhci_arasan_register_sampleclk()
1360 ret = of_property_read_string_index(np, "clock-output-names", 1, in sdhci_arasan_register_sampleclk()
1363 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); in sdhci_arasan_register_sampleclk()
1371 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops; in sdhci_arasan_register_sampleclk()
1373 clk_data->sampleclk_hw.init = &sampleclk_init; in sdhci_arasan_register_sampleclk()
1374 clk_data->sampleclk = in sdhci_arasan_register_sampleclk()
1375 devm_clk_register(dev, &clk_data->sampleclk_hw); in sdhci_arasan_register_sampleclk()
1376 if (IS_ERR(clk_data->sampleclk)) in sdhci_arasan_register_sampleclk()
1377 return PTR_ERR(clk_data->sampleclk); in sdhci_arasan_register_sampleclk()
1378 clk_data->sampleclk_hw.init = NULL; in sdhci_arasan_register_sampleclk()
1381 clk_data->sampleclk); in sdhci_arasan_register_sampleclk()
1383 dev_err(dev, "Failed to add sample clock provider\n"); in sdhci_arasan_register_sampleclk()
1389 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1398 struct device_node *np = dev->of_node; in sdhci_arasan_unregister_sdclk()
1400 if (!of_find_property(np, "#clock-cells", NULL)) in sdhci_arasan_unregister_sdclk()
1403 of_clk_del_provider(dev->of_node); in sdhci_arasan_unregister_sdclk()
1407 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1410 * 0: the Core supports only 32-bit System Address Bus.
1411 * 1: the Core supports 64-bit System Address Bus.
1414 * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1.
1415 * Keem Bay does not support 64-bit access.
1425 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_support64b()
1432 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_support64b()
1433 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_support64b()
1434 mmc_hostname(host->mmc)); in sdhci_arasan_update_support64b()
1438 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value); in sdhci_arasan_update_support64b()
1442 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1452 * Note: without seriously re-architecting SDHCI's clock code and testing on
1458 * re-architecting SDHCI if we see some benefit to it.
1466 struct device_node *np = dev->of_node; in sdhci_arasan_register_sdclk()
1471 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) in sdhci_arasan_register_sdclk()
1492 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_add_host()
1497 if (!sdhci_arasan->has_cqe) in sdhci_arasan_add_host()
1504 cq_host = devm_kzalloc(host->mmc->parent, in sdhci_arasan_add_host()
1507 ret = -ENOMEM; in sdhci_arasan_add_host()
1511 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; in sdhci_arasan_add_host()
1512 cq_host->ops = &sdhci_arasan_cqhci_ops; in sdhci_arasan_add_host()
1514 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_arasan_add_host()
1516 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_arasan_add_host()
1518 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_arasan_add_host()
1542 struct device_node *np = pdev->dev.of_node; in sdhci_arasan_probe()
1545 match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); in sdhci_arasan_probe()
1546 data = match->data; in sdhci_arasan_probe()
1547 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); in sdhci_arasan_probe()
1554 sdhci_arasan->host = host; in sdhci_arasan_probe()
1556 sdhci_arasan->soc_ctl_map = data->soc_ctl_map; in sdhci_arasan_probe()
1557 sdhci_arasan->clk_ops = data->clk_ops; in sdhci_arasan_probe()
1559 node = of_parse_phandle(pdev->dev.of_node, "arasan,soc-ctl-syscon", 0); in sdhci_arasan_probe()
1561 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); in sdhci_arasan_probe()
1564 if (IS_ERR(sdhci_arasan->soc_ctl_base)) { in sdhci_arasan_probe()
1565 ret = dev_err_probe(&pdev->dev, in sdhci_arasan_probe()
1566 PTR_ERR(sdhci_arasan->soc_ctl_base), in sdhci_arasan_probe()
1572 sdhci_arasan->clk_ahb = devm_clk_get(&pdev->dev, "clk_ahb"); in sdhci_arasan_probe()
1573 if (IS_ERR(sdhci_arasan->clk_ahb)) { in sdhci_arasan_probe()
1574 dev_err(&pdev->dev, "clk_ahb clock not found.\n"); in sdhci_arasan_probe()
1575 ret = PTR_ERR(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
1579 clk_xin = devm_clk_get(&pdev->dev, "clk_xin"); in sdhci_arasan_probe()
1581 dev_err(&pdev->dev, "clk_xin clock not found.\n"); in sdhci_arasan_probe()
1586 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
1588 dev_err(&pdev->dev, "Unable to enable AHB clock.\n"); in sdhci_arasan_probe()
1594 dev_err(&pdev->dev, "Unable to enable SD clock.\n"); in sdhci_arasan_probe()
1600 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) in sdhci_arasan_probe()
1601 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; in sdhci_arasan_probe()
1603 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) in sdhci_arasan_probe()
1604 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; in sdhci_arasan_probe()
1606 pltfm_host->clk = clk_xin; in sdhci_arasan_probe()
1608 if (of_device_is_compatible(pdev->dev.of_node, in sdhci_arasan_probe()
1609 "rockchip,rk3399-sdhci-5.1")) in sdhci_arasan_probe()
1612 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || in sdhci_arasan_probe()
1613 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") || in sdhci_arasan_probe()
1614 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) { in sdhci_arasan_probe()
1618 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in sdhci_arasan_probe()
1623 ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); in sdhci_arasan_probe()
1627 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { in sdhci_arasan_probe()
1628 host->mmc_host_ops.execute_tuning = in sdhci_arasan_probe()
1631 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN; in sdhci_arasan_probe()
1634 arasan_dt_parse_clk_phases(&pdev->dev, &sdhci_arasan->clk_data); in sdhci_arasan_probe()
1636 ret = mmc_of_parse(host->mmc); in sdhci_arasan_probe()
1638 if (ret != -EPROBE_DEFER) in sdhci_arasan_probe()
1639 dev_err(&pdev->dev, "parsing dt failed (%d)\n", ret); in sdhci_arasan_probe()
1643 sdhci_arasan->phy = ERR_PTR(-ENODEV); in sdhci_arasan_probe()
1644 if (of_device_is_compatible(pdev->dev.of_node, in sdhci_arasan_probe()
1645 "arasan,sdhci-5.1")) { in sdhci_arasan_probe()
1646 sdhci_arasan->phy = devm_phy_get(&pdev->dev, in sdhci_arasan_probe()
1648 if (IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_probe()
1649 ret = PTR_ERR(sdhci_arasan->phy); in sdhci_arasan_probe()
1650 dev_err(&pdev->dev, "No phy for arasan,sdhci-5.1.\n"); in sdhci_arasan_probe()
1654 ret = phy_init(sdhci_arasan->phy); in sdhci_arasan_probe()
1656 dev_err(&pdev->dev, "phy_init err.\n"); in sdhci_arasan_probe()
1660 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_arasan_probe()
1662 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_arasan_probe()
1664 sdhci_arasan->has_cqe = true; in sdhci_arasan_probe()
1665 host->mmc->caps2 |= MMC_CAP2_CQE; in sdhci_arasan_probe()
1667 if (!of_property_read_bool(np, "disable-cqe-dcmd")) in sdhci_arasan_probe()
1668 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; in sdhci_arasan_probe()
1678 if (!IS_ERR(sdhci_arasan->phy)) in sdhci_arasan_probe()
1679 phy_exit(sdhci_arasan->phy); in sdhci_arasan_probe()
1681 sdhci_arasan_unregister_sdclk(&pdev->dev); in sdhci_arasan_probe()
1685 clk_disable_unprepare(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
1697 struct clk *clk_ahb = sdhci_arasan->clk_ahb; in sdhci_arasan_remove()
1699 if (!IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_remove()
1700 if (sdhci_arasan->is_phy_on) in sdhci_arasan_remove()
1701 phy_power_off(sdhci_arasan->phy); in sdhci_arasan_remove()
1702 phy_exit(sdhci_arasan->phy); in sdhci_arasan_remove()
1705 sdhci_arasan_unregister_sdclk(&pdev->dev); in sdhci_arasan_remove()
1716 .name = "sdhci-arasan",