Lines Matching full:esdhc
3 * Freescale eSDHC controller driver.
27 #include "sdhci-esdhc.h"
65 { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk},
66 { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk},
67 { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk},
68 { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk},
69 { .compatible = "fsl,mpc8379-esdhc" },
70 { .compatible = "fsl,mpc8536-esdhc" },
71 { .compatible = "fsl,esdhc" },
94 * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register
99 * @value: 32bit eSDHC register value on spec_reg address
101 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
103 * address, register function, bit position and function between eSDHC spec
112 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_readl_fixup() local
116 * The bit of ADMA flag in eSDHC is not compatible with standard in esdhc_readl_fixup()
118 * supported by eSDHC. in esdhc_readl_fixup()
119 * And for many FSL eSDHC controller, the reset value of field in esdhc_readl_fixup()
124 if (esdhc->vendor_ver > VENDOR_V_22) { in esdhc_readl_fixup()
149 if (esdhc->quirk_ignore_data_inhibit) in esdhc_readl_fixup()
173 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_readw_fixup() local
184 /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect in esdhc_readw_fixup()
188 (esdhc->quirk_incorrect_hostver)) in esdhc_readw_fixup()
218 * written into eSDHC register.
223 * @old_value: 32bit eSDHC register value on spec_reg address
225 * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC
227 * address, register function, bit position and function between eSDHC spec
293 * eSDHC doesn't have a standard power control register, so we do in esdhc_writeb_fixup()
419 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_be_writew() local
434 esdhc->in_sw_tuning) { in esdhc_be_writew()
445 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_le_writew() local
460 esdhc->in_sw_tuning) { in esdhc_le_writew()
500 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_of_adma_workaround() local
507 (esdhc->vendor_ver == VENDOR_V_23); in esdhc_of_adma_workaround()
529 if (of_device_is_compatible(dev->of_node, "fsl,ls1043a-esdhc") || in esdhc_of_enable_dma()
530 of_device_is_compatible(dev->of_node, "fsl,ls1046a-esdhc")) { in esdhc_of_enable_dma()
550 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_of_get_max_clock() local
552 if (esdhc->peripheral_clock) in esdhc_of_get_max_clock()
553 return esdhc->peripheral_clock; in esdhc_of_get_max_clock()
561 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_of_get_min_clock() local
564 if (esdhc->peripheral_clock) in esdhc_of_get_min_clock()
565 clock = esdhc->peripheral_clock; in esdhc_of_get_min_clock()
574 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_clock_enable() local
581 * IPGEN/HCKEN/PEREN bits exist on eSDHC whose vendor version in esdhc_clock_enable()
584 if (esdhc->vendor_ver <= VENDOR_V_22) in esdhc_clock_enable()
602 while (esdhc->vendor_ver > VENDOR_V_22) { in esdhc_clock_enable()
645 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_of_set_clock() local
658 if (esdhc->vendor_ver < VENDOR_V_23) in esdhc_of_set_clock()
663 esdhc->clk_fixup && host->mmc->ios.timing == MMC_TIMING_LEGACY) in esdhc_of_set_clock()
664 clock_fixup = esdhc->clk_fixup->sd_dflt_max_clk; in esdhc_of_set_clock()
665 else if (esdhc->clk_fixup) in esdhc_of_set_clock()
666 clock_fixup = esdhc->clk_fixup->max_clk[host->mmc->ios.timing]; in esdhc_of_set_clock()
678 esdhc->div_ratio = pre_div * div; in esdhc_of_set_clock()
681 if (esdhc->quirk_limited_clk_division && in esdhc_of_set_clock()
685 if (esdhc->div_ratio <= 4) { in esdhc_of_set_clock()
688 } else if (esdhc->div_ratio <= 8) { in esdhc_of_set_clock()
691 } else if (esdhc->div_ratio <= 12) { in esdhc_of_set_clock()
698 esdhc->div_ratio = pre_div * div; in esdhc_of_set_clock()
701 host->mmc->actual_clock = host->max_clk / esdhc->div_ratio; in esdhc_of_set_clock()
723 while (esdhc->vendor_ver > VENDOR_V_22) { in esdhc_of_set_clock()
799 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_reset() local
806 if (esdhc->quirk_delay_before_data_reset && in esdhc_reset()
812 * Save bus-width for eSDHC whose vendor version is 2.2 in esdhc_reset()
816 (esdhc->vendor_ver <= VENDOR_V_22)) { in esdhc_reset()
824 * Restore bus-width setting and interrupt registers for eSDHC in esdhc_reset()
828 (esdhc->vendor_ver <= VENDOR_V_22)) { in esdhc_reset()
839 * Some bits have to be cleaned manually for eSDHC whose spec in esdhc_reset()
843 (esdhc->spec_ver >= SDHCI_SPEC_300)) { in esdhc_reset()
852 if (esdhc->quirk_unreliable_pulse_detection) { in esdhc_reset()
997 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_prepare_sw_tuning() local
1000 if (esdhc->quirk_tuning_erratum_type1) { in esdhc_prepare_sw_tuning()
1001 *window_start = 5 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1002 *window_end = 3 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1019 if (abs(start_ptr - end_ptr) > (4 * esdhc->div_ratio + 2)) { in esdhc_prepare_sw_tuning()
1020 *window_start = 8 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1021 *window_end = 4 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1023 *window_start = 5 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1024 *window_end = 3 * esdhc->div_ratio; in esdhc_prepare_sw_tuning()
1033 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_execute_sw_tuning() local
1049 esdhc->in_sw_tuning = true; in esdhc_execute_sw_tuning()
1051 esdhc->in_sw_tuning = false; in esdhc_execute_sw_tuning()
1059 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_execute_tuning() local
1069 clk = esdhc->peripheral_clock / 3; in esdhc_execute_tuning()
1076 * The eSDHC controller takes the data timeout value into account in esdhc_execute_tuning()
1089 if (esdhc->quirk_limited_clk_division && in esdhc_execute_tuning()
1104 * tuning may succeed although eSDHC might not have in esdhc_execute_tuning()
1107 if (esdhc->quirk_tuning_erratum_type2 && in esdhc_execute_tuning()
1112 (4 * esdhc->div_ratio + 2)) in esdhc_execute_tuning()
1121 (esdhc->quirk_tuning_erratum_type1 || in esdhc_execute_tuning()
1122 esdhc->quirk_tuning_erratum_type2)) { in esdhc_execute_tuning()
1144 clk = host->max_clk / (esdhc->div_ratio + 1); in esdhc_execute_tuning()
1213 struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_irq() local
1216 if (esdhc->quirk_trans_complete_erratum) { in esdhc_irq()
1339 struct sdhci_esdhc *esdhc; in esdhc_init() local
1346 esdhc = sdhci_pltfm_priv(pltfm_host); in esdhc_init()
1349 esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> in esdhc_init()
1351 esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; in esdhc_init()
1353 esdhc->quirk_incorrect_hostver = true; in esdhc_init()
1355 esdhc->quirk_incorrect_hostver = false; in esdhc_init()
1358 esdhc->quirk_limited_clk_division = true; in esdhc_init()
1360 esdhc->quirk_limited_clk_division = false; in esdhc_init()
1363 esdhc->quirk_unreliable_pulse_detection = true; in esdhc_init()
1365 esdhc->quirk_unreliable_pulse_detection = false; in esdhc_init()
1369 esdhc->clk_fixup = match->data; in esdhc_init()
1372 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { in esdhc_init()
1373 esdhc->quirk_delay_before_data_reset = true; in esdhc_init()
1374 esdhc->quirk_trans_complete_erratum = true; in esdhc_init()
1380 * esdhc->peripheral_clock would be assigned with a value in esdhc_init()
1381 * which is eSDHC base clock when use periperal clock. in esdhc_init()
1383 * API is peripheral clock while the eSDHC base clock is in esdhc_init()
1386 if (of_device_is_compatible(np, "fsl,ls1046a-esdhc") || in esdhc_init()
1387 of_device_is_compatible(np, "fsl,ls1028a-esdhc") || in esdhc_init()
1388 of_device_is_compatible(np, "fsl,ls1088a-esdhc")) in esdhc_init()
1389 esdhc->peripheral_clock = clk_get_rate(clk) / 2; in esdhc_init()
1391 esdhc->peripheral_clock = clk_get_rate(clk); in esdhc_init()
1403 if (esdhc->peripheral_clock) in esdhc_init()
1422 struct sdhci_esdhc *esdhc; in sdhci_esdhc_probe() local
1448 esdhc = sdhci_pltfm_priv(pltfm_host); in sdhci_esdhc_probe()
1450 esdhc->quirk_tuning_erratum_type1 = true; in sdhci_esdhc_probe()
1452 esdhc->quirk_tuning_erratum_type1 = false; in sdhci_esdhc_probe()
1455 esdhc->quirk_tuning_erratum_type2 = true; in sdhci_esdhc_probe()
1457 esdhc->quirk_tuning_erratum_type2 = false; in sdhci_esdhc_probe()
1459 if (esdhc->vendor_ver == VENDOR_V_22) in sdhci_esdhc_probe()
1462 if (esdhc->vendor_ver > VENDOR_V_22) in sdhci_esdhc_probe()
1465 if (of_find_compatible_node(NULL, NULL, "fsl,p2020-esdhc")) { in sdhci_esdhc_probe()
1470 if (of_device_is_compatible(np, "fsl,p5040-esdhc") || in sdhci_esdhc_probe()
1471 of_device_is_compatible(np, "fsl,p5020-esdhc") || in sdhci_esdhc_probe()
1472 of_device_is_compatible(np, "fsl,p4080-esdhc") || in sdhci_esdhc_probe()
1473 of_device_is_compatible(np, "fsl,p1020-esdhc") || in sdhci_esdhc_probe()
1474 of_device_is_compatible(np, "fsl,t1040-esdhc")) in sdhci_esdhc_probe()
1477 if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) in sdhci_esdhc_probe()
1480 esdhc->quirk_ignore_data_inhibit = false; in sdhci_esdhc_probe()
1481 if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { in sdhci_esdhc_probe()
1487 esdhc->quirk_ignore_data_inhibit = true; in sdhci_esdhc_probe()
1509 .name = "sdhci-esdhc",
1520 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");