Lines Matching +full:timeout +full:- +full:tap +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/dma-mapping.h>
23 #include <linux/mmc/slot-gpio.h>
27 #include "sdhci-cqhci.h"
28 #include "sdhci-pltfm.h"
115 * NVQUIRK_HAS_TMCLK is for SoC's having separate timeout clock for Tegra
116 * SDMMC hardware data timeout.
181 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_readw()
183 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) && in tegra_sdhci_readw()
189 return readw(host->ioaddr + reg); in tegra_sdhci_readw()
202 pltfm_host->xfer_mode_shadow = val; in tegra_sdhci_writew()
205 writel((val << 16) | pltfm_host->xfer_mode_shadow, in tegra_sdhci_writew()
206 host->ioaddr + SDHCI_TRANSFER_MODE); in tegra_sdhci_writew()
210 writew(val, host->ioaddr + reg); in tegra_sdhci_writew()
217 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_writel()
219 /* Seems like we're getting spurious timeout and crc errors, so in tegra_sdhci_writel()
226 writel(val, host->ioaddr + reg); in tegra_sdhci_writel()
228 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) && in tegra_sdhci_writel()
231 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); in tegra_sdhci_writel()
236 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL); in tegra_sdhci_writel()
276 writew(val, host->ioaddr + reg); in tegra210_sdhci_writew()
288 * Write-enable shall be assumed if GPIO is missing in a board's in tegra_sdhci_get_ro()
289 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on in tegra_sdhci_get_ro()
292 return mmc_gpio_get_ro(host->mmc); in tegra_sdhci_get_ro()
309 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_is_pad_and_regulator_valid()
312 if (IS_ERR(host->mmc->supply.vqmmc)) in tegra_sdhci_is_pad_and_regulator_valid()
315 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, in tegra_sdhci_is_pad_and_regulator_valid()
318 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc, in tegra_sdhci_is_pad_and_regulator_valid()
322 return tegra_host->pad_control_available; in tegra_sdhci_is_pad_and_regulator_valid()
328 static void tegra_sdhci_set_tap(struct sdhci_host *host, unsigned int tap) in tegra_sdhci_set_tap() argument
332 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_set_tap()
337 * Touching the tap values is a bit tricky on some SoC generations. in tegra_sdhci_set_tap()
339 * the tap values are changed. in tegra_sdhci_set_tap()
342 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP) in tegra_sdhci_set_tap()
347 reg |= tap << SDHCI_CLOCK_CTRL_TAP_SHIFT; in tegra_sdhci_set_tap()
350 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP && in tegra_sdhci_set_tap()
362 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_reset()
370 tegra_sdhci_set_tap(host, tegra_host->default_tap); in tegra_sdhci_reset()
385 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300) in tegra_sdhci_reset()
388 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) in tegra_sdhci_reset()
390 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) in tegra_sdhci_reset()
392 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104) in tegra_sdhci_reset()
394 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50) in tegra_sdhci_reset()
398 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT; in tegra_sdhci_reset()
403 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) { in tegra_sdhci_reset()
409 tegra_host->pad_calib_required = true; in tegra_sdhci_reset()
412 tegra_host->ddr_signaling = false; in tegra_sdhci_reset()
453 &tegra_host->autocal_offsets; in tegra_sdhci_set_padctrl()
462 if (tegra_host->pinctrl_state_1v8_drv) { in tegra_sdhci_set_padctrl()
464 tegra_host->pinctrl_state_1v8_drv; in tegra_sdhci_set_padctrl()
466 drvup = offsets->pull_up_1v8_timeout; in tegra_sdhci_set_padctrl()
467 drvdn = offsets->pull_down_1v8_timeout; in tegra_sdhci_set_padctrl()
470 if (tegra_host->pinctrl_state_3v3_drv) { in tegra_sdhci_set_padctrl()
472 tegra_host->pinctrl_state_3v3_drv; in tegra_sdhci_set_padctrl()
474 drvup = offsets->pull_up_3v3_timeout; in tegra_sdhci_set_padctrl()
475 drvdn = offsets->pull_down_3v3_timeout; in tegra_sdhci_set_padctrl()
480 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
483 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
496 if (!tegra_host->pad_control_available) in tegra_sdhci_set_padctrl()
500 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
501 tegra_host->pinctrl_state_1v8); in tegra_sdhci_set_padctrl()
503 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
506 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc, in tegra_sdhci_set_padctrl()
507 tegra_host->pinctrl_state_3v3); in tegra_sdhci_set_padctrl()
509 dev_err(mmc_dev(host->mmc), in tegra_sdhci_set_padctrl()
522 tegra_host->autocal_offsets; in tegra_sdhci_pad_autocalib()
523 struct mmc_ios *ios = &host->mmc->ios; in tegra_sdhci_pad_autocalib()
529 switch (ios->timing) { in tegra_sdhci_pad_autocalib()
537 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in tegra_sdhci_pad_autocalib()
543 /* Set initial offset before auto-calibration */ in tegra_sdhci_pad_autocalib()
555 /* 10 ms timeout */ in tegra_sdhci_pad_autocalib()
556 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS, in tegra_sdhci_pad_autocalib()
565 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); in tegra_sdhci_pad_autocalib()
572 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false); in tegra_sdhci_pad_autocalib()
574 dev_err(mmc_dev(host->mmc), in tegra_sdhci_pad_autocalib()
584 &tegra_host->autocal_offsets; in tegra_sdhci_parse_pad_autocal_dt()
587 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
588 "nvidia,pad-autocal-pull-up-offset-3v3", in tegra_sdhci_parse_pad_autocal_dt()
589 &autocal->pull_up_3v3); in tegra_sdhci_parse_pad_autocal_dt()
591 autocal->pull_up_3v3 = 0; in tegra_sdhci_parse_pad_autocal_dt()
593 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
594 "nvidia,pad-autocal-pull-down-offset-3v3", in tegra_sdhci_parse_pad_autocal_dt()
595 &autocal->pull_down_3v3); in tegra_sdhci_parse_pad_autocal_dt()
597 autocal->pull_down_3v3 = 0; in tegra_sdhci_parse_pad_autocal_dt()
599 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
600 "nvidia,pad-autocal-pull-up-offset-1v8", in tegra_sdhci_parse_pad_autocal_dt()
601 &autocal->pull_up_1v8); in tegra_sdhci_parse_pad_autocal_dt()
603 autocal->pull_up_1v8 = 0; in tegra_sdhci_parse_pad_autocal_dt()
605 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
606 "nvidia,pad-autocal-pull-down-offset-1v8", in tegra_sdhci_parse_pad_autocal_dt()
607 &autocal->pull_down_1v8); in tegra_sdhci_parse_pad_autocal_dt()
609 autocal->pull_down_1v8 = 0; in tegra_sdhci_parse_pad_autocal_dt()
611 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
612 "nvidia,pad-autocal-pull-up-offset-sdr104", in tegra_sdhci_parse_pad_autocal_dt()
613 &autocal->pull_up_sdr104); in tegra_sdhci_parse_pad_autocal_dt()
615 autocal->pull_up_sdr104 = autocal->pull_up_1v8; in tegra_sdhci_parse_pad_autocal_dt()
617 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
618 "nvidia,pad-autocal-pull-down-offset-sdr104", in tegra_sdhci_parse_pad_autocal_dt()
619 &autocal->pull_down_sdr104); in tegra_sdhci_parse_pad_autocal_dt()
621 autocal->pull_down_sdr104 = autocal->pull_down_1v8; in tegra_sdhci_parse_pad_autocal_dt()
623 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
624 "nvidia,pad-autocal-pull-up-offset-hs400", in tegra_sdhci_parse_pad_autocal_dt()
625 &autocal->pull_up_hs400); in tegra_sdhci_parse_pad_autocal_dt()
627 autocal->pull_up_hs400 = autocal->pull_up_1v8; in tegra_sdhci_parse_pad_autocal_dt()
629 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
630 "nvidia,pad-autocal-pull-down-offset-hs400", in tegra_sdhci_parse_pad_autocal_dt()
631 &autocal->pull_down_hs400); in tegra_sdhci_parse_pad_autocal_dt()
633 autocal->pull_down_hs400 = autocal->pull_down_1v8; in tegra_sdhci_parse_pad_autocal_dt()
636 * Different fail-safe drive strength values based on the signaling in tegra_sdhci_parse_pad_autocal_dt()
641 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL)) in tegra_sdhci_parse_pad_autocal_dt()
644 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
645 "nvidia,pad-autocal-pull-up-offset-3v3-timeout", in tegra_sdhci_parse_pad_autocal_dt()
646 &autocal->pull_up_3v3_timeout); in tegra_sdhci_parse_pad_autocal_dt()
648 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && in tegra_sdhci_parse_pad_autocal_dt()
649 (tegra_host->pinctrl_state_3v3_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
650 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
651 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
652 autocal->pull_up_3v3_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
655 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
656 "nvidia,pad-autocal-pull-down-offset-3v3-timeout", in tegra_sdhci_parse_pad_autocal_dt()
657 &autocal->pull_down_3v3_timeout); in tegra_sdhci_parse_pad_autocal_dt()
659 if (!IS_ERR(tegra_host->pinctrl_state_3v3) && in tegra_sdhci_parse_pad_autocal_dt()
660 (tegra_host->pinctrl_state_3v3_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
661 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
662 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
663 autocal->pull_down_3v3_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
666 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
667 "nvidia,pad-autocal-pull-up-offset-1v8-timeout", in tegra_sdhci_parse_pad_autocal_dt()
668 &autocal->pull_up_1v8_timeout); in tegra_sdhci_parse_pad_autocal_dt()
670 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && in tegra_sdhci_parse_pad_autocal_dt()
671 (tegra_host->pinctrl_state_1v8_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
672 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
673 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
674 autocal->pull_up_1v8_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
677 err = device_property_read_u32(host->mmc->parent, in tegra_sdhci_parse_pad_autocal_dt()
678 "nvidia,pad-autocal-pull-down-offset-1v8-timeout", in tegra_sdhci_parse_pad_autocal_dt()
679 &autocal->pull_down_1v8_timeout); in tegra_sdhci_parse_pad_autocal_dt()
681 if (!IS_ERR(tegra_host->pinctrl_state_1v8) && in tegra_sdhci_parse_pad_autocal_dt()
682 (tegra_host->pinctrl_state_1v8_drv == NULL)) in tegra_sdhci_parse_pad_autocal_dt()
683 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n", in tegra_sdhci_parse_pad_autocal_dt()
684 mmc_hostname(host->mmc)); in tegra_sdhci_parse_pad_autocal_dt()
685 autocal->pull_down_1v8_timeout = 0; in tegra_sdhci_parse_pad_autocal_dt()
694 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib); in tegra_sdhci_request()
696 /* 100 ms calibration interval is specified in the TRM */ in tegra_sdhci_request()
699 tegra_host->last_calib = ktime_get(); in tegra_sdhci_request()
711 err = device_property_read_u32(host->mmc->parent, "nvidia,default-tap", in tegra_sdhci_parse_tap_and_trim()
712 &tegra_host->default_tap); in tegra_sdhci_parse_tap_and_trim()
714 tegra_host->default_tap = 0; in tegra_sdhci_parse_tap_and_trim()
716 err = device_property_read_u32(host->mmc->parent, "nvidia,default-trim", in tegra_sdhci_parse_tap_and_trim()
717 &tegra_host->default_trim); in tegra_sdhci_parse_tap_and_trim()
719 tegra_host->default_trim = 0; in tegra_sdhci_parse_tap_and_trim()
721 err = device_property_read_u32(host->mmc->parent, "nvidia,dqs-trim", in tegra_sdhci_parse_tap_and_trim()
722 &tegra_host->dqs_trim); in tegra_sdhci_parse_tap_and_trim()
724 tegra_host->dqs_trim = 0x11; in tegra_sdhci_parse_tap_and_trim()
732 if (device_property_read_bool(host->mmc->parent, "supports-cqe")) in tegra_sdhci_parse_dt()
733 tegra_host->enable_hwcq = true; in tegra_sdhci_parse_dt()
735 tegra_host->enable_hwcq = false; in tegra_sdhci_parse_dt()
754 * sdhci_calc_clk(). The divider is calculated from host->max_clk and in tegra_sdhci_set_clock()
757 * By setting the host->max_clk to clock * 2 the divider calculation in tegra_sdhci_set_clock()
762 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; in tegra_sdhci_set_clock()
763 clk_set_rate(pltfm_host->clk, host_clk); in tegra_sdhci_set_clock()
764 tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk); in tegra_sdhci_set_clock()
765 if (tegra_host->ddr_signaling) in tegra_sdhci_set_clock()
766 host->max_clk = host_clk; in tegra_sdhci_set_clock()
768 host->max_clk = clk_get_rate(pltfm_host->clk); in tegra_sdhci_set_clock()
772 if (tegra_host->pad_calib_required) { in tegra_sdhci_set_clock()
774 tegra_host->pad_calib_required = false; in tegra_sdhci_set_clock()
786 if (ios->enhanced_strobe) { in tegra_sdhci_hs400_enhanced_strobe()
808 return clk_round_rate(pltfm_host->clk, UINT_MAX); in tegra_sdhci_get_max_clock()
830 /* 1 ms sleep, 5 ms timeout */ in tegra_sdhci_hs400_dll_cal()
831 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA, in tegra_sdhci_hs400_dll_cal()
835 dev_err(mmc_dev(host->mmc), in tegra_sdhci_hs400_dll_cal()
845 u8 word, bit, edge1, tap, window; in tegra_sdhci_tap_correction() local
856 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE; in tegra_sdhci_tap_correction()
859 * Read auto-tuned results and extract good valid passing window by in tegra_sdhci_tap_correction()
860 * filtering out un-wanted bubble/partial/merged windows. in tegra_sdhci_tap_correction()
870 tap = word * TUNING_WORD_BIT_SIZE + bit; in tegra_sdhci_tap_correction()
875 first_fail_tap = tap; in tegra_sdhci_tap_correction()
880 start_pass_tap = tap; in tegra_sdhci_tap_correction()
883 first_pass_tap = tap; in tegra_sdhci_tap_correction()
889 end_pass_tap = tap - 1; in tegra_sdhci_tap_correction()
893 window = end_pass_tap - start_pass_tap; in tegra_sdhci_tap_correction()
896 start_pass_tap = tap; in tegra_sdhci_tap_correction()
899 /* set tap at middle of valid window */ in tegra_sdhci_tap_correction()
900 tap = start_pass_tap + window / 2; in tegra_sdhci_tap_correction()
901 tegra_host->tuned_tap_delay = tap; in tegra_sdhci_tap_correction()
913 /* set tap location at fixed tap relative to the first edge */ in tegra_sdhci_tap_correction()
914 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2; in tegra_sdhci_tap_correction()
915 if (edge1 - 1 > fixed_tap) in tegra_sdhci_tap_correction()
916 tegra_host->tuned_tap_delay = edge1 - fixed_tap; in tegra_sdhci_tap_correction()
918 tegra_host->tuned_tap_delay = edge1 + fixed_tap; in tegra_sdhci_tap_correction()
926 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_post_tuning()
933 /* retain HW tuned tap to use incase if no correction is needed */ in tegra_sdhci_post_tuning()
935 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >> in tegra_sdhci_post_tuning()
937 if (soc_data->min_tap_delay && soc_data->max_tap_delay) { in tegra_sdhci_post_tuning()
938 min_tap_dly = soc_data->min_tap_delay; in tegra_sdhci_post_tuning()
939 max_tap_dly = soc_data->max_tap_delay; in tegra_sdhci_post_tuning()
940 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC; in tegra_sdhci_post_tuning()
951 * fixed tap is used when HW tuning result contains single edge in tegra_sdhci_post_tuning()
952 * and tap is set at fixed tap delay relative to the first edge in tegra_sdhci_post_tuning()
961 window_width = end_tap - start_tap; in tegra_sdhci_post_tuning()
962 num_iter = host->tuning_loop_count; in tegra_sdhci_post_tuning()
968 if (start_tap == 0 || (end_tap == (num_iter - 1)) || in tegra_sdhci_post_tuning()
969 (end_tap == num_iter - 2) || window_width >= thdupper) { in tegra_sdhci_post_tuning()
971 mmc_hostname(host->mmc)); in tegra_sdhci_post_tuning()
977 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); in tegra_sdhci_post_tuning()
986 if (!err && !host->tuning_err) in tegra_sdhci_execute_hw_tuning()
1003 tegra_host->ddr_signaling = false; in tegra_sdhci_set_uhs_signaling()
1009 /* Don't set default tap on tunable modes. */ in tegra_sdhci_set_uhs_signaling()
1019 tegra_host->ddr_signaling = true; in tegra_sdhci_set_uhs_signaling()
1037 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256; in tegra_sdhci_set_uhs_signaling()
1043 if (tegra_host->tuned_tap_delay && !set_default_tap) in tegra_sdhci_set_uhs_signaling()
1044 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay); in tegra_sdhci_set_uhs_signaling()
1046 tegra_sdhci_set_tap(host, tegra_host->default_tap); in tegra_sdhci_set_uhs_signaling()
1049 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); in tegra_sdhci_set_uhs_signaling()
1060 * Start search for minimum tap value at 10, as smaller values are in tegra_sdhci_execute_tuning()
1067 if (!mmc_send_tuning(host->mmc, opcode, NULL)) in tegra_sdhci_execute_tuning()
1072 /* Find the maximum tap value that still passes. */ in tegra_sdhci_execute_tuning()
1076 if (mmc_send_tuning(host->mmc, opcode, NULL)) { in tegra_sdhci_execute_tuning()
1077 max--; in tegra_sdhci_execute_tuning()
1083 /* The TRM states the ideal tap value is at 75% in the passing range. */ in tegra_sdhci_execute_tuning()
1084 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4)); in tegra_sdhci_execute_tuning()
1086 return mmc_send_tuning(host->mmc, opcode, NULL); in tegra_sdhci_execute_tuning()
1097 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { in sdhci_tegra_start_signal_voltage_switch()
1098 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); in sdhci_tegra_start_signal_voltage_switch()
1102 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) { in sdhci_tegra_start_signal_voltage_switch()
1106 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true); in sdhci_tegra_start_signal_voltage_switch()
1109 if (tegra_host->pad_calib_required) in sdhci_tegra_start_signal_voltage_switch()
1118 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev); in tegra_sdhci_init_pinctrl_info()
1119 if (IS_ERR(tegra_host->pinctrl_sdmmc)) { in tegra_sdhci_init_pinctrl_info()
1121 PTR_ERR(tegra_host->pinctrl_sdmmc)); in tegra_sdhci_init_pinctrl_info()
1122 return -1; in tegra_sdhci_init_pinctrl_info()
1125 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state( in tegra_sdhci_init_pinctrl_info()
1126 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv"); in tegra_sdhci_init_pinctrl_info()
1127 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) { in tegra_sdhci_init_pinctrl_info()
1128 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV) in tegra_sdhci_init_pinctrl_info()
1129 tegra_host->pinctrl_state_1v8_drv = NULL; in tegra_sdhci_init_pinctrl_info()
1132 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state( in tegra_sdhci_init_pinctrl_info()
1133 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv"); in tegra_sdhci_init_pinctrl_info()
1134 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) { in tegra_sdhci_init_pinctrl_info()
1135 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV) in tegra_sdhci_init_pinctrl_info()
1136 tegra_host->pinctrl_state_3v3_drv = NULL; in tegra_sdhci_init_pinctrl_info()
1139 tegra_host->pinctrl_state_3v3 = in tegra_sdhci_init_pinctrl_info()
1140 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3"); in tegra_sdhci_init_pinctrl_info()
1141 if (IS_ERR(tegra_host->pinctrl_state_3v3)) { in tegra_sdhci_init_pinctrl_info()
1143 PTR_ERR(tegra_host->pinctrl_state_3v3)); in tegra_sdhci_init_pinctrl_info()
1144 return -1; in tegra_sdhci_init_pinctrl_info()
1147 tegra_host->pinctrl_state_1v8 = in tegra_sdhci_init_pinctrl_info()
1148 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8"); in tegra_sdhci_init_pinctrl_info()
1149 if (IS_ERR(tegra_host->pinctrl_state_1v8)) { in tegra_sdhci_init_pinctrl_info()
1151 PTR_ERR(tegra_host->pinctrl_state_1v8)); in tegra_sdhci_init_pinctrl_info()
1152 return -1; in tegra_sdhci_init_pinctrl_info()
1155 tegra_host->pad_control_available = true; in tegra_sdhci_init_pinctrl_info()
1164 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in tegra_sdhci_voltage_switch()
1166 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) in tegra_sdhci_voltage_switch()
1167 tegra_host->pad_calib_required = true; in tegra_sdhci_voltage_switch()
1172 struct mmc_host *mmc = cq_host->mmc; in tegra_cqhci_writel()
1175 ktime_t timeout; in tegra_cqhci_writel() local
1181 * to be re-configured. in tegra_cqhci_writel()
1190 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1191 timeout = ktime_add_us(ktime_get(), 50); in tegra_cqhci_writel()
1193 timed_out = ktime_compare(ktime_get(), timeout) > 0; in tegra_cqhci_writel()
1203 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1205 writel(val, cq_host->mmio + reg); in tegra_cqhci_writel()
1214 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data; in sdhci_tegra_update_dcmd_desc()
1216 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING && in sdhci_tegra_update_dcmd_desc()
1217 mrq->cmd->flags & MMC_RSP_R1B) in sdhci_tegra_update_dcmd_desc()
1223 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_enable()
1233 if (!cq_host->activated) { in sdhci_tegra_cqe_enable()
1269 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_tegra_cqhci_irq()
1280 * HW busy detection timeout is based on programmed data timeout in tegra_sdhci_set_timeout()
1281 * counter and maximum supported timeout is 11s which may not be in tegra_sdhci_set_timeout()
1286 * without HW timeout. in tegra_sdhci_set_timeout()
1289 * more than maximum HW busy timeout of 11s otherwise use finite in tegra_sdhci_set_timeout()
1293 if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC) in tegra_sdhci_set_timeout()
1304 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_pre_enable()
1314 struct cqhci_host *cq_host = mmc->cqe_private; in sdhci_tegra_cqe_post_disable()
1338 const struct sdhci_tegra_soc_data *soc = tegra->soc_data; in tegra_sdhci_set_dma_mask()
1339 struct device *dev = mmc_dev(host->mmc); in tegra_sdhci_set_dma_mask()
1341 if (soc->dma_mask) in tegra_sdhci_set_dma_mask()
1342 return dma_set_mask_and_coherent(dev, soc->dma_mask); in tegra_sdhci_set_dma_mask()
1387 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1544 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1545 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1546 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1547 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1548 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1549 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1550 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1563 if (!tegra_host->enable_hwcq) in sdhci_tegra_add_host()
1572 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in sdhci_tegra_add_host()
1574 cq_host = devm_kzalloc(host->mmc->parent, in sdhci_tegra_add_host()
1577 ret = -ENOMEM; in sdhci_tegra_add_host()
1581 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR; in sdhci_tegra_add_host()
1582 cq_host->ops = &sdhci_tegra_cqhci_ops; in sdhci_tegra_add_host()
1584 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_tegra_add_host()
1586 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_tegra_add_host()
1588 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_tegra_add_host()
1613 match = of_match_device(sdhci_tegra_dt_match, &pdev->dev); in sdhci_tegra_probe()
1615 return -EINVAL; in sdhci_tegra_probe()
1616 soc_data = match->data; in sdhci_tegra_probe()
1618 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host)); in sdhci_tegra_probe()
1624 tegra_host->ddr_signaling = false; in sdhci_tegra_probe()
1625 tegra_host->pad_calib_required = false; in sdhci_tegra_probe()
1626 tegra_host->pad_control_available = false; in sdhci_tegra_probe()
1627 tegra_host->soc_data = soc_data; in sdhci_tegra_probe()
1629 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) { in sdhci_tegra_probe()
1630 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host); in sdhci_tegra_probe()
1632 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_tegra_probe()
1637 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) in sdhci_tegra_probe()
1638 host->mmc_host_ops.request = tegra_sdhci_request; in sdhci_tegra_probe()
1640 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_tegra_probe()
1643 if (!host->ops->platform_execute_tuning) in sdhci_tegra_probe()
1644 host->mmc_host_ops.execute_tuning = in sdhci_tegra_probe()
1647 rc = mmc_of_parse(host->mmc); in sdhci_tegra_probe()
1651 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) in sdhci_tegra_probe()
1652 host->mmc->caps |= MMC_CAP_1_8V_DDR; in sdhci_tegra_probe()
1655 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY; in sdhci_tegra_probe()
1659 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", in sdhci_tegra_probe()
1661 if (IS_ERR(tegra_host->power_gpio)) { in sdhci_tegra_probe()
1662 rc = PTR_ERR(tegra_host->power_gpio); in sdhci_tegra_probe()
1668 * timeout clock and SW can choose TMCLK or SDCLK for hardware in sdhci_tegra_probe()
1669 * data timeout through the bit USE_TMCLK_FOR_DATA_TIMEOUT of in sdhci_tegra_probe()
1674 * With TMCLK of 12Mhz provides maximum data timeout period that can in sdhci_tegra_probe()
1675 * be achieved is 11s better than using SDCLK for data timeout. in sdhci_tegra_probe()
1681 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) { in sdhci_tegra_probe()
1682 clk = devm_clk_get(&pdev->dev, "tmclk"); in sdhci_tegra_probe()
1685 if (rc == -EPROBE_DEFER) in sdhci_tegra_probe()
1688 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc); in sdhci_tegra_probe()
1695 dev_err(&pdev->dev, in sdhci_tegra_probe()
1700 tegra_host->tmclk = clk; in sdhci_tegra_probe()
1703 clk = devm_clk_get(mmc_dev(host->mmc), NULL); in sdhci_tegra_probe()
1705 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk), in sdhci_tegra_probe()
1710 pltfm_host->clk = clk; in sdhci_tegra_probe()
1712 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev, in sdhci_tegra_probe()
1714 if (IS_ERR(tegra_host->rst)) { in sdhci_tegra_probe()
1715 rc = PTR_ERR(tegra_host->rst); in sdhci_tegra_probe()
1716 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc); in sdhci_tegra_probe()
1720 rc = reset_control_assert(tegra_host->rst); in sdhci_tegra_probe()
1726 rc = reset_control_deassert(tegra_host->rst); in sdhci_tegra_probe()
1739 reset_control_assert(tegra_host->rst); in sdhci_tegra_probe()
1741 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_probe()
1743 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_probe()
1758 reset_control_assert(tegra_host->rst); in sdhci_tegra_remove()
1760 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_remove()
1761 clk_disable_unprepare(tegra_host->tmclk); in sdhci_tegra_remove()
1775 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_tegra_suspend()
1776 ret = cqhci_suspend(host->mmc); in sdhci_tegra_suspend()
1783 cqhci_resume(host->mmc); in sdhci_tegra_suspend()
1787 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_suspend()
1797 ret = clk_prepare_enable(pltfm_host->clk); in sdhci_tegra_resume()
1805 if (host->mmc->caps2 & MMC_CAP2_CQE) { in sdhci_tegra_resume()
1806 ret = cqhci_resume(host->mmc); in sdhci_tegra_resume()
1816 clk_disable_unprepare(pltfm_host->clk); in sdhci_tegra_resume()
1826 .name = "sdhci-tegra",