Lines Matching +full:nand +full:- +full:rb
1 // SPDX-License-Identifier: GPL-2.0
3 * Arasan NAND Flash Controller Driver
5 * Copyright (C) 2014 - 2020 Xilinx, Inc.
17 #include <linux/dma-mapping.h>
103 #define ANFC_MAX_PKT_SIZE (SZ_2K - 1)
111 * struct anfc_op - Defines how to execute an operation
136 * struct anand - Defines the NAND chip related information
137 * @node: Used to store NAND chips into a list
138 * @chip: NAND chip information structure
140 * @rb: Ready-busy line
158 unsigned int rb; member
174 * struct arasan_nfc - Defines the Arasan NAND flash controller driver instance
180 * @chips: List of all NAND chips attached to the controller
195 static struct anand *to_anand(struct nand_chip *nand) in to_anand() argument
197 return container_of(nand, struct anand, chip); in to_anand()
210 ret = readl_relaxed_poll_timeout(nfc->base + INTR_STS_REG, val, in anfc_wait_for_event()
214 dev_err(nfc->dev, "Timeout waiting for event 0x%x\n", event); in anfc_wait_for_event()
215 return -ETIMEDOUT; in anfc_wait_for_event()
218 writel_relaxed(event, nfc->base + INTR_STS_REG); in anfc_wait_for_event()
231 ret = readl_relaxed_poll_timeout(nfc->base + READY_STS_REG, val, in anfc_wait_for_rb()
232 val & BIT(anand->rb), in anfc_wait_for_rb()
235 dev_err(nfc->dev, "Timeout waiting for R/B 0x%x\n", in anfc_wait_for_rb()
236 readl_relaxed(nfc->base + READY_STS_REG)); in anfc_wait_for_rb()
237 return -ETIMEDOUT; in anfc_wait_for_rb()
245 writel_relaxed(nfc_op->pkt_reg, nfc->base + PKT_REG); in anfc_trigger_op()
246 writel_relaxed(nfc_op->addr1_reg, nfc->base + MEM_ADDR1_REG); in anfc_trigger_op()
247 writel_relaxed(nfc_op->addr2_reg, nfc->base + MEM_ADDR2_REG); in anfc_trigger_op()
248 writel_relaxed(nfc_op->cmd_reg, nfc->base + CMD_REG); in anfc_trigger_op()
249 writel_relaxed(nfc_op->prog_reg, nfc->base + PROG_REG); in anfc_trigger_op()
264 return -ENOTSUPP; in anfc_pkt_len_config()
278 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_select_target()
282 writel_relaxed(anand->timings, nfc->base + DATA_INTERFACE_REG); in anfc_select_target()
285 if (nfc->cur_clk != anand->clk) { in anfc_select_target()
286 clk_disable_unprepare(nfc->bus_clk); in anfc_select_target()
287 ret = clk_set_rate(nfc->bus_clk, anand->clk); in anfc_select_target()
289 dev_err(nfc->dev, "Failed to change clock rate\n"); in anfc_select_target()
293 ret = clk_prepare_enable(nfc->bus_clk); in anfc_select_target()
295 dev_err(nfc->dev, in anfc_select_target()
296 "Failed to re-enable the bus clock\n"); in anfc_select_target()
300 nfc->cur_clk = anand->clk; in anfc_select_target()
331 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_read_page_hw_ecc()
334 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0); in anfc_read_page_hw_ecc()
340 PKT_SIZE(chip->ecc.size) | in anfc_read_page_hw_ecc()
341 PKT_STEPS(chip->ecc.steps), in anfc_read_page_hw_ecc()
343 (page & 0xFF) << (8 * (anand->caddr_cycles)) | in anfc_read_page_hw_ecc()
344 (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))), in anfc_read_page_hw_ecc()
347 ADDR2_STRENGTH(anand->strength) | in anfc_read_page_hw_ecc()
348 ADDR2_CS(anand->cs), in anfc_read_page_hw_ecc()
352 CMD_PAGE_SIZE(anand->page_sz) | in anfc_read_page_hw_ecc()
354 CMD_NADDRS(anand->caddr_cycles + in anfc_read_page_hw_ecc()
355 anand->raddr_cycles), in anfc_read_page_hw_ecc()
359 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_FROM_DEVICE); in anfc_read_page_hw_ecc()
360 if (dma_mapping_error(nfc->dev, dma_addr)) { in anfc_read_page_hw_ecc()
361 dev_err(nfc->dev, "Buffer mapping error"); in anfc_read_page_hw_ecc()
362 return -EIO; in anfc_read_page_hw_ecc()
365 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG); in anfc_read_page_hw_ecc()
366 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG); in anfc_read_page_hw_ecc()
371 dma_unmap_single(nfc->dev, dma_addr, len, DMA_FROM_DEVICE); in anfc_read_page_hw_ecc()
373 dev_err(nfc->dev, "Error reading page %d\n", page); in anfc_read_page_hw_ecc()
378 ret = nand_change_read_column_op(chip, mtd->writesize, chip->oob_poi, in anfc_read_page_hw_ecc()
379 mtd->oobsize, 0); in anfc_read_page_hw_ecc()
388 for (step = 0; step < chip->ecc.steps; step++) { in anfc_read_page_hw_ecc()
389 u8 *raw_buf = &buf[step * chip->ecc.size]; in anfc_read_page_hw_ecc()
394 memset(anand->hw_ecc, 0, chip->ecc.bytes); in anfc_read_page_hw_ecc()
395 nand_extract_bits(anand->hw_ecc, 0, in anfc_read_page_hw_ecc()
396 &chip->oob_poi[mtd->oobsize - anand->ecc_total], in anfc_read_page_hw_ecc()
397 anand->ecc_bits * step, anand->ecc_bits); in anfc_read_page_hw_ecc()
399 bf = bch_decode(anand->bch, raw_buf, chip->ecc.size, in anfc_read_page_hw_ecc()
400 anand->hw_ecc, NULL, NULL, anand->errloc); in anfc_read_page_hw_ecc()
406 if (anand->errloc[i] < (chip->ecc.size * 8)) { in anfc_read_page_hw_ecc()
407 bit = BIT(anand->errloc[i] & 7); in anfc_read_page_hw_ecc()
408 byte = anand->errloc[i] >> 3; in anfc_read_page_hw_ecc()
413 mtd->ecc_stats.corrected += bf; in anfc_read_page_hw_ecc()
419 bf = nand_check_erased_ecc_chunk(raw_buf, chip->ecc.size, in anfc_read_page_hw_ecc()
421 chip->ecc.strength); in anfc_read_page_hw_ecc()
423 mtd->ecc_stats.corrected += bf; in anfc_read_page_hw_ecc()
425 memset(raw_buf, 0xFF, chip->ecc.size); in anfc_read_page_hw_ecc()
427 mtd->ecc_stats.failed++; in anfc_read_page_hw_ecc()
439 ret = anfc_select_target(chip, chip->cur_cs); in anfc_sel_read_page_hw_ecc()
450 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_write_page_hw_ecc()
452 unsigned int len = mtd->writesize + (oob_required ? mtd->oobsize : 0); in anfc_write_page_hw_ecc()
458 PKT_SIZE(chip->ecc.size) | in anfc_write_page_hw_ecc()
459 PKT_STEPS(chip->ecc.steps), in anfc_write_page_hw_ecc()
461 (page & 0xFF) << (8 * (anand->caddr_cycles)) | in anfc_write_page_hw_ecc()
462 (((page >> 8) & 0xFF) << (8 * (1 + anand->caddr_cycles))), in anfc_write_page_hw_ecc()
465 ADDR2_STRENGTH(anand->strength) | in anfc_write_page_hw_ecc()
466 ADDR2_CS(anand->cs), in anfc_write_page_hw_ecc()
470 CMD_PAGE_SIZE(anand->page_sz) | in anfc_write_page_hw_ecc()
472 CMD_NADDRS(anand->caddr_cycles + in anfc_write_page_hw_ecc()
473 anand->raddr_cycles) | in anfc_write_page_hw_ecc()
478 writel_relaxed(anand->ecc_conf, nfc->base + ECC_CONF_REG); in anfc_write_page_hw_ecc()
480 ECC_SP_ADDRS(anand->caddr_cycles), in anfc_write_page_hw_ecc()
481 nfc->base + ECC_SP_REG); in anfc_write_page_hw_ecc()
483 dma_addr = dma_map_single(nfc->dev, (void *)buf, len, DMA_TO_DEVICE); in anfc_write_page_hw_ecc()
484 if (dma_mapping_error(nfc->dev, dma_addr)) { in anfc_write_page_hw_ecc()
485 dev_err(nfc->dev, "Buffer mapping error"); in anfc_write_page_hw_ecc()
486 return -EIO; in anfc_write_page_hw_ecc()
489 writel_relaxed(lower_32_bits(dma_addr), nfc->base + DMA_ADDR0_REG); in anfc_write_page_hw_ecc()
490 writel_relaxed(upper_32_bits(dma_addr), nfc->base + DMA_ADDR1_REG); in anfc_write_page_hw_ecc()
494 dma_unmap_single(nfc->dev, dma_addr, len, DMA_TO_DEVICE); in anfc_write_page_hw_ecc()
496 dev_err(nfc->dev, "Error writing page %d\n", page); in anfc_write_page_hw_ecc()
513 return -EIO; in anfc_write_page_hw_ecc()
523 ret = anfc_select_target(chip, chip->cur_cs); in anfc_sel_write_page_hw_ecc()
530 /* NAND framework ->exec_op() hooks and related helpers */
542 nfc_op->addr2_reg = ADDR2_CS(anand->cs); in anfc_parse_instructions()
543 nfc_op->cmd_reg = CMD_PAGE_SIZE(anand->page_sz); in anfc_parse_instructions()
545 for (op_id = 0; op_id < subop->ninstrs; op_id++) { in anfc_parse_instructions()
550 instr = &subop->instrs[op_id]; in anfc_parse_instructions()
552 switch (instr->type) { in anfc_parse_instructions()
555 nfc_op->cmd_reg |= CMD_1(instr->ctx.cmd.opcode); in anfc_parse_instructions()
557 nfc_op->cmd_reg |= CMD_2(instr->ctx.cmd.opcode); in anfc_parse_instructions()
565 addrs = &instr->ctx.addr.addrs[offset]; in anfc_parse_instructions()
566 nfc_op->cmd_reg |= CMD_NADDRS(naddrs); in anfc_parse_instructions()
570 nfc_op->addr1_reg |= (u32)addrs[i] << i * 8; in anfc_parse_instructions()
572 nfc_op->addr2_reg |= addrs[i]; in anfc_parse_instructions()
577 nfc_op->read = true; in anfc_parse_instructions()
581 buf = instr->ctx.data.buf.in; in anfc_parse_instructions()
582 nfc_op->buf = &buf[offset]; in anfc_parse_instructions()
583 nfc_op->len = nand_subop_get_data_len(subop, op_id); in anfc_parse_instructions()
584 ret = anfc_pkt_len_config(nfc_op->len, &nfc_op->steps, in anfc_parse_instructions()
603 nfc_op->pkt_reg |= PKT_SIZE(round_up(pktsize, 4)) | in anfc_parse_instructions()
604 PKT_STEPS(nfc_op->steps); in anfc_parse_instructions()
607 nfc_op->rdy_timeout_ms = instr->ctx.waitrdy.timeout_ms; in anfc_parse_instructions()
617 unsigned int dwords = (nfc_op->len / 4) / nfc_op->steps; in anfc_rw_pio_op()
618 unsigned int last_len = nfc_op->len % 4; in anfc_rw_pio_op()
620 u8 *buf = nfc_op->buf; in anfc_rw_pio_op()
623 for (i = 0; i < nfc_op->steps; i++) { in anfc_rw_pio_op()
624 dir = nfc_op->read ? READ_READY : WRITE_READY; in anfc_rw_pio_op()
627 dev_err(nfc->dev, "PIO %s ready signal not received\n", in anfc_rw_pio_op()
628 nfc_op->read ? "Read" : "Write"); in anfc_rw_pio_op()
633 if (nfc_op->read) in anfc_rw_pio_op()
634 ioread32_rep(nfc->base + DATA_PORT_REG, &buf[offset], in anfc_rw_pio_op()
637 iowrite32_rep(nfc->base + DATA_PORT_REG, &buf[offset], in anfc_rw_pio_op()
644 offset = nfc_op->len - last_len; in anfc_rw_pio_op()
646 if (nfc_op->read) { in anfc_rw_pio_op()
647 remainder = readl_relaxed(nfc->base + DATA_PORT_REG); in anfc_rw_pio_op()
651 writel_relaxed(remainder, nfc->base + DATA_PORT_REG); in anfc_rw_pio_op()
662 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_misc_data_type_exec()
710 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_misc_zerolen_type_exec()
734 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_status_type_exec()
739 if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS) in anfc_status_type_exec()
740 return -ENOTSUPP; in anfc_status_type_exec()
746 tmp = readl_relaxed(nfc->base + FLASH_STS_REG); in anfc_status_type_exec()
747 memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1); in anfc_status_type_exec()
767 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_wait_type_exec()
829 * The controller abstracts all the NAND operations and do not support in anfc_check_op()
835 for (op_id = 0; op_id < op->ninstrs; op_id++) { in anfc_check_op()
836 instr = &op->instrs[op_id]; in anfc_check_op()
838 switch (instr->type) { in anfc_check_op()
840 if (instr->ctx.addr.naddrs > ANFC_MAX_ADDR_CYC) in anfc_check_op()
841 return -ENOTSUPP; in anfc_check_op()
846 if (instr->ctx.data.len > ANFC_MAX_CHUNK_SIZE) in anfc_check_op()
847 return -ENOTSUPP; in anfc_check_op()
849 if (anfc_pkt_len_config(instr->ctx.data.len, 0, 0)) in anfc_check_op()
850 return -ENOTSUPP; in anfc_check_op()
866 * fixed patterns instead of open-coding this check here. in anfc_check_op()
868 if (op->ninstrs == 2 && in anfc_check_op()
869 op->instrs[0].type == NAND_OP_CMD_INSTR && in anfc_check_op()
870 op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS && in anfc_check_op()
871 op->instrs[1].type == NAND_OP_DATA_IN_INSTR) in anfc_check_op()
872 return -ENOTSUPP; in anfc_check_op()
886 ret = anfc_select_target(chip, op->cs); in anfc_exec_op()
897 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_setup_interface()
898 struct device_node *np = nfc->dev->of_node; in anfc_setup_interface()
909 * a multiple of 4. In practice, most data accesses are 4-byte in anfc_setup_interface()
912 * the device *and* we are using the NV-DDR interface(!). In in anfc_setup_interface()
919 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) in anfc_setup_interface()
920 return -ENOTSUPP; in anfc_setup_interface()
931 anand->timings = DIFACE_SDR | in anfc_setup_interface()
932 DIFACE_SDR_MODE(conf->timings.mode); in anfc_setup_interface()
934 anand->timings = DIFACE_NVDDR | in anfc_setup_interface()
935 DIFACE_DDR_MODE(conf->timings.mode); in anfc_setup_interface()
938 anand->clk = ANFC_XLNX_SDR_DFLT_CORE_CLK; in anfc_setup_interface()
941 anand->clk = div_u64((u64)NSEC_PER_SEC * 1000, in anfc_setup_interface()
942 conf->timings.nvddr.tCK_min); in anfc_setup_interface()
946 * Due to a hardware bug in the ZynqMP SoC, SDR timing modes 0-1 work in anfc_setup_interface()
949 * 80MHz when using SDR modes 2-5 with this SoC. in anfc_setup_interface()
951 if (of_device_is_compatible(np, "xlnx,zynqmp-nand-controller") && in anfc_setup_interface()
952 nand_interface_is_sdr(conf) && conf->timings.mode >= 2) in anfc_setup_interface()
953 anand->clk = ANFC_XLNX_SDR_HS_CORE_CLK; in anfc_setup_interface()
970 return -EINVAL; in anfc_calc_hw_ecc_bytes()
1006 struct nand_ecc_ctrl *ecc = &chip->ecc; in anfc_init_hw_ecc_controller()
1010 switch (mtd->writesize) { in anfc_init_hw_ecc_controller()
1018 dev_err(nfc->dev, "Unsupported page size %d\n", mtd->writesize); in anfc_init_hw_ecc_controller()
1019 return -EINVAL; in anfc_init_hw_ecc_controller()
1022 ret = nand_ecc_choose_conf(chip, &anfc_hw_ecc_caps, mtd->oobsize); in anfc_init_hw_ecc_controller()
1026 switch (ecc->strength) { in anfc_init_hw_ecc_controller()
1028 anand->strength = 0x1; in anfc_init_hw_ecc_controller()
1031 anand->strength = 0x2; in anfc_init_hw_ecc_controller()
1034 anand->strength = 0x3; in anfc_init_hw_ecc_controller()
1037 anand->strength = 0x4; in anfc_init_hw_ecc_controller()
1040 dev_err(nfc->dev, "Unsupported strength %d\n", ecc->strength); in anfc_init_hw_ecc_controller()
1041 return -EINVAL; in anfc_init_hw_ecc_controller()
1044 switch (ecc->size) { in anfc_init_hw_ecc_controller()
1054 dev_err(nfc->dev, "Unsupported step size %d\n", ecc->strength); in anfc_init_hw_ecc_controller()
1055 return -EINVAL; in anfc_init_hw_ecc_controller()
1060 ecc->steps = mtd->writesize / ecc->size; in anfc_init_hw_ecc_controller()
1061 ecc->algo = NAND_ECC_ALGO_BCH; in anfc_init_hw_ecc_controller()
1062 anand->ecc_bits = bch_gf_mag * ecc->strength; in anfc_init_hw_ecc_controller()
1063 ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8); in anfc_init_hw_ecc_controller()
1064 anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8); in anfc_init_hw_ecc_controller()
1065 ecc_offset = mtd->writesize + mtd->oobsize - anand->ecc_total; in anfc_init_hw_ecc_controller()
1066 anand->ecc_conf = ECC_CONF_COL(ecc_offset) | in anfc_init_hw_ecc_controller()
1067 ECC_CONF_LEN(anand->ecc_total) | in anfc_init_hw_ecc_controller()
1070 anand->errloc = devm_kmalloc_array(nfc->dev, ecc->strength, in anfc_init_hw_ecc_controller()
1071 sizeof(*anand->errloc), GFP_KERNEL); in anfc_init_hw_ecc_controller()
1072 if (!anand->errloc) in anfc_init_hw_ecc_controller()
1073 return -ENOMEM; in anfc_init_hw_ecc_controller()
1075 anand->hw_ecc = devm_kmalloc(nfc->dev, ecc->bytes, GFP_KERNEL); in anfc_init_hw_ecc_controller()
1076 if (!anand->hw_ecc) in anfc_init_hw_ecc_controller()
1077 return -ENOMEM; in anfc_init_hw_ecc_controller()
1080 anand->bch = bch_init(bch_gf_mag, ecc->strength, bch_prim_poly, true); in anfc_init_hw_ecc_controller()
1081 if (!anand->bch) in anfc_init_hw_ecc_controller()
1082 return -EINVAL; in anfc_init_hw_ecc_controller()
1084 ecc->read_page = anfc_sel_read_page_hw_ecc; in anfc_init_hw_ecc_controller()
1085 ecc->write_page = anfc_sel_write_page_hw_ecc; in anfc_init_hw_ecc_controller()
1093 struct arasan_nfc *nfc = to_anfc(chip->controller); in anfc_attach_chip()
1097 if (mtd->writesize <= SZ_512) in anfc_attach_chip()
1098 anand->caddr_cycles = 1; in anfc_attach_chip()
1100 anand->caddr_cycles = 2; in anfc_attach_chip()
1102 if (chip->options & NAND_ROW_ADDR_3) in anfc_attach_chip()
1103 anand->raddr_cycles = 3; in anfc_attach_chip()
1105 anand->raddr_cycles = 2; in anfc_attach_chip()
1107 switch (mtd->writesize) { in anfc_attach_chip()
1109 anand->page_sz = 0; in anfc_attach_chip()
1112 anand->page_sz = 5; in anfc_attach_chip()
1115 anand->page_sz = 1; in anfc_attach_chip()
1118 anand->page_sz = 2; in anfc_attach_chip()
1121 anand->page_sz = 3; in anfc_attach_chip()
1124 anand->page_sz = 4; in anfc_attach_chip()
1127 return -EINVAL; in anfc_attach_chip()
1131 chip->ecc.read_page_raw = nand_monolithic_read_page_raw; in anfc_attach_chip()
1132 chip->ecc.write_page_raw = nand_monolithic_write_page_raw; in anfc_attach_chip()
1134 switch (chip->ecc.engine_type) { in anfc_attach_chip()
1143 dev_err(nfc->dev, "Unsupported ECC mode: %d\n", in anfc_attach_chip()
1144 chip->ecc.engine_type); in anfc_attach_chip()
1145 return -EINVAL; in anfc_attach_chip()
1155 if (anand->bch) in anfc_detach_chip()
1156 bch_free(anand->bch); in anfc_detach_chip()
1171 int cs, rb, ret; in anfc_chip_init() local
1173 anand = devm_kzalloc(nfc->dev, sizeof(*anand), GFP_KERNEL); in anfc_chip_init()
1175 return -ENOMEM; in anfc_chip_init()
1179 dev_err(nfc->dev, "Invalid reg property\n"); in anfc_chip_init()
1180 return -EINVAL; in anfc_chip_init()
1187 ret = of_property_read_u32(np, "nand-rb", &rb); in anfc_chip_init()
1191 if (cs >= ANFC_MAX_CS || rb >= ANFC_MAX_CS) { in anfc_chip_init()
1192 dev_err(nfc->dev, "Wrong CS %d or RB %d\n", cs, rb); in anfc_chip_init()
1193 return -EINVAL; in anfc_chip_init()
1196 if (test_and_set_bit(cs, &nfc->assigned_cs)) { in anfc_chip_init()
1197 dev_err(nfc->dev, "Already assigned CS %d\n", cs); in anfc_chip_init()
1198 return -EINVAL; in anfc_chip_init()
1201 anand->cs = cs; in anfc_chip_init()
1202 anand->rb = rb; in anfc_chip_init()
1204 chip = &anand->chip; in anfc_chip_init()
1206 mtd->dev.parent = nfc->dev; in anfc_chip_init()
1207 chip->controller = &nfc->controller; in anfc_chip_init()
1208 chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | in anfc_chip_init()
1212 if (!mtd->name) { in anfc_chip_init()
1213 dev_err(nfc->dev, "NAND label property is mandatory\n"); in anfc_chip_init()
1214 return -EINVAL; in anfc_chip_init()
1219 dev_err(nfc->dev, "Scan operation failed\n"); in anfc_chip_init()
1229 list_add_tail(&anand->node, &nfc->chips); in anfc_chip_init()
1240 list_for_each_entry_safe(anand, tmp, &nfc->chips, node) { in anfc_chips_cleanup()
1241 chip = &anand->chip; in anfc_chips_cleanup()
1245 list_del(&anand->node); in anfc_chips_cleanup()
1251 struct device_node *np = nfc->dev->of_node, *nand_np; in anfc_chips_init()
1256 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n", in anfc_chips_init()
1258 return -EINVAL; in anfc_chips_init()
1276 writel_relaxed(0, nfc->base + INTR_SIG_EN_REG); in anfc_reset()
1279 writel_relaxed(EVENT_MASK, nfc->base + INTR_STS_EN_REG); in anfc_reset()
1287 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); in anfc_probe()
1289 return -ENOMEM; in anfc_probe()
1291 nfc->dev = &pdev->dev; in anfc_probe()
1292 nand_controller_init(&nfc->controller); in anfc_probe()
1293 nfc->controller.ops = &anfc_ops; in anfc_probe()
1294 INIT_LIST_HEAD(&nfc->chips); in anfc_probe()
1296 nfc->base = devm_platform_ioremap_resource(pdev, 0); in anfc_probe()
1297 if (IS_ERR(nfc->base)) in anfc_probe()
1298 return PTR_ERR(nfc->base); in anfc_probe()
1302 nfc->controller_clk = devm_clk_get(&pdev->dev, "controller"); in anfc_probe()
1303 if (IS_ERR(nfc->controller_clk)) in anfc_probe()
1304 return PTR_ERR(nfc->controller_clk); in anfc_probe()
1306 nfc->bus_clk = devm_clk_get(&pdev->dev, "bus"); in anfc_probe()
1307 if (IS_ERR(nfc->bus_clk)) in anfc_probe()
1308 return PTR_ERR(nfc->bus_clk); in anfc_probe()
1310 ret = clk_prepare_enable(nfc->controller_clk); in anfc_probe()
1314 ret = clk_prepare_enable(nfc->bus_clk); in anfc_probe()
1327 clk_disable_unprepare(nfc->bus_clk); in anfc_probe()
1330 clk_disable_unprepare(nfc->controller_clk); in anfc_probe()
1341 clk_disable_unprepare(nfc->bus_clk); in anfc_remove()
1342 clk_disable_unprepare(nfc->controller_clk); in anfc_remove()
1349 .compatible = "xlnx,zynqmp-nand-controller",
1352 .compatible = "arasan,nfc-v3p10",
1360 .name = "arasan-nand-controller",
1372 MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");