32 /* HW sequencer opcodes */
132  * @sregs: Start of software sequencer registers
136  * @swseq_reg: Use SW sequencer in register reads/writes
137  * @swseq_erase: Use SW sequencer in erase operation
241 	dev_dbg(ispi->dev, "Using %cW sequencer for register access\n",  in intel_spi_dump_regs()
243 	dev_dbg(ispi->dev, "Using %cW sequencer for erase operation\n",  in intel_spi_dump_regs()
361 	/* Disable #SMI generation from HW sequencer */  in intel_spi_init()
367 	 * Determine whether erase operation should use HW or SW sequencer.  in intel_spi_init()
369 	 * The HW sequencer has a predefined list of opcodes, with only the  in intel_spi_init()
372 	 * cannot be done using HW sequencer.  in intel_spi_init()
385 		dev_err(ispi->dev, "software sequencer not supported, but required\n");  in intel_spi_init()
391 	 * sequencer. All other operations are supposed to be carried out  in intel_spi_init()
392 	 * using software sequencer.  in intel_spi_init()
395 		/* Disable #SMI generation from SW sequencer */  in intel_spi_init()
506 	 * Always clear it after each SW sequencer operation regardless  in intel_spi_sw_cycle()
590 	 * When hardware sequencer is used there is no need to program  in intel_spi_write_reg()
615 	 * We hope that HW sequencer will do the right thing automatically and  in intel_spi_write_reg()
616 	 * with the SW sequencer we cannot use preopcode anyway, so just ignore  in intel_spi_write_reg()
645 	 * Atomic sequence is not expected with HW sequencer reads. Make  in intel_spi_read()
715 	/* Not needed with HW sequencer write, make sure it is cleared */  in intel_spi_write()
802 	/* Not needed with HW sequencer erase, make sure it is cleared */  in intel_spi_erase()