Lines Matching +full:p1010 +full:- +full:flexcan
1 // SPDX-License-Identifier: GPL-2.0
3 // flexcan.c - FLEXCAN CAN controller driver
5 // Copyright (c) 2005-2006 Varma Electronics Oy
7 // Copyright (c) 2010-2017 Pengutronix, Marc Kleine-Budde <kernel@pengutronix.de>
10 // Based on code originally by Andrey Volkov <avolkov@varma-el.com>
17 #include <linux/can/rx-offload.h>
33 #define DRV_NAME "flexcan"
38 /* FLEXCAN module configuration register (CANMCR) bits */
65 /* FLEXCAN control register (CANCTRL) bits */
89 /* FLEXCAN control register 2 (CTRL2) bits */
99 /* FLEXCAN memory error control register (MECR) bits */
111 /* FLEXCAN error and status register (ESR) bits */
143 /* FLEXCAN Bit Timing register (CBT) bits */
151 /* FLEXCAN FD control register (FDCTRL) bits */
164 /* FLEXCAN FD Bit Timing register (FDCBT) bits */
171 /* FLEXCAN interrupt flag register (IFLAG) bits */
181 /* FLEXCAN message buffers */
206 /* FLEXCAN hardware feature flags
209 * SOC Version IP-Version Glitch- [TR]WRN_INT IRQ Err Memory err RTR rece- FD Mode
231 /* Disable non-correctable errors interrupt and freeze mode */
241 /* Support CAN-FD mode */
256 u32 ctrl; /* 0x04 - Not affected by Soft Reset */
259 u32 rxgmask; /* 0x10 - Not affected by Soft Reset */
260 u32 rx14mask; /* 0x14 - Not affected by Soft Reset */
261 u32 rx15mask; /* 0x18 - Not affected by Soft Reset */
270 u32 ctrl2; /* MX6, VF610 - Not affected by Soft Reset */
277 u32 rxfir; /* 0x4c - Not affected by Soft Reset */
278 u32 cbt; /* 0x50 - Not affected by Soft Reset */
283 u8 mb[2][512]; /* 0x80 - Not affected by Soft Reset */
284 /* FIFO-mode:
287 * 0x090...0x0df 1-5 reserved
288 * 0x0e0...0x0ff 6-7 8 entry ID table
290 * 0x0e0...0x2df 6-7..37 8..128 entry ID table
295 u32 rximr[64]; /* 0x880 - Not affected by Soft Reset */
297 u32 gfwr_mx6; /* 0x9e0 - MX6 */
317 u32 fdctrl; /* 0xc00 - Not affected by Soft Reset */
318 u32 fdcbt; /* 0xc04 - Not affected by Soft Reset */
454 /* FlexCAN module is essentially modelled as a little-endian IP in most
456 * implemented in a little-endian fashion.
458 * However there are some SoCs (e.g. LS1021A) which implement the FlexCAN
459 * module in a big-endian fashion (i.e the registers as well as the
460 * message buffer areas are implemented in a big-endian way).
462 * In addition, the FlexCAN module can be found on SoCs having ARM or
493 if (WARN_ON(mb_index >= priv->mb_count)) in flexcan_get_mb()
496 bank_size = sizeof(priv->regs->mb[0]) / priv->mb_size; in flexcan_get_mb()
500 mb_index -= bank_size; in flexcan_get_mb()
503 (&priv->regs->mb[bank][priv->mb_size * mb_index]); in flexcan_get_mb()
508 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_low_power_enter_ack()
511 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) in flexcan_low_power_enter_ack()
514 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) in flexcan_low_power_enter_ack()
515 return -ETIMEDOUT; in flexcan_low_power_enter_ack()
522 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_low_power_exit_ack()
525 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK)) in flexcan_low_power_exit_ack()
528 if (priv->read(®s->mcr) & FLEXCAN_MCR_LPM_ACK) in flexcan_low_power_exit_ack()
529 return -ETIMEDOUT; in flexcan_low_power_exit_ack()
536 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_enable_wakeup_irq()
539 reg_mcr = priv->read(®s->mcr); in flexcan_enable_wakeup_irq()
546 priv->write(reg_mcr, ®s->mcr); in flexcan_enable_wakeup_irq()
551 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_enter_stop_mode()
554 reg_mcr = priv->read(®s->mcr); in flexcan_enter_stop_mode()
556 priv->write(reg_mcr, ®s->mcr); in flexcan_enter_stop_mode()
559 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, in flexcan_enter_stop_mode()
560 1 << priv->stm.req_bit, 1 << priv->stm.req_bit); in flexcan_enter_stop_mode()
567 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_exit_stop_mode()
571 regmap_update_bits(priv->stm.gpr, priv->stm.req_gpr, in flexcan_exit_stop_mode()
572 1 << priv->stm.req_bit, 0); in flexcan_exit_stop_mode()
574 reg_mcr = priv->read(®s->mcr); in flexcan_exit_stop_mode()
576 priv->write(reg_mcr, ®s->mcr); in flexcan_exit_stop_mode()
583 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_error_irq_enable()
584 u32 reg_ctrl = (priv->reg_ctrl_default | FLEXCAN_CTRL_ERR_MSK); in flexcan_error_irq_enable()
586 priv->write(reg_ctrl, ®s->ctrl); in flexcan_error_irq_enable()
591 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_error_irq_disable()
592 u32 reg_ctrl = (priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_MSK); in flexcan_error_irq_disable()
594 priv->write(reg_ctrl, ®s->ctrl); in flexcan_error_irq_disable()
601 err = clk_prepare_enable(priv->clk_ipg); in flexcan_clks_enable()
605 err = clk_prepare_enable(priv->clk_per); in flexcan_clks_enable()
607 clk_disable_unprepare(priv->clk_ipg); in flexcan_clks_enable()
614 clk_disable_unprepare(priv->clk_per); in flexcan_clks_disable()
615 clk_disable_unprepare(priv->clk_ipg); in flexcan_clks_disable()
620 if (!priv->reg_xceiver) in flexcan_transceiver_enable()
623 return regulator_enable(priv->reg_xceiver); in flexcan_transceiver_enable()
628 if (!priv->reg_xceiver) in flexcan_transceiver_disable()
631 return regulator_disable(priv->reg_xceiver); in flexcan_transceiver_disable()
636 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_enable()
639 reg = priv->read(®s->mcr); in flexcan_chip_enable()
641 priv->write(reg, ®s->mcr); in flexcan_chip_enable()
648 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_disable()
651 reg = priv->read(®s->mcr); in flexcan_chip_disable()
653 priv->write(reg, ®s->mcr); in flexcan_chip_disable()
660 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_freeze()
662 u32 bitrate = priv->can.bittiming.bitrate; in flexcan_chip_freeze()
670 reg = priv->read(®s->mcr); in flexcan_chip_freeze()
672 priv->write(reg, ®s->mcr); in flexcan_chip_freeze()
674 while (timeout-- && !(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) in flexcan_chip_freeze()
677 if (!(priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) in flexcan_chip_freeze()
678 return -ETIMEDOUT; in flexcan_chip_freeze()
685 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_unfreeze()
689 reg = priv->read(®s->mcr); in flexcan_chip_unfreeze()
691 priv->write(reg, ®s->mcr); in flexcan_chip_unfreeze()
693 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK)) in flexcan_chip_unfreeze()
696 if (priv->read(®s->mcr) & FLEXCAN_MCR_FRZ_ACK) in flexcan_chip_unfreeze()
697 return -ETIMEDOUT; in flexcan_chip_unfreeze()
704 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_softreset()
707 priv->write(FLEXCAN_MCR_SOFTRST, ®s->mcr); in flexcan_chip_softreset()
708 while (timeout-- && (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST)) in flexcan_chip_softreset()
711 if (priv->read(®s->mcr) & FLEXCAN_MCR_SOFTRST) in flexcan_chip_softreset()
712 return -ETIMEDOUT; in flexcan_chip_softreset()
721 struct flexcan_regs __iomem *regs = priv->regs; in __flexcan_get_berr_counter()
722 u32 reg = priv->read(®s->ecr); in __flexcan_get_berr_counter()
724 bec->txerr = (reg >> 0) & 0xff; in __flexcan_get_berr_counter()
725 bec->rxerr = (reg >> 8) & 0xff; in __flexcan_get_berr_counter()
736 err = pm_runtime_get_sync(priv->dev); in flexcan_get_berr_counter()
738 pm_runtime_put_noidle(priv->dev); in flexcan_get_berr_counter()
744 pm_runtime_put(priv->dev); in flexcan_get_berr_counter()
752 struct canfd_frame *cfd = (struct canfd_frame *)skb->data; in flexcan_start_xmit()
755 u32 ctrl = FLEXCAN_MB_CODE_TX_DATA | ((can_len2dlc(cfd->len)) << 16); in flexcan_start_xmit()
763 if (cfd->can_id & CAN_EFF_FLAG) { in flexcan_start_xmit()
764 can_id = cfd->can_id & CAN_EFF_MASK; in flexcan_start_xmit()
767 can_id = (cfd->can_id & CAN_SFF_MASK) << 18; in flexcan_start_xmit()
770 if (cfd->can_id & CAN_RTR_FLAG) in flexcan_start_xmit()
776 if (cfd->flags & CANFD_BRS) in flexcan_start_xmit()
780 for (i = 0; i < cfd->len; i += sizeof(u32)) { in flexcan_start_xmit()
781 data = be32_to_cpup((__be32 *)&cfd->data[i]); in flexcan_start_xmit()
782 priv->write(data, &priv->tx_mb->data[i / sizeof(u32)]); in flexcan_start_xmit()
787 priv->write(can_id, &priv->tx_mb->can_id); in flexcan_start_xmit()
788 priv->write(ctrl, &priv->tx_mb->can_ctrl); in flexcan_start_xmit()
793 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, in flexcan_start_xmit()
794 &priv->tx_mb_reserved->can_ctrl); in flexcan_start_xmit()
795 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, in flexcan_start_xmit()
796 &priv->tx_mb_reserved->can_ctrl); in flexcan_start_xmit()
804 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_irq_bus_err()
811 timestamp = priv->read(®s->timer) << 16; in flexcan_irq_bus_err()
817 cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; in flexcan_irq_bus_err()
821 cf->data[2] |= CAN_ERR_PROT_BIT1; in flexcan_irq_bus_err()
826 cf->data[2] |= CAN_ERR_PROT_BIT0; in flexcan_irq_bus_err()
831 cf->can_id |= CAN_ERR_ACK; in flexcan_irq_bus_err()
832 cf->data[3] = CAN_ERR_PROT_LOC_ACK; in flexcan_irq_bus_err()
837 cf->data[2] |= CAN_ERR_PROT_BIT; in flexcan_irq_bus_err()
838 cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; in flexcan_irq_bus_err()
843 cf->data[2] |= CAN_ERR_PROT_FORM; in flexcan_irq_bus_err()
848 cf->data[2] |= CAN_ERR_PROT_STUFF; in flexcan_irq_bus_err()
852 priv->can.can_stats.bus_error++; in flexcan_irq_bus_err()
854 dev->stats.rx_errors++; in flexcan_irq_bus_err()
856 dev->stats.tx_errors++; in flexcan_irq_bus_err()
858 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); in flexcan_irq_bus_err()
860 dev->stats.rx_fifo_errors++; in flexcan_irq_bus_err()
866 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_irq_state()
891 if (likely(new_state == priv->can.state)) in flexcan_irq_state()
894 timestamp = priv->read(®s->timer) << 16; in flexcan_irq_state()
905 err = can_rx_offload_queue_sorted(&priv->offload, skb, timestamp); in flexcan_irq_state()
907 dev->stats.rx_fifo_errors++; in flexcan_irq_state()
915 reg = (u64)priv->read(addr - 4) << 32; in flexcan_read64_mask()
917 reg |= priv->read(addr); in flexcan_read64_mask()
925 priv->write(upper_32_bits(val), addr - 4); in flexcan_write64()
927 priv->write(lower_32_bits(val), addr); in flexcan_write64()
932 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->rx_mask); in flexcan_read_reg_iflag_rx()
937 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask); in flexcan_read_reg_iflag_tx()
950 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_mailbox_read()
959 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { in flexcan_mailbox_read()
963 reg_ctrl = priv->read(&mb->can_ctrl); in flexcan_mailbox_read()
974 offload->dev->stats.rx_over_errors++; in flexcan_mailbox_read()
975 offload->dev->stats.rx_errors++; in flexcan_mailbox_read()
978 reg_iflag1 = priv->read(®s->iflag1); in flexcan_mailbox_read()
982 reg_ctrl = priv->read(&mb->can_ctrl); in flexcan_mailbox_read()
986 skb = ERR_PTR(-ENOBUFS); in flexcan_mailbox_read()
991 skb = alloc_canfd_skb(offload->dev, &cfd); in flexcan_mailbox_read()
993 skb = alloc_can_skb(offload->dev, (struct can_frame **)&cfd); in flexcan_mailbox_read()
995 skb = ERR_PTR(-ENOMEM); in flexcan_mailbox_read()
1002 reg_id = priv->read(&mb->can_id); in flexcan_mailbox_read()
1004 cfd->can_id = ((reg_id >> 0) & CAN_EFF_MASK) | CAN_EFF_FLAG; in flexcan_mailbox_read()
1006 cfd->can_id = (reg_id >> 18) & CAN_SFF_MASK; in flexcan_mailbox_read()
1009 cfd->len = can_dlc2len(get_canfd_dlc((reg_ctrl >> 16) & 0xf)); in flexcan_mailbox_read()
1012 cfd->flags |= CANFD_BRS; in flexcan_mailbox_read()
1014 cfd->len = get_can_dlc((reg_ctrl >> 16) & 0xf); in flexcan_mailbox_read()
1017 cfd->can_id |= CAN_RTR_FLAG; in flexcan_mailbox_read()
1021 cfd->flags |= CANFD_ESI; in flexcan_mailbox_read()
1023 for (i = 0; i < cfd->len; i += sizeof(u32)) { in flexcan_mailbox_read()
1024 __be32 data = cpu_to_be32(priv->read(&mb->data[i / sizeof(u32)])); in flexcan_mailbox_read()
1025 *(__be32 *)(cfd->data + i) = data; in flexcan_mailbox_read()
1029 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) in flexcan_mailbox_read()
1030 flexcan_write64(priv, FLEXCAN_IFLAG_MB(n), ®s->iflag1); in flexcan_mailbox_read()
1032 priv->write(FLEXCAN_IFLAG_RX_FIFO_AVAILABLE, ®s->iflag1); in flexcan_mailbox_read()
1038 priv->read(®s->timer); in flexcan_mailbox_read()
1046 struct net_device_stats *stats = &dev->stats; in flexcan_irq()
1048 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_irq()
1052 enum can_state last_state = priv->can.state; in flexcan_irq()
1055 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { in flexcan_irq()
1061 ret = can_rx_offload_irq_offload_timestamp(&priv->offload, in flexcan_irq()
1069 reg_iflag1 = priv->read(®s->iflag1); in flexcan_irq()
1072 can_rx_offload_irq_offload_fifo(&priv->offload); in flexcan_irq()
1078 priv->write(FLEXCAN_IFLAG_RX_FIFO_OVERFLOW, in flexcan_irq()
1079 ®s->iflag1); in flexcan_irq()
1080 dev->stats.rx_over_errors++; in flexcan_irq()
1081 dev->stats.rx_errors++; in flexcan_irq()
1088 if (reg_iflag_tx & priv->tx_mask) { in flexcan_irq()
1089 u32 reg_ctrl = priv->read(&priv->tx_mb->can_ctrl); in flexcan_irq()
1092 stats->tx_bytes += can_rx_offload_get_echo_skb(&priv->offload, in flexcan_irq()
1094 stats->tx_packets++; in flexcan_irq()
1098 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, in flexcan_irq()
1099 &priv->tx_mb->can_ctrl); in flexcan_irq()
1100 flexcan_write64(priv, priv->tx_mask, ®s->iflag1); in flexcan_irq()
1104 reg_esr = priv->read(®s->esr); in flexcan_irq()
1109 priv->write(reg_esr & (FLEXCAN_ESR_ALL_INT | FLEXCAN_ESR_WAK_INT), ®s->esr); in flexcan_irq()
1114 (priv->devtype_data->quirks & (FLEXCAN_QUIRK_BROKEN_WERR_STATE | in flexcan_irq()
1118 /* bus error IRQ - handle if bus error reporting is activated */ in flexcan_irq()
1120 (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) in flexcan_irq()
1124 * bus error reporting is de-activated and in flexcan_irq()
1126 * +--------------------------------------------------------------+ in flexcan_irq()
1127 * | +----------------------------------------------+ [stopped / | in flexcan_irq()
1128 * | | | sleeping] -+ in flexcan_irq()
1129 * +-+-> active <-> warning <-> passive -> bus off -+ in flexcan_irq()
1135 if ((last_state != priv->can.state) && in flexcan_irq()
1136 (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_PERR_STATE) && in flexcan_irq()
1137 !(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) { in flexcan_irq()
1138 switch (priv->can.state) { in flexcan_irq()
1140 if (priv->devtype_data->quirks & in flexcan_irq()
1167 const struct can_bittiming *bt = &priv->can.bittiming; in flexcan_set_bittiming_ctrl()
1168 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_set_bittiming_ctrl()
1171 reg = priv->read(®s->ctrl); in flexcan_set_bittiming_ctrl()
1178 reg |= FLEXCAN_CTRL_PRESDIV(bt->brp - 1) | in flexcan_set_bittiming_ctrl()
1179 FLEXCAN_CTRL_PSEG1(bt->phase_seg1 - 1) | in flexcan_set_bittiming_ctrl()
1180 FLEXCAN_CTRL_PSEG2(bt->phase_seg2 - 1) | in flexcan_set_bittiming_ctrl()
1181 FLEXCAN_CTRL_RJW(bt->sjw - 1) | in flexcan_set_bittiming_ctrl()
1182 FLEXCAN_CTRL_PROPSEG(bt->prop_seg - 1); in flexcan_set_bittiming_ctrl()
1185 priv->write(reg, ®s->ctrl); in flexcan_set_bittiming_ctrl()
1189 priv->read(®s->mcr), priv->read(®s->ctrl)); in flexcan_set_bittiming_ctrl()
1195 struct can_bittiming *bt = &priv->can.bittiming; in flexcan_set_bittiming_cbt()
1196 struct can_bittiming *dbt = &priv->can.data_bittiming; in flexcan_set_bittiming_cbt()
1197 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_set_bittiming_cbt()
1207 if (bt->phase_seg1 > 0x20) { in flexcan_set_bittiming_cbt()
1208 bt->prop_seg += (bt->phase_seg1 - 0x20); in flexcan_set_bittiming_cbt()
1209 bt->phase_seg1 = 0x20; in flexcan_set_bittiming_cbt()
1213 FIELD_PREP(FLEXCAN_CBT_EPRESDIV_MASK, bt->brp - 1) | in flexcan_set_bittiming_cbt()
1214 FIELD_PREP(FLEXCAN_CBT_ERJW_MASK, bt->sjw - 1) | in flexcan_set_bittiming_cbt()
1215 FIELD_PREP(FLEXCAN_CBT_EPROPSEG_MASK, bt->prop_seg - 1) | in flexcan_set_bittiming_cbt()
1216 FIELD_PREP(FLEXCAN_CBT_EPSEG1_MASK, bt->phase_seg1 - 1) | in flexcan_set_bittiming_cbt()
1217 FIELD_PREP(FLEXCAN_CBT_EPSEG2_MASK, bt->phase_seg2 - 1); in flexcan_set_bittiming_cbt()
1220 priv->write(reg_cbt, ®s->cbt); in flexcan_set_bittiming_cbt()
1222 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { in flexcan_set_bittiming_cbt()
1225 if (bt->brp != dbt->brp) in flexcan_set_bittiming_cbt()
1227 dbt->brp, bt->brp); in flexcan_set_bittiming_cbt()
1237 if (dbt->phase_seg1 > 0x8) { in flexcan_set_bittiming_cbt()
1238 dbt->prop_seg += (dbt->phase_seg1 - 0x8); in flexcan_set_bittiming_cbt()
1239 dbt->phase_seg1 = 0x8; in flexcan_set_bittiming_cbt()
1242 reg_fdcbt = priv->read(®s->fdcbt); in flexcan_set_bittiming_cbt()
1249 reg_fdcbt |= FIELD_PREP(FLEXCAN_FDCBT_FPRESDIV_MASK, dbt->brp - 1) | in flexcan_set_bittiming_cbt()
1250 FIELD_PREP(FLEXCAN_FDCBT_FRJW_MASK, dbt->sjw - 1) | in flexcan_set_bittiming_cbt()
1251 FIELD_PREP(FLEXCAN_FDCBT_FPROPSEG_MASK, dbt->prop_seg) | in flexcan_set_bittiming_cbt()
1252 FIELD_PREP(FLEXCAN_FDCBT_FPSEG1_MASK, dbt->phase_seg1 - 1) | in flexcan_set_bittiming_cbt()
1253 FIELD_PREP(FLEXCAN_FDCBT_FPSEG2_MASK, dbt->phase_seg2 - 1); in flexcan_set_bittiming_cbt()
1256 priv->write(reg_fdcbt, ®s->fdcbt); in flexcan_set_bittiming_cbt()
1259 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_set_bittiming_cbt()
1261 if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) in flexcan_set_bittiming_cbt()
1265 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_set_bittiming_cbt()
1269 reg_fdctrl = priv->read(®s->fdctrl); in flexcan_set_bittiming_cbt()
1273 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { in flexcan_set_bittiming_cbt()
1276 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { in flexcan_set_bittiming_cbt()
1282 ((dbt->phase_seg1 - 1) + in flexcan_set_bittiming_cbt()
1283 dbt->prop_seg + 2) * in flexcan_set_bittiming_cbt()
1284 ((dbt->brp - 1 ) + 1)); in flexcan_set_bittiming_cbt()
1289 priv->write(reg_fdctrl, ®s->fdctrl); in flexcan_set_bittiming_cbt()
1293 priv->read(®s->mcr), priv->read(®s->ctrl), in flexcan_set_bittiming_cbt()
1294 priv->read(®s->ctrl2), priv->read(®s->fdctrl), in flexcan_set_bittiming_cbt()
1295 priv->read(®s->cbt), priv->read(®s->fdcbt)); in flexcan_set_bittiming_cbt()
1301 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_set_bittiming()
1304 reg = priv->read(®s->ctrl); in flexcan_set_bittiming()
1308 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) in flexcan_set_bittiming()
1310 if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) in flexcan_set_bittiming()
1312 if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) in flexcan_set_bittiming()
1316 priv->write(reg, ®s->ctrl); in flexcan_set_bittiming()
1318 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) in flexcan_set_bittiming()
1327 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_ram_init()
1338 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_ram_init()
1340 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_ram_init()
1342 memset_io(®s->mb[0][0], 0, in flexcan_ram_init()
1343 offsetof(struct flexcan_regs, rx_smb1[3]) - in flexcan_ram_init()
1346 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) in flexcan_ram_init()
1347 memset_io(®s->tx_smb_fd[0], 0, in flexcan_ram_init()
1348 offsetof(struct flexcan_regs, rx_smb1_fd[17]) - in flexcan_ram_init()
1352 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_ram_init()
1363 struct flexcan_regs __iomem *regs = priv->regs; in flexcan_chip_start()
1379 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_ECC) in flexcan_chip_start()
1397 reg_mcr = priv->read(®s->mcr); in flexcan_chip_start()
1400 FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_MAXMB(priv->tx_mb_idx); in flexcan_chip_start()
1405 * - disable for timestamp mode in flexcan_chip_start()
1406 * - enable for FIFO mode in flexcan_chip_start()
1408 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) in flexcan_chip_start()
1418 * earlier versions of flexcan block guide. in flexcan_chip_start()
1421 * - enable Self Reception for loopback mode in flexcan_chip_start()
1423 * - disable for normal operation in flexcan_chip_start()
1425 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) in flexcan_chip_start()
1430 /* MCR - CAN-FD */ in flexcan_chip_start()
1431 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) in flexcan_chip_start()
1437 priv->write(reg_mcr, ®s->mcr); in flexcan_chip_start()
1450 reg_ctrl = priv->read(®s->ctrl); in flexcan_chip_start()
1456 * on most Flexcan cores, too. Otherwise we don't get in flexcan_chip_start()
1459 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_WERR_STATE || in flexcan_chip_start()
1460 priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) in flexcan_chip_start()
1466 priv->reg_ctrl_default = reg_ctrl; in flexcan_chip_start()
1470 priv->write(reg_ctrl, ®s->ctrl); in flexcan_chip_start()
1472 if ((priv->devtype_data->quirks & FLEXCAN_QUIRK_ENABLE_EACEN_RRS)) { in flexcan_chip_start()
1473 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_chip_start()
1475 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_chip_start()
1478 if (priv->can.ctrlmode_supported & CAN_CTRLMODE_FD) { in flexcan_chip_start()
1481 reg_fdctrl = priv->read(®s->fdctrl); in flexcan_chip_start()
1485 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) { in flexcan_chip_start()
1501 priv->write(reg_fdctrl, ®s->fdctrl); in flexcan_chip_start()
1504 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { in flexcan_chip_start()
1505 for (i = priv->offload.mb_first; i <= priv->offload.mb_last; i++) { in flexcan_chip_start()
1507 priv->write(FLEXCAN_MB_CODE_RX_EMPTY, in flexcan_chip_start()
1508 &mb->can_ctrl); in flexcan_chip_start()
1512 for (i = FLEXCAN_TX_MB_RESERVED_OFF_FIFO; i < priv->mb_count; i++) { in flexcan_chip_start()
1514 priv->write(FLEXCAN_MB_CODE_RX_INACTIVE, in flexcan_chip_start()
1515 &mb->can_ctrl); in flexcan_chip_start()
1520 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, in flexcan_chip_start()
1521 &priv->tx_mb_reserved->can_ctrl); in flexcan_chip_start()
1524 priv->write(FLEXCAN_MB_CODE_TX_INACTIVE, in flexcan_chip_start()
1525 &priv->tx_mb->can_ctrl); in flexcan_chip_start()
1528 priv->write(0x0, ®s->rxgmask); in flexcan_chip_start()
1529 priv->write(0x0, ®s->rx14mask); in flexcan_chip_start()
1530 priv->write(0x0, ®s->rx15mask); in flexcan_chip_start()
1532 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG) in flexcan_chip_start()
1533 priv->write(0x0, ®s->rxfgmask); in flexcan_chip_start()
1536 for (i = 0; i < priv->mb_count; i++) in flexcan_chip_start()
1537 priv->write(0, ®s->rximr[i]); in flexcan_chip_start()
1539 /* On Vybrid, disable non-correctable errors interrupt and in flexcan_chip_start()
1546 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) { in flexcan_chip_start()
1549 * MECR register (step 1 - 5) in flexcan_chip_start()
1554 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_chip_start()
1556 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_chip_start()
1559 reg_mecr = priv->read(®s->mecr); in flexcan_chip_start()
1561 priv->write(reg_mecr, ®s->mecr); in flexcan_chip_start()
1566 priv->write(reg_mecr, ®s->mecr); in flexcan_chip_start()
1572 priv->write(reg_mecr, ®s->mecr); in flexcan_chip_start()
1575 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_chip_start()
1583 priv->can.state = CAN_STATE_ERROR_ACTIVE; in flexcan_chip_start()
1586 disable_irq(dev->irq); in flexcan_chip_start()
1587 priv->write(priv->reg_ctrl_default, ®s->ctrl); in flexcan_chip_start()
1588 reg_imask = priv->rx_mask | priv->tx_mask; in flexcan_chip_start()
1589 priv->write(upper_32_bits(reg_imask), ®s->imask2); in flexcan_chip_start()
1590 priv->write(lower_32_bits(reg_imask), ®s->imask1); in flexcan_chip_start()
1591 enable_irq(dev->irq); in flexcan_chip_start()
1595 priv->read(®s->mcr), priv->read(®s->ctrl)); in flexcan_chip_start()
1611 struct flexcan_regs __iomem *regs = priv->regs; in __flexcan_chip_stop()
1623 priv->write(0, ®s->imask2); in __flexcan_chip_stop()
1624 priv->write(0, ®s->imask1); in __flexcan_chip_stop()
1625 priv->write(priv->reg_ctrl_default & ~FLEXCAN_CTRL_ERR_ALL, in __flexcan_chip_stop()
1626 ®s->ctrl); in __flexcan_chip_stop()
1628 priv->can.state = CAN_STATE_STOPPED; in __flexcan_chip_stop()
1653 if ((priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES) && in flexcan_open()
1654 (priv->can.ctrlmode & CAN_CTRLMODE_FD)) { in flexcan_open()
1655 netdev_err(dev, "Three Samples mode and CAN-FD mode can't be used together\n"); in flexcan_open()
1656 return -EINVAL; in flexcan_open()
1659 err = pm_runtime_get_sync(priv->dev); in flexcan_open()
1661 pm_runtime_put_noidle(priv->dev); in flexcan_open()
1673 err = request_irq(dev->irq, flexcan_irq, IRQF_SHARED, dev->name, dev); in flexcan_open()
1677 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) in flexcan_open()
1678 priv->mb_size = sizeof(struct flexcan_mb) + CANFD_MAX_DLEN; in flexcan_open()
1680 priv->mb_size = sizeof(struct flexcan_mb) + CAN_MAX_DLEN; in flexcan_open()
1681 priv->mb_count = (sizeof(priv->regs->mb[0]) / priv->mb_size) + in flexcan_open()
1682 (sizeof(priv->regs->mb[1]) / priv->mb_size); in flexcan_open()
1684 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) in flexcan_open()
1685 priv->tx_mb_reserved = in flexcan_open()
1688 priv->tx_mb_reserved = in flexcan_open()
1690 priv->tx_mb_idx = priv->mb_count - 1; in flexcan_open()
1691 priv->tx_mb = flexcan_get_mb(priv, priv->tx_mb_idx); in flexcan_open()
1692 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx); in flexcan_open()
1694 priv->offload.mailbox_read = flexcan_mailbox_read; in flexcan_open()
1696 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP) { in flexcan_open()
1697 priv->offload.mb_first = FLEXCAN_RX_MB_OFF_TIMESTAMP_FIRST; in flexcan_open()
1698 priv->offload.mb_last = priv->mb_count - 2; in flexcan_open()
1700 priv->rx_mask = GENMASK_ULL(priv->offload.mb_last, in flexcan_open()
1701 priv->offload.mb_first); in flexcan_open()
1702 err = can_rx_offload_add_timestamp(dev, &priv->offload); in flexcan_open()
1704 priv->rx_mask = FLEXCAN_IFLAG_RX_FIFO_OVERFLOW | in flexcan_open()
1706 err = can_rx_offload_add_fifo(dev, &priv->offload, in flexcan_open()
1719 can_rx_offload_enable(&priv->offload); in flexcan_open()
1725 can_rx_offload_del(&priv->offload); in flexcan_open()
1727 free_irq(dev->irq, dev); in flexcan_open()
1733 pm_runtime_put(priv->dev); in flexcan_open()
1743 can_rx_offload_disable(&priv->offload); in flexcan_close()
1746 can_rx_offload_del(&priv->offload); in flexcan_close()
1747 free_irq(dev->irq, dev); in flexcan_close()
1751 pm_runtime_put(priv->dev); in flexcan_close()
1772 return -EOPNOTSUPP; in flexcan_set_mode()
1788 struct flexcan_regs __iomem *regs = priv->regs; in register_flexcandev()
1800 reg = priv->read(®s->ctrl); in register_flexcandev()
1801 if (priv->clk_src) in register_flexcandev()
1805 priv->write(reg, ®s->ctrl); in register_flexcandev()
1817 reg = priv->read(®s->mcr); in register_flexcandev()
1819 priv->write(reg, ®s->mcr); in register_flexcandev()
1826 reg = priv->read(®s->mcr); in register_flexcandev()
1829 err = -ENODEV; in register_flexcandev()
1841 pm_runtime_put(priv->dev); in register_flexcandev()
1860 struct device_node *np = pdev->dev.of_node; in flexcan_setup_stop_mode()
1868 return -EINVAL; in flexcan_setup_stop_mode()
1873 ret = of_property_read_u32_array(np, "fsl,stop-mode", out_val, in flexcan_setup_stop_mode()
1876 dev_dbg(&pdev->dev, "no stop-mode property\n"); in flexcan_setup_stop_mode()
1883 dev_dbg(&pdev->dev, "could not find gpr node by phandle\n"); in flexcan_setup_stop_mode()
1884 return -ENODEV; in flexcan_setup_stop_mode()
1888 priv->stm.gpr = syscon_node_to_regmap(gpr_np); in flexcan_setup_stop_mode()
1889 if (IS_ERR(priv->stm.gpr)) { in flexcan_setup_stop_mode()
1890 dev_dbg(&pdev->dev, "could not find gpr regmap\n"); in flexcan_setup_stop_mode()
1891 ret = PTR_ERR(priv->stm.gpr); in flexcan_setup_stop_mode()
1895 priv->stm.req_gpr = out_val[1]; in flexcan_setup_stop_mode()
1896 priv->stm.req_bit = out_val[2]; in flexcan_setup_stop_mode()
1898 dev_dbg(&pdev->dev, in flexcan_setup_stop_mode()
1900 gpr_np->full_name, priv->stm.req_gpr, priv->stm.req_bit); in flexcan_setup_stop_mode()
1902 device_set_wakeup_capable(&pdev->dev, true); in flexcan_setup_stop_mode()
1904 if (of_property_read_bool(np, "wakeup-source")) in flexcan_setup_stop_mode()
1905 device_set_wakeup_enable(&pdev->dev, true); in flexcan_setup_stop_mode()
1915 { .compatible = "fsl,imx8qm-flexcan", .data = &fsl_imx8qm_devtype_data, },
1916 { .compatible = "fsl,imx8mp-flexcan", .data = &fsl_imx8mp_devtype_data, },
1917 { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
1918 { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
1919 { .compatible = "fsl,imx53-flexcan", .data = &fsl_imx25_devtype_data, },
1920 { .compatible = "fsl,imx35-flexcan", .data = &fsl_imx25_devtype_data, },
1921 { .compatible = "fsl,imx25-flexcan", .data = &fsl_imx25_devtype_data, },
1922 { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
1923 { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
1924 { .compatible = "fsl,ls1021ar2-flexcan", .data = &fsl_ls1021a_r2_devtype_data, },
1925 { .compatible = "fsl,lx2160ar1-flexcan", .data = &fsl_lx2160a_r1_devtype_data, },
1931 { .name = "flexcan", .driver_data = (kernel_ulong_t)&fsl_p1010_devtype_data, },
1949 reg_xceiver = devm_regulator_get_optional(&pdev->dev, "xceiver"); in flexcan_probe()
1950 if (PTR_ERR(reg_xceiver) == -EPROBE_DEFER) in flexcan_probe()
1951 return -EPROBE_DEFER; in flexcan_probe()
1952 else if (PTR_ERR(reg_xceiver) == -ENODEV) in flexcan_probe()
1957 if (pdev->dev.of_node) { in flexcan_probe()
1958 of_property_read_u32(pdev->dev.of_node, in flexcan_probe()
1959 "clock-frequency", &clock_freq); in flexcan_probe()
1960 of_property_read_u8(pdev->dev.of_node, in flexcan_probe()
1961 "fsl,clk-source", &clk_src); in flexcan_probe()
1965 clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in flexcan_probe()
1967 dev_err(&pdev->dev, "no ipg clock defined\n"); in flexcan_probe()
1971 clk_per = devm_clk_get(&pdev->dev, "per"); in flexcan_probe()
1973 dev_err(&pdev->dev, "no per clock defined\n"); in flexcan_probe()
1981 return -ENODEV; in flexcan_probe()
1987 of_id = of_match_device(flexcan_of_match, &pdev->dev); in flexcan_probe()
1989 devtype_data = of_id->data; in flexcan_probe()
1990 } else if (platform_get_device_id(pdev)->driver_data) { in flexcan_probe()
1992 platform_get_device_id(pdev)->driver_data; in flexcan_probe()
1994 return -ENODEV; in flexcan_probe()
1997 if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) && in flexcan_probe()
1998 !(devtype_data->quirks & FLEXCAN_QUIRK_USE_OFF_TIMESTAMP)) { in flexcan_probe()
1999 dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n"); in flexcan_probe()
2000 return -EINVAL; in flexcan_probe()
2005 return -ENOMEM; in flexcan_probe()
2008 SET_NETDEV_DEV(dev, &pdev->dev); in flexcan_probe()
2010 dev->netdev_ops = &flexcan_netdev_ops; in flexcan_probe()
2011 dev->irq = irq; in flexcan_probe()
2012 dev->flags |= IFF_ECHO; in flexcan_probe()
2016 if (of_property_read_bool(pdev->dev.of_node, "big-endian") || in flexcan_probe()
2017 devtype_data->quirks & FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN) { in flexcan_probe()
2018 priv->read = flexcan_read_be; in flexcan_probe()
2019 priv->write = flexcan_write_be; in flexcan_probe()
2021 priv->read = flexcan_read_le; in flexcan_probe()
2022 priv->write = flexcan_write_le; in flexcan_probe()
2025 priv->dev = &pdev->dev; in flexcan_probe()
2026 priv->can.clock.freq = clock_freq; in flexcan_probe()
2027 priv->can.do_set_mode = flexcan_set_mode; in flexcan_probe()
2028 priv->can.do_get_berr_counter = flexcan_get_berr_counter; in flexcan_probe()
2029 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | in flexcan_probe()
2032 priv->regs = regs; in flexcan_probe()
2033 priv->clk_ipg = clk_ipg; in flexcan_probe()
2034 priv->clk_per = clk_per; in flexcan_probe()
2035 priv->clk_src = clk_src; in flexcan_probe()
2036 priv->devtype_data = devtype_data; in flexcan_probe()
2037 priv->reg_xceiver = reg_xceiver; in flexcan_probe()
2039 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) { in flexcan_probe()
2040 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | in flexcan_probe()
2042 priv->can.bittiming_const = &flexcan_fd_bittiming_const; in flexcan_probe()
2043 priv->can.data_bittiming_const = in flexcan_probe()
2046 priv->can.bittiming_const = &flexcan_bittiming_const; in flexcan_probe()
2049 pm_runtime_get_noresume(&pdev->dev); in flexcan_probe()
2050 pm_runtime_set_active(&pdev->dev); in flexcan_probe()
2051 pm_runtime_enable(&pdev->dev); in flexcan_probe()
2055 dev_err(&pdev->dev, "registering netdev failed\n"); in flexcan_probe()
2062 if (priv->devtype_data->quirks & FLEXCAN_QUIRK_SETUP_STOP_MODE) { in flexcan_probe()
2065 dev_dbg(&pdev->dev, "failed to setup stop-mode\n"); in flexcan_probe()
2071 pm_runtime_put_noidle(&pdev->dev); in flexcan_probe()
2072 pm_runtime_disable(&pdev->dev); in flexcan_probe()
2081 device_set_wakeup_enable(&pdev->dev, false); in flexcan_remove()
2082 device_set_wakeup_capable(&pdev->dev, false); in flexcan_remove()
2084 pm_runtime_disable(&pdev->dev); in flexcan_remove()
2101 enable_irq_wake(dev->irq); in flexcan_suspend()
2117 priv->can.state = CAN_STATE_SLEEPING; in flexcan_suspend()
2128 priv->can.state = CAN_STATE_ERROR_ACTIVE; in flexcan_resume()
2133 disable_irq_wake(dev->irq); in flexcan_resume()
2227 "Marc Kleine-Budde <kernel@pengutronix.de>");
2229 MODULE_DESCRIPTION("CAN port driver for flexcan based chip");